mirror of
https://github.com/FEX-Emu/FEX.git
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InstructionCountCI: enable FRINTTS when we use float->int
the relevant target hw (e.g. apple m1) supports this, so let's track with it on. Secondary_REP and VEX_map1 are duplicated to have frintts and !frintts versions so we can track the non-frintts path instead, since armv8.5 is still kinda new. the rest just enable on to minimize combinatorics. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed
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commit
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11 files changed
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@@ -1,7 +1,9 @@
|
||||
{
|
||||
"Features": {
|
||||
"Bitness": 64,
|
||||
"EnabledHostFeatures": [],
|
||||
"EnabledHostFeatures": [
|
||||
"FRINTTS"
|
||||
],
|
||||
"DisabledHostFeatures": [
|
||||
"FCMA",
|
||||
"RPRES",
|
||||
|
||||
@@ -1,7 +1,9 @@
|
||||
{
|
||||
"Features": {
|
||||
"Bitness": 64,
|
||||
"EnabledHostFeatures": [],
|
||||
"EnabledHostFeatures": [
|
||||
"FRINTTS"
|
||||
],
|
||||
"DisabledHostFeatures": [
|
||||
"SVE128",
|
||||
"SVE256",
|
||||
|
||||
@@ -3,7 +3,8 @@
|
||||
"Bitness": 64,
|
||||
"EnabledHostFeatures": [
|
||||
"FLAGM",
|
||||
"FLAGM2"
|
||||
"FLAGM2",
|
||||
"FRINTTS"
|
||||
],
|
||||
"DisabledHostFeatures": [
|
||||
"SVE128",
|
||||
|
||||
@@ -1,7 +1,9 @@
|
||||
{
|
||||
"Features": {
|
||||
"Bitness": 64,
|
||||
"EnabledHostFeatures": [],
|
||||
"EnabledHostFeatures": [
|
||||
"FRINTTS"
|
||||
],
|
||||
"DisabledHostFeatures": [
|
||||
"SVE128",
|
||||
"SVE256",
|
||||
|
||||
@@ -1,7 +1,9 @@
|
||||
{
|
||||
"Features": {
|
||||
"Bitness": 64,
|
||||
"EnabledHostFeatures": [],
|
||||
"EnabledHostFeatures": [
|
||||
"FRINTTS"
|
||||
],
|
||||
"DisabledHostFeatures": [
|
||||
"SVE128",
|
||||
"SVE256",
|
||||
|
||||
@@ -8,7 +8,8 @@
|
||||
"RPRES",
|
||||
"AFP",
|
||||
"FLAGM",
|
||||
"FLAGM2"
|
||||
"FLAGM2",
|
||||
"FRINTTS"
|
||||
]
|
||||
},
|
||||
"Instructions": {
|
||||
|
||||
@@ -1,7 +1,9 @@
|
||||
{
|
||||
"Features": {
|
||||
"Bitness": 64,
|
||||
"EnabledHostFeatures": [],
|
||||
"EnabledHostFeatures": [
|
||||
"FRINTTS"
|
||||
],
|
||||
"DisabledHostFeatures": [
|
||||
"SVE128",
|
||||
"SVE256",
|
||||
|
||||
@@ -2,7 +2,8 @@
|
||||
"Features": {
|
||||
"Bitness": 64,
|
||||
"EnabledHostFeatures": [
|
||||
"SVE128"
|
||||
"SVE128",
|
||||
"FRINTTS"
|
||||
],
|
||||
"DisabledHostFeatures": [
|
||||
"SVE256",
|
||||
|
||||
@@ -0,0 +1,142 @@
|
||||
{
|
||||
"Features": {
|
||||
"Bitness": 64,
|
||||
"EnabledHostFeatures": [
|
||||
"FRINTTS"
|
||||
],
|
||||
"DisabledHostFeatures": [
|
||||
"SVE128",
|
||||
"SVE256",
|
||||
"RPRES",
|
||||
"AFP",
|
||||
"FLAGM",
|
||||
"FLAGM2"
|
||||
]
|
||||
},
|
||||
"Instructions": {
|
||||
"cvttss2si eax, xmm0": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0xf3 0x0f 0x2c",
|
||||
"ExpectedArm64ASM": [
|
||||
"fcvtzs w20, s16",
|
||||
"mov w21, #0x80000000",
|
||||
"ldr s2, [x28, #2816]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s2, s16",
|
||||
"csel w4, w20, w21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"cvttss2si eax, dword [rbx]": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"Comment": "0xf3 0x0f 0x2c",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr s2, [x6]",
|
||||
"fcvtzs w20, s2",
|
||||
"mov w21, #0x80000000",
|
||||
"ldr s3, [x28, #2816]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s3, s2",
|
||||
"csel w4, w20, w21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"cvttss2si rax, xmm0": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": "0xf3 0x0f 0x2c",
|
||||
"ExpectedArm64ASM": [
|
||||
"fcvtzs x20, s16",
|
||||
"mov x21, #0x8000000000000000",
|
||||
"ldr s2, [x28, #2848]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s2, s16",
|
||||
"csel x4, x20, x21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"cvttss2si rax, dword [rbx]": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"Comment": "0xf3 0x0f 0x2c",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr d2, [x6]",
|
||||
"fcvtzs x20, s2",
|
||||
"mov x21, #0x8000000000000000",
|
||||
"ldr s3, [x28, #2848]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s3, s2",
|
||||
"csel x4, x20, x21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"cvtss2si eax, xmm0": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"Comment": "0xf3 0x0f 0x2d",
|
||||
"ExpectedArm64ASM": [
|
||||
"frinti s2, s16",
|
||||
"fcvtzs w20, s2",
|
||||
"mov w21, #0x80000000",
|
||||
"ldr s3, [x28, #2816]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s3, s2",
|
||||
"csel w4, w20, w21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"cvtss2si eax, dword [rbx]": {
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "0xf3 0x0f 0x2d",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr s2, [x6]",
|
||||
"frinti s2, s2",
|
||||
"fcvtzs w20, s2",
|
||||
"mov w21, #0x80000000",
|
||||
"ldr s3, [x28, #2816]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s3, s2",
|
||||
"csel w4, w20, w21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"cvtss2si rax, xmm0": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"Comment": "0xf3 0x0f 0x2d",
|
||||
"ExpectedArm64ASM": [
|
||||
"frinti s2, s16",
|
||||
"fcvtzs x20, s2",
|
||||
"mov x21, #0x8000000000000000",
|
||||
"ldr s3, [x28, #2848]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s3, s2",
|
||||
"csel x4, x20, x21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"cvtss2si rax, dword [rbx]": {
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": "0xf3 0x0f 0x2d",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr d2, [x6]",
|
||||
"frinti s2, s2",
|
||||
"fcvtzs x20, s2",
|
||||
"mov x21, #0x8000000000000000",
|
||||
"ldr s3, [x28, #2848]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s3, s2",
|
||||
"csel x4, x20, x21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"cvttps2dq xmm0, xmm1": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": "0xf3 0x0f 0x5b",
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2912]",
|
||||
"ldr q3, [x28, #2816]",
|
||||
"fcvtzs v4.4s, v17.4s",
|
||||
"fcmgt v3.4s, v3.4s, v17.4s",
|
||||
"mov v16.16b, v3.16b",
|
||||
"bsl v16.16b, v4.16b, v2.16b"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
@@ -10,7 +10,8 @@
|
||||
"RPRES",
|
||||
"AFP",
|
||||
"FLAGM",
|
||||
"FLAGM2"
|
||||
"FLAGM2",
|
||||
"FRINTTS"
|
||||
]
|
||||
},
|
||||
"Instructions": {
|
||||
|
||||
@@ -0,0 +1,295 @@
|
||||
{
|
||||
"Features": {
|
||||
"Bitness": 64,
|
||||
"EnabledHostFeatures": [
|
||||
"SVE128",
|
||||
"SVE256",
|
||||
"FRINTTS"
|
||||
],
|
||||
"DisabledHostFeatures": [
|
||||
"FCMA",
|
||||
"RPRES",
|
||||
"AFP",
|
||||
"FLAGM",
|
||||
"FLAGM2"
|
||||
]
|
||||
},
|
||||
"Instructions": {
|
||||
"vcvttss2si eax, xmm0": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x2c 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"fcvtzs w20, s16",
|
||||
"mov w21, #0x80000000",
|
||||
"ldr s2, [x28, #2816]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s2, s16",
|
||||
"csel w4, w20, w21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"vcvttss2si rax, xmm0": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x2c 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"fcvtzs x20, s16",
|
||||
"mov x21, #0x8000000000000000",
|
||||
"ldr s2, [x28, #2848]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s2, s16",
|
||||
"csel x4, x20, x21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"vcvttsd2si eax, xmm0": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": [
|
||||
"Map 1 0b11 0x2c 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"fcvtzs w20, d16",
|
||||
"mov w21, #0x80000000",
|
||||
"ldr d2, [x28, #2864]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp d2, d16",
|
||||
"csel w4, w20, w21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"vcvttsd2si rax, xmm0": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": [
|
||||
"Map 1 0b11 0x2c 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"fcvtzs x20, d16",
|
||||
"mov x21, #0x8000000000000000",
|
||||
"ldr d2, [x28, #2896]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp d2, d16",
|
||||
"csel x4, x20, x21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"vcvtss2si eax, xmm0": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x2d 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"frinti s2, s16",
|
||||
"fcvtzs w20, s2",
|
||||
"mov w21, #0x80000000",
|
||||
"ldr s3, [x28, #2816]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s3, s2",
|
||||
"csel w4, w20, w21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"vcvtss2si rax, xmm0": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x2d 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"frinti s2, s16",
|
||||
"fcvtzs x20, s2",
|
||||
"mov x21, #0x8000000000000000",
|
||||
"ldr s3, [x28, #2848]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp s3, s2",
|
||||
"csel x4, x20, x21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"vcvtsd2si eax, xmm0": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"Comment": [
|
||||
"Map 1 0b11 0x2d 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"frinti d2, d16",
|
||||
"fcvtzs x20, d2",
|
||||
"mov x21, #0x8000000000000000",
|
||||
"ldr d3, [x28, #2896]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp d3, d2",
|
||||
"csel x4, x20, x21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"vcvtsd2si rax, xmm0": {
|
||||
"ExpectedInstructionCount": 8,
|
||||
"Comment": [
|
||||
"Map 1 0b11 0x2d 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"frinti d2, d16",
|
||||
"fcvtzs x20, d2",
|
||||
"mov x21, #0x8000000000000000",
|
||||
"ldr d3, [x28, #2896]",
|
||||
"mrs x22, nzcv",
|
||||
"fcmp d3, d2",
|
||||
"csel x4, x20, x21, gt",
|
||||
"msr nzcv, x22"
|
||||
]
|
||||
},
|
||||
"vcvtps2dq xmm0, xmm1": {
|
||||
"ExpectedInstructionCount": 7,
|
||||
"Comment": [
|
||||
"Map 1 0b01 0x5b 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"frinti v2.4s, v17.4s",
|
||||
"ldr q3, [x28, #2912]",
|
||||
"ldr q4, [x28, #2816]",
|
||||
"fcvtzs v5.4s, v2.4s",
|
||||
"fcmgt v2.4s, v4.4s, v2.4s",
|
||||
"mov v16.16b, v2.16b",
|
||||
"bsl v16.16b, v5.16b, v3.16b"
|
||||
]
|
||||
},
|
||||
"vcvtps2dq ymm0, ymm1": {
|
||||
"ExpectedInstructionCount": 13,
|
||||
"Comment": [
|
||||
"Map 1 0b01 0x5b 256-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"frinti z2.s, p7/m, z17.s",
|
||||
"ldr x0, [x28, #2024]",
|
||||
"ld1b {z3.b}, p7/z, [x0]",
|
||||
"ldr x0, [x28, #1976]",
|
||||
"ld1b {z4.b}, p7/z, [x0]",
|
||||
"fcvtzs z5.s, p7/m, z2.s",
|
||||
"fcmgt p0.s, p7/z, z4.s, z2.s",
|
||||
"not z0.s, p0/m, z4.s",
|
||||
"movprfx z2.s, p0/z, z4.s",
|
||||
"orr z2.s, p0/m, z2.s, z0.s",
|
||||
"movprfx z0, z5",
|
||||
"bsl z0.d, z0.d, z3.d, z2.d",
|
||||
"mov z16.d, z0.d"
|
||||
]
|
||||
},
|
||||
"vcvttps2dq xmm0, xmm1": {
|
||||
"ExpectedInstructionCount": 6,
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x5b 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2912]",
|
||||
"ldr q3, [x28, #2816]",
|
||||
"fcvtzs v4.4s, v17.4s",
|
||||
"fcmgt v3.4s, v3.4s, v17.4s",
|
||||
"mov v16.16b, v3.16b",
|
||||
"bsl v16.16b, v4.16b, v2.16b"
|
||||
]
|
||||
},
|
||||
"vcvttps2dq ymm0, ymm1": {
|
||||
"ExpectedInstructionCount": 12,
|
||||
"Comment": [
|
||||
"Map 1 0b10 0x5b 256-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr x0, [x28, #2024]",
|
||||
"ld1b {z2.b}, p7/z, [x0]",
|
||||
"ldr x0, [x28, #1976]",
|
||||
"ld1b {z3.b}, p7/z, [x0]",
|
||||
"fcvtzs z4.s, p7/m, z17.s",
|
||||
"fcmgt p0.s, p7/z, z3.s, z17.s",
|
||||
"not z0.s, p0/m, z3.s",
|
||||
"movprfx z3.s, p0/z, z3.s",
|
||||
"orr z3.s, p0/m, z3.s, z0.s",
|
||||
"movprfx z0, z4",
|
||||
"bsl z0.d, z0.d, z2.d, z3.d",
|
||||
"mov z16.d, z0.d"
|
||||
]
|
||||
},
|
||||
"vcvttpd2dq xmm0, xmm1": {
|
||||
"ExpectedInstructionCount": 9,
|
||||
"Comment": [
|
||||
"Map 1 0b01 0xe6 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr d2, [x28, #2912]",
|
||||
"ldr q3, [x28, #2864]",
|
||||
"fcvtzs z4.s, p6/m, z17.d",
|
||||
"uzp1 z4.s, z4.s, z4.s",
|
||||
"mov v4.8b, v4.8b",
|
||||
"fcmgt v3.2d, v3.2d, v17.2d",
|
||||
"shrn v3.2s, v3.2d, #32",
|
||||
"mov v16.16b, v3.16b",
|
||||
"bsl v16.16b, v4.16b, v2.16b"
|
||||
]
|
||||
},
|
||||
"vcvttpd2dq xmm0, ymm1": {
|
||||
"ExpectedInstructionCount": 15,
|
||||
"Comment": [
|
||||
"Map 1 0b01 0xe6 256-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"ldr q2, [x28, #2912]",
|
||||
"ldr x0, [x28, #2000]",
|
||||
"ld1b {z3.b}, p7/z, [x0]",
|
||||
"fcvtzs z4.s, p7/m, z17.d",
|
||||
"uzp1 z4.s, z4.s, z4.s",
|
||||
"mov v4.16b, v4.16b",
|
||||
"fcmgt p0.d, p7/z, z3.d, z17.d",
|
||||
"not z0.d, p0/m, z3.d",
|
||||
"movprfx z3.d, p0/z, z3.d",
|
||||
"orr z3.d, p0/m, z3.d, z0.d",
|
||||
"shrnb z3.s, z3.d, #32",
|
||||
"uzp1 z3.s, z3.s, z3.s",
|
||||
"movprfx z0, z4",
|
||||
"bsl z0.d, z0.d, z2.d, z3.d",
|
||||
"mov z16.d, z0.d"
|
||||
]
|
||||
},
|
||||
"vcvtpd2dq xmm0, xmm1": {
|
||||
"ExpectedInstructionCount": 10,
|
||||
"Comment": [
|
||||
"Map 1 0b11 0xe6 128-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"frinti v2.2d, v17.2d",
|
||||
"ldr d3, [x28, #2912]",
|
||||
"ldr q4, [x28, #2864]",
|
||||
"fcvtzs z5.s, p6/m, z2.d",
|
||||
"uzp1 z5.s, z5.s, z5.s",
|
||||
"mov v5.8b, v5.8b",
|
||||
"fcmgt v2.2d, v4.2d, v2.2d",
|
||||
"shrn v2.2s, v2.2d, #32",
|
||||
"mov v16.16b, v2.16b",
|
||||
"bsl v16.16b, v5.16b, v3.16b"
|
||||
]
|
||||
},
|
||||
"vcvtpd2dq xmm0, ymm1": {
|
||||
"ExpectedInstructionCount": 16,
|
||||
"Comment": [
|
||||
"Map 1 0b11 0xe6 256-bit"
|
||||
],
|
||||
"ExpectedArm64ASM": [
|
||||
"frinti z2.d, p7/m, z17.d",
|
||||
"ldr q3, [x28, #2912]",
|
||||
"ldr x0, [x28, #2000]",
|
||||
"ld1b {z4.b}, p7/z, [x0]",
|
||||
"fcvtzs z5.s, p7/m, z2.d",
|
||||
"uzp1 z5.s, z5.s, z5.s",
|
||||
"mov v5.16b, v5.16b",
|
||||
"fcmgt p0.d, p7/z, z4.d, z2.d",
|
||||
"not z0.d, p0/m, z4.d",
|
||||
"movprfx z2.d, p0/z, z4.d",
|
||||
"orr z2.d, p0/m, z2.d, z0.d",
|
||||
"shrnb z2.s, z2.d, #32",
|
||||
"uzp1 z2.s, z2.s, z2.s",
|
||||
"movprfx z0, z5",
|
||||
"bsl z0.d, z0.d, z3.d, z2.d",
|
||||
"mov z16.d, z0.d"
|
||||
]
|
||||
}
|
||||
}
|
||||
}
|
||||
Reference in new issue
Block a user