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https://github.com/FEX-Emu/FEX.git
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Merge pull request #3287 from Sonicadvance1/remove_config_threads
Config: Removes Threads option
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9 files changed
+25
-79
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@@ -321,16 +321,6 @@ namespace DefaultValues {
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Meta->Load();
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// Do configuration option fix ups after everything is reloaded
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{
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// Always fix up the number of threads and create the configuration
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// Otherwise the application could receive zero as the number of threads
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FEX_CONFIG_OPT(Cores, THREADS);
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if (Cores == 0) {
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// When the number of emulated CPU cores is zero then auto detect
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FEXCore::Config::EraseSet(FEXCore::Config::CONFIG_THREADS, fextl::fmt::format("{}", FEXCore::CPUInfo::CalculateNumberOfCPUs()));
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}
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}
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if (FEXCore::Config::Exists(FEXCore::Config::CONFIG_CORE)) {
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// Sanitize Core option
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FEX_CONFIG_OPT(Core, CORE);
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@@ -31,15 +31,6 @@
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"Maximum number of instruction to store in a block"
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]
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},
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"Threads": {
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"Type": "uint32",
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"Default": "0",
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"ShortArg": "T",
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"Desc": [
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"Number of physical hardware threads to tell the process we have.",
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"0 will auto detect."
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]
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},
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"CacheObjectCodeCompilation": {
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"Type": "uint32",
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"Default": "FEXCore::Config::ConfigObjectCodeHandler::CONFIG_NONE",
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@@ -106,11 +106,10 @@ static uint32_t GetCycleCounterFrequency() {
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}
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void CPUIDEmu::SetupHostHybridFlag() {
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size_t CPUs = FEXCore::CPUInfo::CalculateNumberOfCPUs();
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PerCPUData.resize(CPUs);
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PerCPUData.resize(Cores);
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uint64_t MIDR{};
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for (size_t i = 0; i < CPUs; ++i) {
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for (size_t i = 0; i < Cores; ++i) {
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std::error_code ec{};
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fextl::string MIDRPath = fextl::fmt::format("/sys/devices/system/cpu/cpu{}/regs/identification/midr_el1", i);
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@@ -218,7 +217,7 @@ void CPUIDEmu::SetupHostHybridFlag() {
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fextl::vector<const CPUMIDR*> LittleCores;
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// Separate CPU cores out to big or little selected
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for (size_t i = 0; i < CPUs; ++i) {
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for (size_t i = 0; i < Cores; ++i) {
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uint32_t MIDR = PerCPUData[i].MIDR;
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auto MIDROption = FindDefinedMIDR(MIDR);
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if (MIDROption) {
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@@ -334,7 +333,7 @@ void CPUIDEmu::SetupHostHybridFlag() {
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}
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else {
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// If we aren't hybrid then just claim everything is big
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for (size_t i = 0; i < CPUs; ++i) {
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for (size_t i = 0; i < Cores; ++i) {
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uint32_t MIDR = PerCPUData[i].MIDR;
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auto MIDROption = FindDefinedMIDR(MIDR);
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@@ -380,7 +379,6 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_0h(uint32_t Leaf) const {
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// Processor Info and Features bits
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FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) const {
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FEXCore::CPUID::FunctionResults Res{};
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uint32_t CoreCount = Cores();
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// Hypervisor bit is normally set but some applications have issues with it.
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uint32_t Hypervisor = HideHypervisorBit() ? 0 : 1;
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@@ -389,7 +387,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_01h(uint32_t Leaf) const {
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Res.ebx = 0 | // Brand index
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(8 << 8) | // Cache line size in bytes
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(CoreCount << 16) | // Number of addressable IDs for the logical cores in the physical CPU
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(Cores << 16) | // Number of addressable IDs for the logical cores in the physical CPU
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(0 << 24); // Local APIC ID
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Res.ecx =
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@@ -496,7 +494,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_04h(uint32_t Leaf) const {
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if (Leaf == 0) {
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// Report L1D
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uint32_t CoreCount = Cores() - 1;
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uint32_t CoreCount = Cores - 1;
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Res.eax = CacheType_Data | // Cache type
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(0b001 << 5) | // Cache level
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@@ -520,7 +518,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_04h(uint32_t Leaf) const {
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}
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else if (Leaf == 1) {
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// Report L1I
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uint32_t CoreCount = Cores() - 1;
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uint32_t CoreCount = Cores - 1;
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Res.eax = CacheType_Instruction | // Cache type
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(0b001 << 5) | // Cache level
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@@ -544,7 +542,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_04h(uint32_t Leaf) const {
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}
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else if (Leaf == 2) {
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// Report L2
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uint32_t CoreCount = Cores() - 1;
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uint32_t CoreCount = Cores - 1;
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Res.eax = CacheType_Unified | // Cache type
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(0b010 << 5) | // Cache level
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@@ -568,7 +566,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_04h(uint32_t Leaf) const {
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}
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else if (Leaf == 3) {
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// Report L3
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uint32_t CoreCount = Cores() - 1;
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uint32_t CoreCount = Cores - 1;
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Res.eax = CacheType_Unified | // Cache type
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(0b011 << 5) | // Cache level
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@@ -1070,7 +1068,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_0008h(uint32_t Leaf) con
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(0 << 1) | // IRPerf: Instructions retired count support
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(CTX->HostFeatures.SupportsCLZERO << 0); // CLZERO support
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uint32_t CoreCount = Cores() - 1;
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uint32_t CoreCount = Cores - 1;
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Res.ecx =
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(0 << 16) | // PerfTscSize: Performance timestamp count size
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((uint32_t)std::log2(CoreCount + 1) << 12) | // ApicIdSize: Number of bits in ApicID
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@@ -1168,7 +1166,7 @@ FEXCore::CPUID::FunctionResults CPUIDEmu::Function_8000_001Dh(uint32_t Leaf) con
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}
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else if (Leaf == 3) {
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// Report L3
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uint32_t CoreCount = Cores() - 1;
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uint32_t CoreCount = Cores - 1;
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Res.eax = CacheType_Unified | // Cache type
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(0b011 << 5) | // Cache level
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@@ -1209,6 +1207,7 @@ FEXCore::CPUID::XCRResults CPUIDEmu::XCRFunction_0h() const {
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void CPUIDEmu::Init(FEXCore::Context::ContextImpl *ctx) {
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CTX = ctx;
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Cores = FEXCore::CPUInfo::CalculateNumberOfCPUs();
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// Setup some state tracking
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SetupHostHybridFlag();
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@@ -113,7 +113,7 @@ public:
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private:
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FEXCore::Context::ContextImpl *CTX;
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bool Hybrid{};
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FEX_CONFIG_OPT(Cores, THREADS);
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uint32_t Cores{};
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FEX_CONFIG_OPT(HideHypervisorBit, HIDEHYPERVISORBIT);
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// XFEATURE_ENABLED_MASK
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@@ -14,6 +14,7 @@ $end_info$
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#include <FEXCore/Core/CodeLoader.h>
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#include <FEXCore/Core/Context.h>
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#include <FEXCore/Core/CPUID.h>
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#include <FEXCore/Utils/CPUInfo.h>
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#include <FEXCore/Utils/LogManager.h>
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#include <FEXCore/fextl/fmt.h>
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#include <FEXCore/fextl/string.h>
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@@ -621,12 +622,13 @@ namespace FEX::EmulatedFile {
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}
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EmulatedFDManager::EmulatedFDManager(FEXCore::Context::Context *ctx)
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: CTX {ctx} {
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: CTX {ctx}
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, ThreadsConfig { FEXCore::CPUInfo::CalculateNumberOfCPUs() } {
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FDReadCreators["/proc/cpuinfo"] = [&](FEXCore::Context::Context *ctx, int32_t fd, const char *pathname, int32_t flags, mode_t mode) -> int32_t {
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// Only allow a single thread to initialize the cpu_info.
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// Jit in-case multiple threads try to initialize at once.
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// Check if deferred cpuinfo initialization has occured.
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std::call_once(cpu_info_initialized, [&]() { cpu_info = GenerateCPUInfo(ctx, ThreadsConfig()); });
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std::call_once(cpu_info_initialized, [&]() { cpu_info = GenerateCPUInfo(ctx, ThreadsConfig); });
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int FD = GenTmpFD();
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write(FD, (void*)&cpu_info.at(0), cpu_info.size());
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@@ -702,9 +704,8 @@ namespace FEX::EmulatedFile {
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fextl::string procCmdLine = fextl::fmt::format("/proc/{}/cmdline", getpid());
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FDReadCreators[procCmdLine] = cmdline_handler;
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uint64_t CPUCores = ThreadsConfig();
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if (CPUCores > 1) {
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cpus_online = fextl::fmt::format("0-{}", CPUCores - 1);
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if (ThreadsConfig > 1) {
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cpus_online = fextl::fmt::format("0-{}", ThreadsConfig - 1);
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}
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else {
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cpus_online = "0";
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@@ -34,6 +34,6 @@ namespace FEX::EmulatedFile {
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fextl::unordered_map<fextl::string, FDReadStringFunc> FDReadCreators;
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static int32_t ProcAuxv(FEXCore::Context::Context* ctx, int32_t fd, const char* pathname, int32_t flags, mode_t mode);
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FEX_CONFIG_OPT(ThreadsConfig, THREADS);
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const uint32_t ThreadsConfig;
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};
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}
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@@ -175,7 +175,6 @@ public:
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FEX_CONFIG_OPT(IsInterpreterInstalled, INTERPRETER_INSTALLED);
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FEX_CONFIG_OPT(Filename, APP_FILENAME);
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FEX_CONFIG_OPT(RootFSPath, ROOTFS);
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FEX_CONFIG_OPT(ThreadsConfig, THREADS);
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FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
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FEX_CONFIG_OPT(SMCChecks, SMCCHECKS);
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@@ -89,21 +89,8 @@ namespace FEX::HLE {
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REGISTER_SYSCALL_IMPL_FLAGS(getcpu, SyscallFlags::OPTIMIZETHROUGH | SyscallFlags::NOSYNCSTATEONENTRY,
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[](FEXCore::Core::CpuStateFrame *Frame, unsigned *cpu, unsigned *node, struct getcpu_cache *tcache) -> uint64_t {
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uint32_t LocalCPU{};
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uint32_t LocalNode{};
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// tcache is ignored
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uint64_t Result = ::syscall(SYSCALL_DEF(getcpu), cpu ? &LocalCPU : nullptr, node ? &LocalNode : nullptr, nullptr);
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if (Result == 0) {
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if (cpu) {
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// Ensure we don't return a number over our number of emulated cores
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*cpu = LocalCPU % FEX::HLE::_SyscallHandler->ThreadsConfig();
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}
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if (node) {
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// Just claim we are part of node zero
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*node = 0;
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}
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}
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uint64_t Result = ::syscall(SYSCALL_DEF(getcpu), cpu, node, nullptr);
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SYSCALL_ERRNO();
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});
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@@ -80,35 +80,14 @@ namespace FEX::HLE {
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REGISTER_SYSCALL_IMPL_FLAGS(sched_setaffinity, SyscallFlags::OPTIMIZETHROUGH | SyscallFlags::NOSYNCSTATEONENTRY | SyscallFlags::NOSIDEEFFECTS,
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[](FEXCore::Core::CpuStateFrame *Frame, pid_t pid, size_t cpusetsize, const unsigned long *mask) -> uint64_t {
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return 0;
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uint64_t Result = ::syscall(SYSCALL_DEF(sched_setaffinity), pid, cpusetsize, mask);
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SYSCALL_ERRNO();
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});
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REGISTER_SYSCALL_IMPL_FLAGS(sched_getaffinity, SyscallFlags::OPTIMIZETHROUGH | SyscallFlags::NOSYNCSTATEONENTRY,
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[](FEXCore::Core::CpuStateFrame *Frame, pid_t pid, size_t cpusetsize, unsigned char *mask) -> uint64_t {
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uint64_t Cores = FEX::HLE::_SyscallHandler->ThreadsConfig();
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// Bytes need to round up to size of uint64_t
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uint64_t Bytes = FEXCore::AlignUp(Cores, sizeof(uint64_t));
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// cpusetsize needs to be 8byte aligned
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if (cpusetsize & (sizeof(uint64_t) - 1)) {
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return -EINVAL;
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}
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// If we don't have enough bytes to store the resulting structure
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// then we need to return -EINVAL
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if (cpusetsize < Bytes) {
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return -EINVAL;
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}
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memset(mask, 0, Bytes);
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for (uint64_t i = 0; i < Cores; ++i) {
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mask[i / 8] |= (1 << (i % 8));
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}
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// Returns the number of bytes written in to mask
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return Bytes;
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uint64_t Result = ::syscall(SYSCALL_DEF(sched_getaffinity), pid, cpusetsize, mask);
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SYSCALL_ERRNO();
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});
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REGISTER_SYSCALL_IMPL_PASS_FLAGS(sched_setattr, SyscallFlags::OPTIMIZETHROUGH | SyscallFlags::NOSYNCSTATEONENTRY,
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