mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 13:00:15 +02:00
Merge pull request #3252 from Sonicadvance1/fix_fillstaticregisters
ARMEmitter: Fix GPR fill mask in `FillStaticRegs`
This commit is contained in:
7 files changed
+3433
-3423
No files matched your search
@@ -663,11 +663,23 @@ void Arm64Emitter::SpillStaticRegs(FEXCore::ARMEmitter::Register TmpReg, bool FP
|
||||
}
|
||||
|
||||
void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRFillMask) {
|
||||
FEXCore::ARMEmitter::Register TmpReg = FEXCore::ARMEmitter::Reg::r0;
|
||||
LOGMAN_THROW_A_FMT(GPRFillMask != 0, "Must fill at least 1 GPR for a temp");
|
||||
bool FoundRegister{};
|
||||
for (auto Reg : StaticRegisters) {
|
||||
if (((1U << Reg.Idx()) & GPRFillMask)) {
|
||||
TmpReg = Reg;
|
||||
FoundRegister = true;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
LOGMAN_THROW_A_FMT(FoundRegister, "Didn't have an SRA register to use as a temporary while spilling!");
|
||||
|
||||
#ifndef VIXL_SIMULATOR
|
||||
if (EmitterCTX->HostFeatures.SupportsAFP) {
|
||||
// Enable AFP features when filling JIT state.
|
||||
LOGMAN_THROW_A_FMT(GPRFillMask != 0, "Must fill at least 1 GPR for a temp");
|
||||
auto TmpReg = StaticRegisters[FindFirstSetBit(GPRFillMask)];
|
||||
mrs(TmpReg, ARMEmitter::SystemRegister::FPCR);
|
||||
|
||||
// Enable FPCR.NEP and FPCR.AH
|
||||
@@ -710,8 +722,6 @@ void Arm64Emitter::FillStaticRegs(bool FPRs, uint32_t GPRFillMask, uint32_t FPRF
|
||||
if (GPRFillMask && FPRFillMask == ~0U) {
|
||||
// Optimize the common case where we can fill four registers per instruction.
|
||||
// Use one of the filling static registers before we fill it.
|
||||
auto TmpReg = StaticRegisters[FindFirstSetBit(GPRFillMask)];
|
||||
|
||||
// Load the sse offset in to the temporary register
|
||||
add(ARMEmitter::Size::i64Bit, TmpReg, STATE.R(), offsetof(FEXCore::Core::CpuStateFrame, State.xmm.sse.data[0][0]));
|
||||
for (size_t i = 0; i < StaticFPRegisters.size(); i += 4) {
|
||||
|
||||
@@ -42,11 +42,11 @@
|
||||
"ldr x2, [x28, #1112]",
|
||||
"mov w1, w5",
|
||||
"blr x2",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
|
||||
+1535
-1535
File diff suppressed because it is too large.
Load diff
@@ -2566,11 +2566,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -2634,11 +2634,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -2699,11 +2699,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -2773,11 +2773,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -2867,11 +2867,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -2957,11 +2957,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3030,11 +3030,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3110,11 +3110,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3153,11 +3153,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3234,11 +3234,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3291,11 +3291,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3350,11 +3350,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -4469,11 +4469,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -4534,11 +4534,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7149,11 +7149,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7200,11 +7200,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7251,11 +7251,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7302,11 +7302,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7353,11 +7353,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7404,11 +7404,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7455,11 +7455,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7507,11 +7507,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7625,11 +7625,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7676,11 +7676,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7727,11 +7727,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7778,11 +7778,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7829,11 +7829,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7880,11 +7880,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7931,11 +7931,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7982,11 +7982,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -10740,11 +10740,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -10786,11 +10786,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -10843,11 +10843,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -10889,11 +10889,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
|
||||
@@ -42,11 +42,11 @@
|
||||
"ldr x2, [x28, #1112]",
|
||||
"mov w1, w5",
|
||||
"blr x2",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
|
||||
+1535
-1535
File diff suppressed because it is too large.
Load diff
@@ -2565,11 +2565,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -2633,11 +2633,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -2698,11 +2698,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -2772,11 +2772,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -2866,11 +2866,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -2956,11 +2956,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3029,11 +3029,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3109,11 +3109,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3152,11 +3152,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3233,11 +3233,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3290,11 +3290,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -3349,11 +3349,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -4468,11 +4468,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -4533,11 +4533,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7148,11 +7148,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7199,11 +7199,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7250,11 +7250,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7301,11 +7301,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7352,11 +7352,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7403,11 +7403,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7454,11 +7454,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7506,11 +7506,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7624,11 +7624,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7675,11 +7675,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7726,11 +7726,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7777,11 +7777,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7828,11 +7828,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7879,11 +7879,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7930,11 +7930,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -7981,11 +7981,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -10739,11 +10739,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -10785,11 +10785,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -10842,11 +10842,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
@@ -10888,11 +10888,11 @@
|
||||
"ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",
|
||||
"ld1 {v12.2d, v13.2d, v14.2d, v15.2d}, [sp], #64",
|
||||
"ldr x30, [sp], #16",
|
||||
"add x5, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x5], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x5], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x5], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x5], #64",
|
||||
"add x4, x28, #0xc0 (192)",
|
||||
"ld1 {v16.2d, v17.2d, v18.2d, v19.2d}, [x4], #64",
|
||||
"ld1 {v20.2d, v21.2d, v22.2d, v23.2d}, [x4], #64",
|
||||
"ld1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x4], #64",
|
||||
"ld1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x4], #64",
|
||||
"ldp x4, x5, [x28, #8]",
|
||||
"ldp x6, x7, [x28, #24]",
|
||||
"ldp x8, x9, [x28, #40]",
|
||||
|
||||
Reference in new issue
Block a user