Merge pull request #4719 from Sonicadvance1/runtime_mode_switch_take2

Runtime mode switch take 2

FEXCore/Source/Interface/Context/Context.h

@@ -290,10 +290,6 @@ public:
   uintptr_t CompileBlock(FEXCore::Core::CpuStateFrame* Frame, uint64_t GuestRIP, uint64_t MaxInst = 0);
   uintptr_t CompileSingleStep(FEXCore::Core::CpuStateFrame* Frame, uint64_t GuestRIP);
 
-  IR::OpSize GetGPROpSize() const {
-    return Config.Is64BitMode ? IR::OpSize::i64Bit : IR::OpSize::i32Bit;
-  }
-
   FEXCore::JITSymbols Symbols;
 
   FEXCore::Utils::PooledAllocatorVirtual OpDispatcherAllocator;

FEXCore/Source/Interface/Core/Core.cpp

@@ -441,6 +441,22 @@ ContextImpl::CreateThread(uint64_t InitialRIP, uint64_t StackPointer, const FEXC
   Thread->CurrentFrame->State.gregs[X86State::REG_RSP] = StackPointer;
   Thread->CurrentFrame->State.rip = InitialRIP;
 
+  // Set up default code segment.
+  // Default code segment indexes match the numbers that the Linux kernel uses.
+  Thread->CurrentFrame->State.cs_idx = 6 << 3;
+  auto &GDT = Thread->CurrentFrame->State.gdt[Thread->CurrentFrame->State.cs_idx >> 3];
+  Thread->CurrentFrame->State.SetGDTBase(&GDT, 0);
+  Thread->CurrentFrame->State.SetGDTLimit(&GDT, 0xF'FFFFU);
+
+  if (Config.Is64BitMode) {
+    GDT.L = 1; // L = Long Mode = 64-bit
+    GDT.D = 0; // D = Default Operand SIze = Reserved
+  }
+  else {
+    GDT.L = 0; // L = Long Mode = 32-bit
+    GDT.D = 1; // D = Default Operand Size = 32-bit
+  }
+
   // Copy over the new thread state to the new object
   if (NewThreadState) {
     memcpy(&Thread->CurrentFrame->State, NewThreadState, sizeof(FEXCore::Core::CPUState));
@@ -558,14 +574,14 @@ ContextImpl::GenerateIR(FEXCore::Core::InternalThreadState* Thread, uint64_t Gue
     bool HadDispatchError {false};
     bool HadInvalidInst {false};
 
-    Thread->FrontendDecoder->DecodeInstructionsAtEntry(GuestCode, GuestRIP, MaxInst);
+    Thread->FrontendDecoder->DecodeInstructionsAtEntry(Thread, GuestCode, GuestRIP, MaxInst);
 
     auto BlockInfo = Thread->FrontendDecoder->GetDecodedBlockInfo();
     auto CodeBlocks = &BlockInfo->Blocks;
 
-    Thread->OpDispatcher->BeginFunction(GuestRIP, CodeBlocks, BlockInfo->TotalInstructionCount);
+    Thread->OpDispatcher->BeginFunction(GuestRIP, CodeBlocks, BlockInfo->TotalInstructionCount, BlockInfo->Is64BitMode);
 
-    const auto GPRSize = GetGPROpSize();
+    const auto GPRSize = Thread->OpDispatcher->GetGPROpSize();
 
     for (size_t j = 0; j < CodeBlocks->size(); ++j) {
       const FEXCore::Frontend::Decoder::DecodedBlocks& Block = CodeBlocks->at(j);
@@ -1021,7 +1037,7 @@ void ContextImpl::AddThunkTrampolineIRHandler(uintptr_t Entrypoint, uintptr_t Gu
       IRHeader.first->Blocks = emit->WrapNode(Block);
       emit->SetCurrentCodeBlock(Block);
 
-      const auto GPRSize = GetGPROpSize();
+      const auto GPRSize = this->Config.Is64BitMode ? IR::OpSize::i64Bit : IR::OpSize::i32Bit;
 
       if (GPRSize == IR::OpSize::i64Bit) {
         IR::Ref R = emit->_StoreRegister(emit->Constant(Entrypoint), GPRSize);

FEXCore/Source/Interface/Core/Frontend.cpp

@@ -333,7 +333,7 @@ bool Decoder::NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op,
   uint8_t DestSize {};
   const bool HasWideningDisplacement =
     (FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_WIDENING_SIZE_LAST) != 0 ||
-    (Options.w && CTX->Config.Is64BitMode);
+    (Options.w && BlockInfo.Is64BitMode);
   const bool HasNarrowingDisplacement =
     (FEXCore::X86Tables::DecodeFlags::GetOpAddr(DecodeInst->Flags, 0) & FEXCore::X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST) != 0;
 
@@ -351,7 +351,7 @@ bool Decoder::NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op,
   const bool HasMODRM = !!(Info->Flags & FEXCore::X86Tables::InstFlags::FLAGS_MODRM);
 
   const bool HasREX = !!(DecodeInst->Flags & DecodeFlags::FLAG_REX_PREFIX);
-  const bool Has16BitAddressing = !CTX->Config.Is64BitMode && DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE;
+  const bool Has16BitAddressing = !BlockInfo.Is64BitMode && DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE;
 
   if (Options.w && (Info->Flags & InstFlags::FLAGS_REX_W_0)) {
     return false;
@@ -412,7 +412,7 @@ bool Decoder::NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op,
       // If the default operating mode is 32bit and we have the operand size flag then the operating size drops to 16bit
       DecodeInst->Flags |= DecodeFlags::GenSizeDstSize(DecodeFlags::SIZE_16BIT);
       DestSize = 2;
-    } else if ((HasXMMDst || HasMMDst || CTX->Config.Is64BitMode) &&
+    } else if ((HasXMMDst || HasMMDst || BlockInfo.Is64BitMode) &&
                (HasWideningDisplacement || DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BIT ||
                 DstSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BITDEF)) {
       DecodeInst->Flags |= DecodeFlags::GenSizeDstSize(DecodeFlags::SIZE_64BIT);
@@ -441,7 +441,7 @@ bool Decoder::NormalOp(const FEXCore::X86Tables::X86InstInfo* Info, uint16_t Op,
       // See table 1-2. Operand-Size Overrides for this decoding
       // If the default operating mode is 32bit and we have the operand size flag then the operating size drops to 16bit
       DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_16BIT);
-    } else if ((HasXMMSrc || HasMMSrc || CTX->Config.Is64BitMode) &&
+    } else if ((HasXMMSrc || HasMMSrc || BlockInfo.Is64BitMode) &&
                (HasWideningDisplacement || SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BIT ||
                 SrcSizeFlag == FEXCore::X86Tables::InstFlags::SIZE_64BITDEF)) {
       DecodeInst->Flags |= DecodeFlags::GenSizeSrcSize(DecodeFlags::SIZE_64BIT);
@@ -711,7 +711,7 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
     DecodedHeader options {};
 
     if ((Byte1 & 0b10000000) == 0) {
-      if (!CTX->Config.Is64BitMode) {
+      if (!BlockInfo.Is64BitMode) {
         return false;
       }
 
@@ -730,12 +730,12 @@ bool Decoder::NormalOpHeader(const FEXCore::X86Tables::X86InstInfo* Info, uint16
       options.w = (Byte2 & 0b10000000) != 0;
       options.L = (Byte2 & 0b100) != 0;
       if ((Byte1 & 0b01000000) == 0) {
-        if (!CTX->Config.Is64BitMode) {
+        if (!BlockInfo.Is64BitMode) {
           return false;
         }
         DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_X;
       }
-      if (CTX->Config.Is64BitMode && (Byte1 & 0b00100000) == 0) {
+      if (BlockInfo.Is64BitMode && (Byte1 & 0b00100000) == 0) {
         DecodeInst->Flags |= DecodeFlags::FLAG_REX_XGPR_B;
       }
       if (options.w) {
@@ -808,7 +808,7 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
           FEXCore::X86Tables::ModRMDecoded ModRM;
           ModRM.Hex = DecodeInst->ModRM;
 
-          const bool Has16BitAddressing = !CTX->Config.Is64BitMode && DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE;
+          const bool Has16BitAddressing = !BlockInfo.Is64BitMode && DecodeInst->Flags & DecodeFlags::FLAG_ADDRESS_SIZE;
 
           // All 3DNow! instructions have the second argument as the rm handler
           // We need to decode it upfront to get the displacement out of the way
@@ -917,17 +917,17 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
       DecodeInst->Flags |= DecodeFlags::FLAG_ADDRESS_SIZE;
       break;
     case 0x26: // ES legacy prefix
-      if (!CTX->Config.Is64BitMode) {
+      if (!BlockInfo.Is64BitMode) {
         DecodeInst->Flags |= DecodeFlags::FLAG_ES_PREFIX;
       }
       break;
     case 0x2E: // CS legacy prefix
-      if (!CTX->Config.Is64BitMode) {
+      if (!BlockInfo.Is64BitMode) {
         DecodeInst->Flags |= DecodeFlags::FLAG_CS_PREFIX;
       }
       break;
     case 0x36: // SS legacy prefix
-      if (!CTX->Config.Is64BitMode) {
+      if (!BlockInfo.Is64BitMode) {
         DecodeInst->Flags |= DecodeFlags::FLAG_SS_PREFIX;
       }
       break;
@@ -935,7 +935,7 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
       // Annoyingly GCC generates NOP ops with these prefixes
       // Just ignore them for now
       // eg. 66 2e 0f 1f 84 00 00 00 00 00 nop    WORD PTR cs:[rax+rax*1+0x0]
-      if (!CTX->Config.Is64BitMode) {
+      if (!BlockInfo.Is64BitMode) {
         DecodeInst->Flags |= DecodeFlags::FLAG_DS_PREFIX;
       }
       break;
@@ -962,7 +962,7 @@ bool Decoder::DecodeInstructionImpl(uint64_t PC) {
         auto Info = &FEXCore::X86Tables::BaseOps[Op];
 
         if (Info->Type == FEXCore::X86Tables::TYPE_REX_PREFIX) {
-          if (!CTX->Config.Is64BitMode) {
+          if (!BlockInfo.Is64BitMode) {
             return false;
           }
           DecodeInst->Flags |= DecodeFlags::FLAG_REX_PREFIX;
@@ -1029,7 +1029,7 @@ void Decoder::BranchTargetInMultiblockRange() {
 
   // If the RIP setting is conditional AND within our symbol range then it can be considered for multiblock
   uint64_t TargetRIP = 0;
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   bool Conditional = true;
   const auto InstEnd = DecodeInst->PC + DecodeInst->InstSize;
 
@@ -1102,7 +1102,7 @@ bool Decoder::InstCanContinue() const {
   }
 
   uint64_t TargetRIP = 0;
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   if (DecodeInst->OP == 0xE8) { // Call - immediate target
     const uint64_t NextRIP = DecodeInst->PC + DecodeInst->InstSize;
@@ -1194,7 +1194,7 @@ const uint8_t* Decoder::AdjustAddrForSpecialRegion(const uint8_t* _InstStream, u
   return _InstStream - EntryPoint + RIP;
 }
 
-void Decoder::DecodeInstructionsAtEntry(const uint8_t* _InstStream, uint64_t PC, uint64_t MaxInst) {
+void Decoder::DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState *Thread, const uint8_t* _InstStream, uint64_t PC, uint64_t MaxInst) {
   FEXCORE_PROFILE_SCOPED("DecodeInstructions");
   BlockInfo.TotalInstructionCount = 0;
   BlockInfo.Blocks.clear();
@@ -1205,6 +1205,11 @@ void Decoder::DecodeInstructionsAtEntry(const uint8_t* _InstStream, uint64_t PC,
   MaxCondBranchBackwards = ~0ULL;
   DecodedBuffer = PoolObject.ReownOrClaimBuffer();
 
+  // Decode operating mode from thread's CS segment.
+  const auto CSSegment = Thread->CurrentFrame->State.gdt[Thread->CurrentFrame->State.cs_idx >> 3];
+  BlockInfo.Is64BitMode = CSSegment.L == 1;
+  LOGMAN_THROW_A_FMT(BlockInfo.Is64BitMode == CTX->Config.Is64BitMode, "Expected operating mode to not change at runtime!");
+
   // XXX: Load symbol data
   SymbolAvailable = false;
   EntryPoint = PC;

FEXCore/Source/Interface/Core/Frontend.h

@@ -2,6 +2,7 @@
 #pragma once
 
 #include "Interface/Core/X86Tables/X86Tables.h"
+#include "Interface/IR/IR.h"
 
 #include <FEXCore/HLE/SyscallHandler.h>
 #include <FEXCore/Utils/Telemetry.h>
@@ -37,13 +38,14 @@ public:
 
   struct DecodedBlockInformation final {
     uint64_t TotalInstructionCount;
+    bool Is64BitMode {};
     fextl::vector<DecodedBlocks> Blocks;
     fextl::set<uint64_t> EntryPoints;
     fextl::set<uint64_t> CodePages; // Start addresses of all pages touching the block
   };
 
   Decoder(FEXCore::Core::InternalThreadState* Thread);
-  void DecodeInstructionsAtEntry(const uint8_t* InstStream, uint64_t PC, uint64_t MaxInst);
+  void DecodeInstructionsAtEntry(FEXCore::Core::InternalThreadState *Thread, const uint8_t* InstStream, uint64_t PC, uint64_t MaxInst);
 
   const DecodedBlockInformation* GetDecodedBlockInfo() const {
     return &BlockInfo;
@@ -110,6 +112,9 @@ private:
   bool HitNonExecutableRange {};
 
   const uint8_t* InstStream {};
+  IR::OpSize GetGPROpSize() const {
+    return BlockInfo.Is64BitMode ? IR::OpSize::i64Bit : IR::OpSize::i32Bit;
+  }
 
   static constexpr size_t MAX_INST_SIZE = 15;
   uint8_t InstructionSize {};

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -72,7 +72,7 @@ void OpDispatchBuilder::SyscallOp(OpcodeArgs, bool IsSyscallInst) {
   // Calculate flags early.
   CalculateDeferredFlags();
 
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   auto NewRIP = GetRelocatedPC(Op, -Op->InstSize);
   _StoreContext(GPRSize, GPRClass, NewRIP, offsetof(FEXCore::Core::CPUState, rip));
 
@@ -112,10 +112,10 @@ void OpDispatchBuilder::SyscallOp(OpcodeArgs, bool IsSyscallInst) {
 }
 
 void OpDispatchBuilder::ThunkOp(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   uint8_t* sha256 = (uint8_t*)(Op->PC + 2);
 
-  if (CTX->Config.Is64BitMode) {
+  if (Is64BitMode) {
     // x86-64 ABI puts the function argument in RDI
     Thunk(LoadGPRRegister(X86State::REG_RDI), *reinterpret_cast<SHA256Sum*>(sha256));
   } else {
@@ -134,7 +134,7 @@ void OpDispatchBuilder::LEAOp(OpcodeArgs) {
   // LEA specifically ignores segment prefixes
   const auto SrcSize = OpSizeFromSrc(Op);
 
-  if (CTX->Config.Is64BitMode) {
+  if (Is64BitMode) {
     const auto DstSize = X86Tables::DecodeFlags::GetOpAddr(Op->Flags, 0) == X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST ? OpSize::i16Bit :
                          X86Tables::DecodeFlags::GetOpAddr(Op->Flags, 0) == X86Tables::DecodeFlags::FLAG_WIDENING_SIZE_LAST ? OpSize::i64Bit :
                                                                                                                               OpSize::i32Bit;
@@ -153,7 +153,7 @@ void OpDispatchBuilder::LEAOp(OpcodeArgs) {
 void OpDispatchBuilder::NOPOp(OpcodeArgs) {}
 
 void OpDispatchBuilder::RETOp(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   // ABI Optimization: Flags don't survive calls or rets
   if (CTX->Config.ABILocalFlags) {
@@ -194,7 +194,7 @@ void OpDispatchBuilder::IRETOp(OpcodeArgs) {
     return;
   }
 
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   Ref SP = _RMWHandle(LoadGPRRegister(X86State::REG_RSP));
 
@@ -208,7 +208,7 @@ void OpDispatchBuilder::IRETOp(OpcodeArgs) {
   // eflags (lower 16 used)
   SetPackedRFLAG(false, Pop(GPRSize, SP));
 
-  if (CTX->Config.Is64BitMode) {
+  if (Is64BitMode) {
     // RSP and SS only happen in 64-bit mode or if this is a CPL mode jump!
     // FEX doesn't support a CPL mode switch, so don't need to worry about this on 32-bit
     StoreGPRRegister(X86State::REG_RSP, Pop(GPRSize, SP));
@@ -227,7 +227,7 @@ void OpDispatchBuilder::IRETOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::CallbackReturnOp(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   // Store the new RIP
   _CallbackReturn();
   auto NewRIP = _LoadContext(GPRSize, GPRClass, offsetof(FEXCore::Core::CPUState, rip));
@@ -385,7 +385,7 @@ void OpDispatchBuilder::PUSHSegmentOp(OpcodeArgs, uint32_t SegmentReg) {
   const auto DstSize = OpSizeFromDst(Op);
 
   Ref Src {};
-  if (!CTX->Config.Is64BitMode()) {
+  if (!Is64BitMode) {
     switch (SegmentReg) {
     case FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX:
       Src = _LoadContext(SrcSize, GPRClass, offsetof(FEXCore::Core::CPUState, es_idx));
@@ -510,7 +510,7 @@ void OpDispatchBuilder::LEAVEOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::CALLOp(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   BlockSetRIP = true;
 
@@ -673,7 +673,7 @@ void OpDispatchBuilder::SETccOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::CMOVOp(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   // Calculate flags early.
   CalculateDeferredFlags();
@@ -703,7 +703,7 @@ void OpDispatchBuilder::CondJUMPOp(OpcodeArgs) {
   uint64_t InstRIP = Op->PC + Op->InstSize;
   uint64_t Target = InstRIP + TargetOffset;
 
-  if (CTX->GetGPROpSize() == OpSize::i32Bit) {
+  if (GetGPROpSize() == OpSize::i32Bit) {
     // If the GPRSize is 4 then we need to be careful about PC wrapping
     if (TargetOffset < 0 && -TargetOffset > InstRIP) {
       // Invert the signed value if we are underflowing
@@ -773,7 +773,7 @@ void OpDispatchBuilder::CondJUMPRCXOp(OpcodeArgs) {
   CalculateDeferredFlags();
 
   BlockSetRIP = true;
-  auto JcxGPRSize = CTX->GetGPROpSize();
+  auto JcxGPRSize = GetGPROpSize();
   JcxGPRSize = (Op->Flags & X86Tables::DecodeFlags::FLAG_ADDRESS_SIZE) ? (JcxGPRSize >> 1) : JcxGPRSize;
 
   uint64_t Target = Op->PC + Op->InstSize + Op->Src[0].Literal();
@@ -835,7 +835,7 @@ void OpDispatchBuilder::LoopOp(OpcodeArgs) {
   auto SrcSize = (Op->Flags & X86Tables::DecodeFlags::FLAG_ADDRESS_SIZE) ? OpSize::i32Bit : OpSize::i64Bit;
   auto OpSize = SrcSize == OpSize::i64Bit ? OpSize::i64Bit : OpSize::i32Bit;
 
-  if (!CTX->Config.Is64BitMode) {
+  if (!Is64BitMode) {
     // RCX size is 32-bit or 16-bit when executing in 32-bit mode.
     SrcSize = IR::SizeToOpSize(IR::OpSizeToSize(SrcSize) >> 1);
     OpSize = OpSize::i32Bit;
@@ -909,7 +909,7 @@ void OpDispatchBuilder::JUMPOp(OpcodeArgs) {
   uint64_t InstRIP = Op->PC + Op->InstSize;
   uint64_t TargetRIP = InstRIP + TargetOffset;
 
-  if (CTX->GetGPROpSize() == OpSize::i32Bit) {
+  if (GetGPROpSize() == OpSize::i32Bit) {
     // If the GPRSize is 4 then we need to be careful about PC wrapping
     if (TargetOffset < 0 && -TargetOffset > InstRIP) {
       // Invert the signed value if we are underflowing
@@ -1208,7 +1208,7 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs, bool ToSeg) {
       break;
     case FEXCore::X86State::REG_RBP: // GS
     case FEXCore::X86State::REG_R13: // GS
-      if (!CTX->Config.Is64BitMode) {
+      if (!Is64BitMode) {
         _StoreContext(OpSize::i16Bit, GPRClass, Src, offsetof(FEXCore::Core::CPUState, gs_idx));
         UpdatePrefixFromSegment(Src, FEXCore::X86Tables::DecodeFlags::FLAG_GS_PREFIX);
       } else {
@@ -1218,7 +1218,7 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs, bool ToSeg) {
       break;
     case FEXCore::X86State::REG_RSP: // FS
     case FEXCore::X86State::REG_R12: // FS
-      if (!CTX->Config.Is64BitMode) {
+      if (!Is64BitMode) {
         _StoreContext(OpSize::i16Bit, GPRClass, Src, offsetof(FEXCore::Core::CPUState, fs_idx));
         UpdatePrefixFromSegment(Src, FEXCore::X86Tables::DecodeFlags::FLAG_FS_PREFIX);
       } else {
@@ -1253,7 +1253,7 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs, bool ToSeg) {
       break;
     case FEXCore::X86State::REG_RBP: // GS
     case FEXCore::X86State::REG_R13: // GS
-      if (CTX->Config.Is64BitMode) {
+      if (Is64BitMode) {
         Segment = Constant(0);
       } else {
         Segment = _LoadContext(OpSize::i16Bit, GPRClass, offsetof(FEXCore::Core::CPUState, gs_idx));
@@ -1261,7 +1261,7 @@ void OpDispatchBuilder::MOVSegOp(OpcodeArgs, bool ToSeg) {
       break;
     case FEXCore::X86State::REG_RSP: // FS
     case FEXCore::X86State::REG_R12: // FS
-      if (CTX->Config.Is64BitMode) {
+      if (Is64BitMode) {
         Segment = Constant(0);
       } else {
         Segment = _LoadContext(OpSize::i16Bit, GPRClass, offsetof(FEXCore::Core::CPUState, fs_idx));
@@ -1306,7 +1306,7 @@ void OpDispatchBuilder::MOVOffsetOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::CPUIDOp(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   Ref Src = LoadSource_WithOpSize(GPRClass, Op, Op->Src[0], GPRSize, Op->Flags);
   Ref Leaf = LoadGPRRegister(X86State::REG_RCX);
@@ -1736,7 +1736,7 @@ void OpDispatchBuilder::BLSRBMIOp(OpcodeArgs) {
 void OpDispatchBuilder::BMI2Shift(OpcodeArgs) {
   // In the event the source is a memory operand, use the
   // exact width instead of the GPR size.
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   const auto Size = OpSizeFromSrc(Op);
   const auto SrcSize = Op->Src[0].IsGPR() ? GPRSize : Size;
 
@@ -1797,7 +1797,7 @@ void OpDispatchBuilder::RORX(OpcodeArgs) {
   const auto SrcSize = OpSizeFromSrc(Op);
   const auto SrcSizeBits = IR::OpSizeAsBits(SrcSize);
   const auto Amount = Op->Src[1].Literal() & (SrcSizeBits - 1);
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   const auto DoRotation = Amount != 0 && Amount < SrcSizeBits;
   const auto IsSameGPR = Op->Src[0].IsGPR() && Op->Dest.IsGPR() && Op->Src[0].Data.GPR.GPR == Op->Dest.Data.GPR.GPR;
@@ -1828,7 +1828,7 @@ void OpDispatchBuilder::MULX(OpcodeArgs) {
 
   // Src1 can be a memory operand, so ensure we constrain to the
   // absolute width of the access in that scenario.
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   const auto Src1Size = Op->Src[1].IsGPR() ? GPRSize : OpSize;
 
   Ref Src1 = LoadSource_WithOpSize(GPRClass, Op, Op->Src[1], Src1Size, Op->Flags);
@@ -2353,7 +2353,7 @@ void OpDispatchBuilder::BTOp(OpcodeArgs, uint32_t SrcIndex, BTAction Action) {
   if (Op->Dest.IsGPR()) {
     // When the destination is a GPR, we don't care about garbage in the upper bits.
     // Load the full register.
-    auto Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, CTX->GetGPROpSize(), Op->Flags);
+    auto Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, GetGPROpSize(), Op->Flags);
     Value = Dest;
 
     // Get the bit selection from the src. We need to mask for 8/16-bit, but
@@ -2436,7 +2436,7 @@ void OpDispatchBuilder::BTOp(OpcodeArgs, uint32_t SrcIndex, BTAction Action) {
 
       if (DestIsLockedMem(Op)) {
         HandledLock = true;
-        Value = _AtomicFetchCLR(OpSize::i8Bit, BitMask, LoadEffectiveAddress(this, Address, CTX->GetGPROpSize(), true));
+        Value = _AtomicFetchCLR(OpSize::i8Bit, BitMask, LoadEffectiveAddress(this, Address, GetGPROpSize(), true));
       } else {
         Value = _LoadMemAutoTSO(GPRClass, OpSize::i8Bit, Address, OpSize::i8Bit);
 
@@ -2451,7 +2451,7 @@ void OpDispatchBuilder::BTOp(OpcodeArgs, uint32_t SrcIndex, BTAction Action) {
 
       if (DestIsLockedMem(Op)) {
         HandledLock = true;
-        Value = _AtomicFetchOr(OpSize::i8Bit, BitMask, LoadEffectiveAddress(this, Address, CTX->GetGPROpSize(), true));
+        Value = _AtomicFetchOr(OpSize::i8Bit, BitMask, LoadEffectiveAddress(this, Address, GetGPROpSize(), true));
       } else {
         Value = _LoadMemAutoTSO(GPRClass, OpSize::i8Bit, Address, OpSize::i8Bit);
 
@@ -2466,7 +2466,7 @@ void OpDispatchBuilder::BTOp(OpcodeArgs, uint32_t SrcIndex, BTAction Action) {
 
       if (DestIsLockedMem(Op)) {
         HandledLock = true;
-        Value = _AtomicFetchXor(OpSize::i8Bit, BitMask, LoadEffectiveAddress(this, Address, CTX->GetGPROpSize(), true));
+        Value = _AtomicFetchXor(OpSize::i8Bit, BitMask, LoadEffectiveAddress(this, Address, GetGPROpSize(), true));
       } else {
         Value = _LoadMemAutoTSO(GPRClass, OpSize::i8Bit, Address, OpSize::i8Bit);
 
@@ -2601,7 +2601,7 @@ void OpDispatchBuilder::IMULOp(OpcodeArgs) {
     StoreGPRRegister(X86State::REG_RAX, LocalResult);
     StoreGPRRegister(X86State::REG_RDX, LocalResultHigh);
   } else if (Size == OpSize::i64Bit) {
-    if (!CTX->Config.Is64BitMode) {
+    if (!Is64BitMode) {
       LogMan::Msg::EFmt("Doesn't exist in 32bit mode");
       DecodeFailure = true;
       return;
@@ -2650,7 +2650,7 @@ void OpDispatchBuilder::MULOp(OpcodeArgs) {
     StoreGPRRegister(X86State::REG_RAX, ResultLow);
     StoreGPRRegister(X86State::REG_RDX, ResultHigh);
   } else if (Size == OpSize::i64Bit) {
-    if (!CTX->Config.Is64BitMode) {
+    if (!Is64BitMode) {
       LogMan::Msg::EFmt("Doesn't exist in 32bit mode");
       DecodeFailure = true;
       return;
@@ -2701,7 +2701,7 @@ void OpDispatchBuilder::NOTOp(OpcodeArgs) {
 
     // Always load full size, we explicitly want the upper bits to get the
     // insert behaviour for free/implicitly.
-    const auto GPRSize = CTX->GetGPROpSize();
+    const auto GPRSize = GetGPROpSize();
     Ref Src = LoadSource_WithOpSize(GPRClass, Op, Dest, GPRSize, Op->Flags);
 
     // For 8/16-bit, use 64-bit invert so we invert in place, while getting
@@ -2910,14 +2910,14 @@ void OpDispatchBuilder::WriteSegmentReg(OpcodeArgs, OpDispatchBuilder::Segment S
 }
 
 void OpDispatchBuilder::EnterOp(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   const uint64_t Value = Op->Src[0].Literal();
 
   const uint16_t AllocSpace = Value & 0xFFFF;
   const uint8_t Level = (Value >> 16) & 0x1F;
 
   const auto PushValue = [&](IR::OpSize Size, Ref Src) -> Ref {
-    const auto GPRSize = CTX->GetGPROpSize();
+    const auto GPRSize = GetGPROpSize();
 
     auto OldSP = LoadGPRRegister(X86State::REG_RSP);
     auto NewSP = _Push(GPRSize, Size, Src, OldSP);
@@ -2958,7 +2958,7 @@ void OpDispatchBuilder::SGDTOp(OpcodeArgs) {
   // Operand size prefix is ignored on this instruction, size purely depends on operating mode.
   uint64_t GDTAddress = 0xFFFFFFFFFFFE0000ULL;
   auto GDTStoreSize = OpSize::i64Bit;
-  if (!CTX->Config.Is64BitMode) {
+  if (!Is64BitMode) {
     // Mask off upper bits if 32-bit result.
     GDTAddress &= ~0U;
     GDTStoreSize = OpSize::i32Bit;
@@ -2974,7 +2974,7 @@ void OpDispatchBuilder::SIDTOp(OpcodeArgs) {
   // See SGDTOp, matches Linux in reported values
   uint64_t IDTAddress = 0xFFFFFE0000000000ULL;
   auto IDTStoreSize = OpSize::i64Bit;
-  if (!CTX->Config.Is64BitMode) {
+  if (!Is64BitMode) {
     // Mask off upper bits if 32-bit result.
     IDTAddress &= ~0U;
     IDTStoreSize = OpSize::i32Bit;
@@ -3003,7 +3003,7 @@ void OpDispatchBuilder::SMSWOp(OpcodeArgs) {
                         (1U << 1) | ///< MP - Monitor Coprocessor
                         (1U << 0)); ///< PE - Protection Enabled
 
-  if (CTX->Config.Is64BitMode) {
+  if (Is64BitMode) {
     DstSize = X86Tables::DecodeFlags::GetOpAddr(Op->Flags, 0) == X86Tables::DecodeFlags::FLAG_OPERAND_SIZE_LAST  ? OpSize::i16Bit :
               X86Tables::DecodeFlags::GetOpAddr(Op->Flags, 0) == X86Tables::DecodeFlags::FLAG_WIDENING_SIZE_LAST ? OpSize::i64Bit :
                                                                                                                    OpSize::i32Bit;
@@ -3011,7 +3011,7 @@ void OpDispatchBuilder::SMSWOp(OpcodeArgs) {
     if (!IsMemDst && DstSize == OpSize::i32Bit) {
       // Special-case version of `smsw ebx`. This instruction does an insert in to the lower 32-bits on 64-bit hosts.
       // Override and insert.
-      auto Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, CTX->GetGPROpSize(), Op->Flags);
+      auto Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, GetGPROpSize(), Op->Flags);
       Const = _Bfi(OpSize::i64Bit, 32, 0, Dest, Const);
       DstSize = OpSize::i64Bit;
     }
@@ -3531,7 +3531,7 @@ void OpDispatchBuilder::BSWAPOp(OpcodeArgs) {
     // BSWAP of 16bit is undef. ZEN+ causes the lower 16bits to get zero'd
     Dest = Constant(0);
   } else {
-    Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, CTX->GetGPROpSize(), Op->Flags);
+    Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, GetGPROpSize(), Op->Flags);
     Dest = _Rev(Size, Dest);
   }
   StoreResult(GPRClass, Op, Dest, OpSize::iInvalid);
@@ -3575,13 +3575,13 @@ void OpDispatchBuilder::NEGOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::DIVOp(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   auto Size = OpSizeFromSrc(Op);
 
   // This loads the divisor. 32-bit/64-bit paths mask inside the JIT, 8/16 do not.
   Ref Divisor = LoadSource(GPRClass, Op, Op->Dest, Op->Flags, {.AllowUpperGarbage = Size >= OpSize::i32Bit});
 
-  if (Size == OpSize::i64Bit && !CTX->Config.Is64BitMode) {
+  if (Size == OpSize::i64Bit && !Is64BitMode) {
     LogMan::Msg::EFmt("Doesn't exist in 32bit mode");
     DecodeFailure = true;
     return;
@@ -3619,10 +3619,10 @@ void OpDispatchBuilder::IDIVOp(OpcodeArgs) {
   // This loads the divisor
   Ref Divisor = LoadSource(GPRClass, Op, Op->Dest, Op->Flags);
 
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   auto Size = OpSizeFromSrc(Op);
 
-  if (Size == OpSize::i64Bit && !CTX->Config.Is64BitMode) {
+  if (Size == OpSize::i64Bit && !Is64BitMode) {
     LogMan::Msg::EFmt("Doesn't exist in 32bit mode");
     DecodeFailure = true;
     return;
@@ -3659,7 +3659,7 @@ void OpDispatchBuilder::IDIVOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::BSFOp(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   const auto DstSize = OpSizeFromDst(Op) == OpSize::i16Bit ? OpSize::i16Bit : GPRSize;
   Ref Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, DstSize, Op->Flags, {.AllowUpperGarbage = true});
   Ref Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true});
@@ -3681,7 +3681,7 @@ void OpDispatchBuilder::BSFOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::BSROp(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   const auto DstSize = OpSizeFromDst(Op) == OpSize::i16Bit ? OpSize::i16Bit : GPRSize;
   Ref Dest = LoadSource_WithOpSize(GPRClass, Op, Op->Dest, DstSize, Op->Flags, {.AllowUpperGarbage = true});
   Ref Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, {.AllowUpperGarbage = true});
@@ -3714,7 +3714,7 @@ void OpDispatchBuilder::CMPXCHGOp(OpcodeArgs) {
   //    *Xn = Xt
   // Xs = MemData
 
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   auto Size = OpSizeFromSrc(Op);
 
   if (Op->Dest.IsGPR()) {
@@ -3858,8 +3858,10 @@ void OpDispatchBuilder::CreateJumpBlocks(const fextl::vector<FEXCore::Frontend::
   }
 }
 
-void OpDispatchBuilder::BeginFunction(uint64_t RIP, const fextl::vector<FEXCore::Frontend::Decoder::DecodedBlocks>* Blocks, uint32_t NumInstructions) {
+void OpDispatchBuilder::BeginFunction(uint64_t RIP, const fextl::vector<FEXCore::Frontend::Decoder::DecodedBlocks>* Blocks, uint32_t NumInstructions, bool _Is64BitMode) {
   Entry = RIP;
+  Is64BitMode = _Is64BitMode;
+  LOGMAN_THROW_A_FMT(Is64BitMode == CTX->Config.Is64BitMode, "Expected operating mode to not change at runtime!");
   auto IRHeader = _IRHeader(InvalidNode, RIP, 0, NumInstructions, 0, 0);
   CreateJumpBlocks(Blocks);
 
@@ -3872,7 +3874,7 @@ void OpDispatchBuilder::BeginFunction(uint64_t RIP, const fextl::vector<FEXCore:
 void OpDispatchBuilder::Finalize() {
   // This usually doesn't emit any IR but in the case of hitting the block instruction limit it will
   FlushRegisterCache();
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   // Node 0 is invalid node
   Ref RealNode = reinterpret_cast<Ref>(GetNode(1));
@@ -3913,9 +3915,9 @@ uint32_t OpDispatchBuilder::GetDstBitSize(X86Tables::DecodedOp Op) const {
 }
 
 Ref OpDispatchBuilder::GetSegment(uint32_t Flags, uint32_t DefaultPrefix, bool Override) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
-  if (CTX->Config.Is64BitMode) {
+  if (Is64BitMode) {
     if (Flags & FEXCore::X86Tables::DecodeFlags::FLAG_FS_PREFIX) {
       return _LoadContext(GPRSize, GPRClass, offsetof(FEXCore::Core::CPUState, fs_cached));
     } else if (Flags & FEXCore::X86Tables::DecodeFlags::FLAG_GS_PREFIX) {
@@ -4055,8 +4057,15 @@ void OpDispatchBuilder::UpdatePrefixFromSegment(Ref Segment, uint32_t SegmentReg
   // Use BFE to extract the selector index in bits [15,3] of the segment register.
   // In some cases the upper 16-bits of the 32-bit GPR contain garbage to ignore.
   Segment = _Bfe(OpSize::i32Bit, 16 - 3, 3, Segment);
-  auto NewSegment = _LoadContextIndexed(Segment, OpSize::i32Bit, offsetof(FEXCore::Core::CPUState, gdt[0]), 4, GPRClass);
+  Ref NewSegment = _LoadContextIndexed(Segment, OpSize::i64Bit, offsetof(FEXCore::Core::CPUState, gdt[0]), 8, GPRClass);
   CheckLegacySegmentWrite(NewSegment, SegmentReg);
+
+  // Extract the 32-bit base from the GDT segment.
+  auto Upper32 = _Lshr(OpSize::i64Bit, NewSegment, _Constant(32));
+  auto Masked = _And(OpSize::i32Bit, Upper32, _Constant(0xFF00'0000));
+  Ref Merged = _Orlshr(OpSize::i32Bit, Masked, NewSegment, 16);
+  NewSegment = _Bfi(OpSize::i32Bit, 8, 16, Merged, Upper32);
+
   switch (SegmentReg) {
   case FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX:
     _StoreContext(OpSize::i32Bit, GPRClass, NewSegment, offsetof(FEXCore::Core::CPUState, es_cached));
@@ -4082,7 +4091,7 @@ void OpDispatchBuilder::UpdatePrefixFromSegment(Ref Segment, uint32_t SegmentReg
 
 AddressMode OpDispatchBuilder::DecodeAddress(const X86Tables::DecodedOp& Op, const X86Tables::DecodedOperand& Operand,
                                              MemoryAccessType AccessType, bool IsLoad) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   AddressMode A {};
   A.Segment = GetSegment(Op->Flags);
@@ -4108,7 +4117,7 @@ AddressMode OpDispatchBuilder::DecodeAddress(const X86Tables::DecodedOp& Op, con
     A.Offset = Operand.Data.GPRIndirect.Displacement;
     A.NonTSO |= IsNonTSOReg(AccessType, Operand.Data.GPRIndirect.GPR);
   } else if (Operand.IsRIPRelative()) {
-    if (CTX->Config.Is64BitMode) {
+    if (Is64BitMode) {
       A.Base = GetRelocatedPC(Op, Operand.Data.RIPLiteral.Value.s);
     } else {
       // 32bit this isn't RIP relative but instead absolute
@@ -4177,7 +4186,7 @@ Ref OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, const X86T
 
   if ((IsOperandMem(Operand, true) && LoadData) || ForceLoad) {
     if (OpSize == OpSize::f80Bit) {
-      Ref MemSrc = LoadEffectiveAddress(this, A, CTX->GetGPROpSize(), true);
+      Ref MemSrc = LoadEffectiveAddress(this, A, GetGPROpSize(), true);
       if (CTX->HostFeatures.SupportsSVE128 || CTX->HostFeatures.SupportsSVE256) {
         return _LoadMemX87SVEOptPredicate(OpSize::i128Bit, OpSize::i16Bit, MemSrc);
       } else {
@@ -4189,17 +4198,17 @@ Ref OpDispatchBuilder::LoadSource_WithOpSize(RegisterClassType Class, const X86T
 
     return _LoadMemAutoTSO(Class, OpSize, A, Align == OpSize::iInvalid ? OpSize : Align);
   } else {
-    return LoadEffectiveAddress(this, A, CTX->GetGPROpSize(), false, AllowUpperGarbage);
+    return LoadEffectiveAddress(this, A, GetGPROpSize(), false, AllowUpperGarbage);
   }
 }
 
 Ref OpDispatchBuilder::GetRelocatedPC(const FEXCore::X86Tables::DecodedOp& Op, int64_t Offset) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   return _EntrypointOffset(GPRSize, Op->PC + Op->InstSize + Offset - Entry);
 }
 
 Ref OpDispatchBuilder::LoadGPRRegister(uint32_t GPR, IR::OpSize Size, uint8_t Offset, bool AllowUpperGarbage) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   if (Size == OpSize::iInvalid) {
     Size = GPRSize;
   }
@@ -4218,7 +4227,7 @@ Ref OpDispatchBuilder::LoadGPRRegister(uint32_t GPR, IR::OpSize Size, uint8_t Of
 }
 
 void OpDispatchBuilder::StoreGPRRegister(uint32_t GPR, const Ref Src, IR::OpSize Size, uint8_t Offset) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   if (Size == OpSize::iInvalid) {
     Size = GPRSize;
   }
@@ -4248,7 +4257,7 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
   if (Operand.IsGPR()) {
     // 8Bit and 16bit destination types store their result without effecting the upper bits
     // 32bit ops ZEXT the result to 64bit
-    const auto GPRSize = CTX->GetGPROpSize();
+    const auto GPRSize = GetGPROpSize();
 
     const auto gpr = Operand.Data.GPR.GPR;
     if (gpr >= FEXCore::X86State::REG_MM_0) {
@@ -4310,7 +4319,7 @@ void OpDispatchBuilder::StoreResult_WithOpSize(FEXCore::IR::RegisterClassType Cl
   AddressMode A = DecodeAddress(Op, Operand, AccessType, false /* IsLoad */);
 
   if (OpSize == OpSize::f80Bit) {
-    Ref MemStoreDst = LoadEffectiveAddress(this, A, CTX->GetGPROpSize(), true);
+    Ref MemStoreDst = LoadEffectiveAddress(this, A, GetGPROpSize(), true);
     if (CTX->HostFeatures.SupportsSVE128 || CTX->HostFeatures.SupportsSVE256) {
       _StoreMemX87SVEOptPredicate(OpSize::i128Bit, OpSize::i16Bit, Src, MemStoreDst);
     } else {
@@ -4421,7 +4430,7 @@ void OpDispatchBuilder::ALUOp(OpcodeArgs, FEXCore::IR::IROps ALUIROp, FEXCore::I
   if (Size < OpSize::i32Bit && !DestIsLockedMem(Op) && Op->Dest.IsGPR() && !Op->Dest.Data.GPR.HighBits && IsConst &&
       (ALUIROp == IR::IROps::OP_XOR || ALUIROp == IR::IROps::OP_OR || ALUIROp == IR::IROps::OP_ANDWITHFLAGS)) {
 
-    RoundedSize = ResultSize = CTX->GetGPROpSize();
+    RoundedSize = ResultSize = GetGPROpSize();
     LOGMAN_THROW_A_FMT(Const < (1ull << IR::OpSizeAsBits(Size)), "does not clobber");
 
     // For AND, we can play the same trick but we instead need the upper bits of
@@ -4503,7 +4512,7 @@ void OpDispatchBuilder::INTOp(OpcodeArgs) {
 #ifndef _WIN32
     constexpr uint8_t SYSCALL_LITERAL = 0x80;
     if (Literal == SYSCALL_LITERAL) {
-      if (CTX->Config.Is64BitMode()) [[unlikely]] {
+      if (Is64BitMode) [[unlikely]] {
         LogMan::Msg::EFmt("[Unsupported] Trying to execute 32-bit syscall from a 64-bit process.");
         UnhandledOp(Op);
         return;
@@ -4576,7 +4585,7 @@ void OpDispatchBuilder::INTOp(OpcodeArgs) {
   // Calculate flags early.
   FlushRegisterCache();
 
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   if (SetRIPToNext) {
     BlockSetRIP = SetRIPToNext;
@@ -4635,7 +4644,7 @@ void OpDispatchBuilder::LZCNT(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::MOVBEOp(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
   const auto SrcSize = OpSizeFromSrc(Op);
 
   Ref Src = LoadSource(GPRClass, Op, Op->Src[0], Op->Flags, {.Align = OpSize::i8Bit});
@@ -4764,7 +4773,7 @@ void OpDispatchBuilder::RDPIDOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::CRC32(OpcodeArgs) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   // Destination GPR size is always 4 or 8 bytes depending on widening
   const auto DstSize = Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_REX_WIDENING ? OpSize::i64Bit : OpSize::i32Bit;
@@ -4803,7 +4812,7 @@ void OpDispatchBuilder::RDRANDOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::BreakOp(OpcodeArgs, FEXCore::IR::BreakDefinition BreakDefinition) {
-  const auto GPRSize = CTX->GetGPROpSize();
+  const auto GPRSize = GetGPROpSize();
 
   // We don't actually support this instruction
   // Multiblock may hit it though

FEXCore/Source/Interface/Core/OpcodeDispatcher.h

@@ -198,7 +198,7 @@ public:
       auto it = JumpTargets.find(NextRIP);
       if (it == JumpTargets.end()) {
 
-        const auto GPRSize = CTX->GetGPROpSize();
+        const auto GPRSize = GetGPROpSize();
         // If we don't have a jump target to a new block then we have to leave
         // Set the RIP to the next instruction and leave
         auto RelocatedNextRIP = _EntrypointOffset(GPRSize, NextRIP - Entry);
@@ -300,7 +300,7 @@ public:
     return ShouldDump;
   }
 
-  void BeginFunction(uint64_t RIP, const fextl::vector<FEXCore::Frontend::Decoder::DecodedBlocks>* Blocks, uint32_t NumInstructions);
+  void BeginFunction(uint64_t RIP, const fextl::vector<FEXCore::Frontend::Decoder::DecodedBlocks>* Blocks, uint32_t NumInstructions, bool Is64BitMode);
   void Finalize();
 
   // Dispatch builder functions
@@ -1197,7 +1197,7 @@ public:
 
     CalculateDeferredFlags();
 
-    const auto GPRSize = CTX->GetGPROpSize();
+    const auto GPRSize = GetGPROpSize();
     const auto VectorSize = GetGuestVectorLength();
 
     // Write backwards. This is a heuristic to improve coalescing, since we
@@ -1270,6 +1270,10 @@ public:
     RegCache.Partial &= ~Mask;
   }
 
+  IR::OpSize GetGPROpSize() const {
+    return Is64BitMode ? IR::OpSize::i64Bit : IR::OpSize::i32Bit;
+  }
+
 protected:
   void RecordX87Use() override {
     CurrentHeader->HasX87 = true;
@@ -1971,7 +1975,7 @@ private:
   }
 
   Ref LoadGPR(uint8_t Reg) {
-    return LoadRegCache(Reg, GPR0Index + Reg, GPRClass, CTX->GetGPROpSize());
+    return LoadRegCache(Reg, GPR0Index + Reg, GPRClass, GetGPROpSize());
   }
 
   Ref LoadContext(IR::OpSize Size, uint8_t Index) {
@@ -2371,6 +2375,7 @@ private:
   bool BlockSetRIP {false};
 
   bool Multiblock {};
+  bool Is64BitMode {};
   uint64_t Entry {};
   IROp_IRHeader* CurrentHeader {};
 
@@ -2405,7 +2410,7 @@ private:
 
   Ref _LoadMemAutoTSO(FEXCore::IR::RegisterClassType Class, IR::OpSize Size, AddressMode A, IR::OpSize Align = IR::OpSize::i8Bit) {
     bool AtomicTSO = IsTSOEnabled(Class) && !A.NonTSO;
-    A = SelectAddressMode(this, A, CTX->GetGPROpSize(), CTX->HostFeatures.SupportsTSOImm9, AtomicTSO, Class != GPRClass, Size);
+    A = SelectAddressMode(this, A, GetGPROpSize(), CTX->HostFeatures.SupportsTSOImm9, AtomicTSO, Class != GPRClass, Size);
 
     if (AtomicTSO) {
       return _LoadMemTSO(Class, Size, A.Base, A.Index, Align, A.IndexType, A.IndexScale);
@@ -2425,7 +2430,7 @@ private:
       A.Offset = 0;
     }
 
-    Out.Base = LoadEffectiveAddress(this, A, CTX->GetGPROpSize(), true, false);
+    Out.Base = LoadEffectiveAddress(this, A, GetGPROpSize(), true, false);
     return Out;
   }
 
@@ -2456,7 +2461,7 @@ private:
 
   Ref _StoreMemAutoTSO(FEXCore::IR::RegisterClassType Class, IR::OpSize Size, AddressMode A, Ref Value, IR::OpSize Align = IR::OpSize::i8Bit) {
     bool AtomicTSO = IsTSOEnabled(Class) && !A.NonTSO;
-    A = SelectAddressMode(this, A, CTX->GetGPROpSize(), CTX->HostFeatures.SupportsTSOImm9, AtomicTSO, Class != GPRClass, Size);
+    A = SelectAddressMode(this, A, GetGPROpSize(), CTX->HostFeatures.SupportsTSOImm9, AtomicTSO, Class != GPRClass, Size);
 
     if (AtomicTSO) {
       return _StoreMemTSO(Class, Size, Value, A.Base, A.Index, Align, A.IndexType, A.IndexScale);
@@ -2507,7 +2512,7 @@ private:
 
   void Push(IR::OpSize Size, Ref Value) {
     auto OldSP = LoadGPRRegister(X86State::REG_RSP);
-    auto NewSP = _Push(CTX->GetGPROpSize(), Size, Value, OldSP);
+    auto NewSP = _Push(GetGPROpSize(), Size, Value, OldSP);
     StoreGPRRegister(X86State::REG_RSP, NewSP);
     FlushRegisterCache();
   }

FEXCore/Source/Interface/Core/OpcodeDispatcher/AVX_128.cpp

@@ -778,7 +778,7 @@ void OpDispatchBuilder::AVX128_VectorXOR(OpcodeArgs) {
 void OpDispatchBuilder::AVX128_VZERO(OpcodeArgs) {
   const auto DstSize = GetDstSize(Op);
   const auto IsVZEROALL = DstSize == Core::CPUState::XMM_AVX_REG_SIZE;
-  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto NumRegs = Is64BitMode ? 16U : 8U;
 
   if (IsVZEROALL) {
     // NOTE: Despite the name being VZEROALL, this will still only ever
@@ -968,7 +968,7 @@ void OpDispatchBuilder::AVX128_VBROADCAST(OpcodeArgs) {
     }
   } else {
     // Get the address to broadcast from into a GPR.
-    Ref Address = MakeSegmentAddress(Op, Op->Src[0], CTX->GetGPROpSize());
+    Ref Address = MakeSegmentAddress(Op, Op->Src[0], GetGPROpSize());
     Src.Low = _VBroadcastFromMem(OpSize::i128Bit, ElementSize, Address);
   }
 
@@ -1022,7 +1022,7 @@ void OpDispatchBuilder::AVX128_InsertCVTGPR_To_FPR(OpcodeArgs) {
 
   if (Op->Src[1].IsGPR()) {
     // If the source is a GPR then convert directly from the GPR.
-    auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Op->Src[1], CTX->GetGPROpSize(), Op->Flags);
+    auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Op->Src[1], GetGPROpSize(), Op->Flags);
     Result.Low = _VSToFGPRInsert(OpSize::i128Bit, DstElementSize, SrcSize, Src1.Low, Src2, false);
   } else if (SrcSize != DstElementSize) {
     // If the source is from memory but the Source size and destination size aren't the same,
@@ -1179,7 +1179,7 @@ void OpDispatchBuilder::AVX128_MOVBetweenGPR_FPR(OpcodeArgs) {
     RefPair Result {};
     if (Op->Src[0].IsGPR()) {
       // Loading from GPR and moving to Vector.
-      Ref Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], CTX->GetGPROpSize(), Op->Flags);
+      Ref Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], GetGPROpSize(), Op->Flags);
       // zext to 128bit
       Result.Low = _VCastFromGPR(OpSize::i128Bit, OpSizeFromSrc(Op), Src);
     } else {
@@ -1227,7 +1227,7 @@ void OpDispatchBuilder::AVX128_PExtr(OpcodeArgs) {
   Index &= NumElements - 1;
 
   if (Op->Dest.IsGPR()) {
-    const auto GPRSize = CTX->GetGPROpSize();
+    const auto GPRSize = GetGPROpSize();
     // Extract already zero extends the result.
     Ref Result = _VExtractToGPR(OpSize::i128Bit, OverridenElementSize, Src.Low, Index);
     StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Result, GPRSize, OpSize::iInvalid);
@@ -1341,7 +1341,7 @@ void OpDispatchBuilder::AVX128_MOVMSK(OpcodeArgs) {
     auto GPRHigh = Mask8Byte(Src.High);
     GPR = _Orlshl(OpSize::i64Bit, GPRLow, GPRHigh, 2);
   }
-  StoreResult_WithOpSize(GPRClass, Op, Op->Dest, GPR, CTX->GetGPROpSize(), OpSize::iInvalid);
+  StoreResult_WithOpSize(GPRClass, Op, Op->Dest, GPR, GetGPROpSize(), OpSize::iInvalid);
 }
 
 void OpDispatchBuilder::AVX128_MOVMSKB(OpcodeArgs) {
@@ -1383,7 +1383,7 @@ void OpDispatchBuilder::AVX128_PINSRImpl(OpcodeArgs, IR::OpSize ElementSize, con
 
   if (Src2Op.IsGPR()) {
     // If the source is a GPR then convert directly from the GPR.
-    auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, CTX->GetGPROpSize(), Op->Flags);
+    auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, GetGPROpSize(), Op->Flags);
     Result.Low = _VInsGPR(OpSize::i128Bit, ElementSize, Index, Src1.Low, Src2);
   } else {
     // If loading from memory then we only load the element size
@@ -2055,7 +2055,7 @@ void OpDispatchBuilder::AVX128_VMASKMOVImpl(OpcodeArgs, IR::OpSize ElementSize,
   auto Mask = AVX128_LoadSource_WithOpSize(Op, MaskOp, Op->Flags, !Is128Bit);
 
   const auto MakeAddress = [this, Op](const X86Tables::DecodedOperand& Data) {
-    return MakeSegmentAddress(Op, Data, CTX->GetGPROpSize());
+    return MakeSegmentAddress(Op, Data, GetGPROpSize());
   };
 
   if (IsStore) {
@@ -2148,7 +2148,7 @@ void OpDispatchBuilder::AVX128_VectorVariableBlend(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::AVX128_SaveAVXState(Ref MemBase) {
-  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto NumRegs = Is64BitMode ? 16U : 8U;
 
   for (uint32_t i = 0; i < NumRegs; i += 2) {
     RefPair Pair = LoadContextPair(OpSize::i128Bit, AVXHigh0Index + i);
@@ -2157,7 +2157,7 @@ void OpDispatchBuilder::AVX128_SaveAVXState(Ref MemBase) {
 }
 
 void OpDispatchBuilder::AVX128_RestoreAVXState(Ref MemBase) {
-  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto NumRegs = Is64BitMode ? 16U : 8U;
 
   for (uint32_t i = 0; i < NumRegs; i += 2) {
     auto YMMHRegs = LoadMemPair(FPRClass, OpSize::i128Bit, MemBase, i * 16 + 576);
@@ -2168,7 +2168,7 @@ void OpDispatchBuilder::AVX128_RestoreAVXState(Ref MemBase) {
 }
 
 void OpDispatchBuilder::AVX128_DefaultAVXState() {
-  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto NumRegs = Is64BitMode ? 16U : 8U;
 
   auto ZeroRegister = LoadZeroVector(OpSize::i128Bit);
   for (uint32_t i = 0; i < NumRegs; i++) {

FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp

@@ -434,7 +434,7 @@ Ref OpDispatchBuilder::InsertCVTGPR_To_FPRImpl(OpcodeArgs, IR::OpSize DstSize, I
 
   if (Src2Op.IsGPR()) {
     // If the source is a GPR then convert directly from the GPR.
-    auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, CTX->GetGPROpSize(), Op->Flags);
+    auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, GetGPROpSize(), Op->Flags);
     return _VSToFGPRInsert(DstSize, DstElementSize, SrcSize, Src1, Src2, ZeroUpperBits);
   } else if (SrcSize != DstElementSize) {
     // If the source is from memory but the Source size and destination size aren't the same,
@@ -741,7 +741,7 @@ void OpDispatchBuilder::MOVMSKOp(OpcodeArgs, IR::OpSize ElementSize) {
     GPR = _Bfi(OpSize::i64Bit, 32, 31, GPR, GPR);
     // Shift right to only get the two sign bits we care about.
     GPR = _Lshr(OpSize::i64Bit, GPR, Constant(62));
-    StoreResult_WithOpSize(GPRClass, Op, Op->Dest, GPR, CTX->GetGPROpSize(), OpSize::iInvalid);
+    StoreResult_WithOpSize(GPRClass, Op, Op->Dest, GPR, GetGPROpSize(), OpSize::iInvalid);
   } else if (Size == OpSize::i128Bit && ElementSize == OpSize::i32Bit) {
     // Shift all the sign bits to the bottom of their respective elements.
     Src = _VUShrI(Size, OpSize::i32Bit, Src, 31);
@@ -753,7 +753,7 @@ void OpDispatchBuilder::MOVMSKOp(OpcodeArgs, IR::OpSize ElementSize) {
     Src = _VAddV(Size, OpSize::i32Bit, Src);
     // Extract to a GPR.
     Ref GPR = _VExtractToGPR(Size, OpSize::i32Bit, Src, 0);
-    StoreResult_WithOpSize(GPRClass, Op, Op->Dest, GPR, CTX->GetGPROpSize(), OpSize::iInvalid);
+    StoreResult_WithOpSize(GPRClass, Op, Op->Dest, GPR, GetGPROpSize(), OpSize::iInvalid);
   } else {
     Ref CurrentVal = Constant(0);
 
@@ -1504,7 +1504,7 @@ void OpDispatchBuilder::VBROADCASTOp(OpcodeArgs, IR::OpSize ElementSize) {
     Result = _VDupElement(DstSize, ElementSize, Src, 0);
   } else {
     // Get the address to broadcast from into a GPR.
-    Ref Address = MakeSegmentAddress(Op, Op->Src[0], CTX->GetGPROpSize());
+    Ref Address = MakeSegmentAddress(Op, Op->Src[0], GetGPROpSize());
     Result = _VBroadcastFromMem(DstSize, ElementSize, Address);
   }
 
@@ -1523,7 +1523,7 @@ Ref OpDispatchBuilder::PINSROpImpl(OpcodeArgs, IR::OpSize ElementSize, const X86
 
   if (Src2Op.IsGPR()) {
     // If the source is a GPR then convert directly from the GPR.
-    auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, CTX->GetGPROpSize(), Op->Flags);
+    auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, GetGPROpSize(), Op->Flags);
     return _VInsGPR(Size, ElementSize, Index, Src1, Src2);
   }
 
@@ -1644,7 +1644,7 @@ void OpDispatchBuilder::PExtrOp(OpcodeArgs, IR::OpSize ElementSize) {
   Index &= NumElements - 1;
 
   if (Op->Dest.IsGPR()) {
-    const auto GPRSize = CTX->GetGPROpSize();
+    const auto GPRSize = GetGPROpSize();
     // Extract already zero extends the result.
     Ref Result = _VExtractToGPR(OpSize::i128Bit, OverridenElementSize, Src, Index);
     StoreResult_WithOpSize(GPRClass, Op, Op->Dest, Result, GPRSize, OpSize::iInvalid);
@@ -2065,7 +2065,7 @@ Ref OpDispatchBuilder::CVTGPR_To_FPRImpl(OpcodeArgs, IR::OpSize DstElementSize,
   Ref Converted {};
   if (Src2Op.IsGPR()) {
     // If the source is a GPR then convert directly from the GPR.
-    auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, CTX->GetGPROpSize(), Op->Flags);
+    auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, GetGPROpSize(), Op->Flags);
     Converted = _Float_FromGPR_S(DstElementSize, SrcSize, Src2);
   } else if (SrcSize != DstElementSize) {
     // If the source is from memory but the Source size and destination size aren't the same,
@@ -2355,7 +2355,7 @@ void OpDispatchBuilder::VMASKMOVOpImpl(OpcodeArgs, IR::OpSize ElementSize, IR::O
                                        const X86Tables::DecodedOperand& MaskOp, const X86Tables::DecodedOperand& DataOp) {
 
   const auto MakeAddress = [this, Op](const X86Tables::DecodedOperand& Data) {
-    return MakeSegmentAddress(Op, Data, CTX->GetGPROpSize());
+    return MakeSegmentAddress(Op, Data, GetGPROpSize());
   };
 
   Ref Mask = LoadSource_WithOpSize(FPRClass, Op, MaskOp, DataSize, Op->Flags);
@@ -2398,7 +2398,7 @@ void OpDispatchBuilder::MOVBetweenGPR_FPR(OpcodeArgs, VectorOpType VectorType) {
     Ref Result {};
     if (Op->Src[0].IsGPR()) {
       // Loading from GPR and moving to Vector.
-      Ref Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], CTX->GetGPROpSize(), Op->Flags);
+      Ref Src = LoadSource_WithOpSize(FPRClass, Op, Op->Src[0], GetGPROpSize(), Op->Flags);
       // zext to 128bit
       Result = _VCastFromGPR(OpSize::i128Bit, OpSizeFromSrc(Op), Src);
     } else {
@@ -2504,7 +2504,7 @@ Ref OpDispatchBuilder::XSaveBase(X86Tables::DecodedOp Op) {
 void OpDispatchBuilder::XSaveOpImpl(OpcodeArgs) {
   // NOTE: Mask should be EAX and EDX concatenated, but we only need to test
   //       for features that are in the lower 32 bits, so EAX only is sufficient.
-  const auto OpSize = CTX->GetGPROpSize();
+  const auto OpSize = GetGPROpSize();
 
   const auto StoreIfFlagSet = [this, OpSize](uint32_t BitIndex, auto fn, uint32_t FieldSize = 1) {
     Ref Mask = LoadGPRRegister(X86State::REG_RAX);
@@ -2634,7 +2634,7 @@ void OpDispatchBuilder::SaveX87State(OpcodeArgs, Ref MemBase) {
 }
 
 void OpDispatchBuilder::SaveSSEState(Ref MemBase) {
-  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto NumRegs = Is64BitMode ? 16U : 8U;
 
   for (uint32_t i = 0; i < NumRegs; i += 2) {
     _StoreMemPair(FPRClass, OpSize::i128Bit, LoadXMMRegister(i), LoadXMMRegister(i + 1), MemBase, i * 16 + 160);
@@ -2647,7 +2647,7 @@ void OpDispatchBuilder::SaveMXCSRState(Ref MemBase) {
 }
 
 void OpDispatchBuilder::SaveAVXState(Ref MemBase) {
-  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto NumRegs = Is64BitMode ? 16U : 8U;
 
   for (uint32_t i = 0; i < NumRegs; i += 2) {
     Ref Upper0 = _VDupElement(OpSize::i256Bit, OpSize::i128Bit, LoadXMMRegister(i + 0), 1);
@@ -2676,7 +2676,7 @@ void OpDispatchBuilder::FXRStoreOp(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::XRstorOpImpl(OpcodeArgs) {
-  const auto OpSize = CTX->GetGPROpSize();
+  const auto OpSize = GetGPROpSize();
 
   // If a bit in our XSTATE_BV is set, then we restore from that region of the XSAVE area,
   // otherwise, if not set, then we need to set the relevant data the bit corresponds to
@@ -2762,7 +2762,7 @@ void OpDispatchBuilder::RestoreX87State(Ref MemBase) {
 }
 
 void OpDispatchBuilder::RestoreSSEState(Ref MemBase) {
-  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto NumRegs = Is64BitMode ? 16U : 8U;
 
   for (uint32_t i = 0; i < NumRegs; i += 2) {
     auto XMMRegs = LoadMemPair(FPRClass, OpSize::i128Bit, MemBase, i * 16 + 160);
@@ -2783,7 +2783,7 @@ void OpDispatchBuilder::RestoreMXCSRState(Ref MXCSR) {
 }
 
 void OpDispatchBuilder::RestoreAVXState(Ref MemBase) {
-  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto NumRegs = Is64BitMode ? 16U : 8U;
 
   for (uint32_t i = 0; i < NumRegs; i += 2) {
     Ref XMMReg0 = LoadXMMRegister(i + 0);
@@ -2808,7 +2808,7 @@ void OpDispatchBuilder::DefaultX87State(OpcodeArgs) {
 }
 
 void OpDispatchBuilder::DefaultSSEState() {
-  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto NumRegs = Is64BitMode ? 16U : 8U;
 
   Ref ZeroVector = LoadZeroVector(OpSize::i128Bit);
   for (uint32_t i = 0; i < NumRegs; ++i) {
@@ -2817,7 +2817,7 @@ void OpDispatchBuilder::DefaultSSEState() {
 }
 
 void OpDispatchBuilder::DefaultAVXState() {
-  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto NumRegs = Is64BitMode ? 16U : 8U;
 
   for (uint32_t i = 0; i < NumRegs; i++) {
     Ref Reg = LoadXMMRegister(i);
@@ -4729,7 +4729,7 @@ void OpDispatchBuilder::VPBLENDWOp(OpcodeArgs) {
 void OpDispatchBuilder::VZEROOp(OpcodeArgs) {
   const auto DstSize = OpSizeFromDst(Op);
   const auto IsVZEROALL = DstSize == OpSize::i256Bit;
-  const auto NumRegs = CTX->Config.Is64BitMode ? 16U : 8U;
+  const auto NumRegs = Is64BitMode ? 16U : 8U;
 
   if (IsVZEROALL) {
     // NOTE: Despite the name being VZEROALL, this will still only ever

FEXCore/Source/Interface/Core/OpcodeDispatcher/X87.cpp

@@ -125,7 +125,7 @@ void OpDispatchBuilder::FST(OpcodeArgs, IR::OpSize Width) {
   const auto SourceSize = ReducedPrecisionMode ? OpSize::i64Bit : OpSize::i128Bit;
   AddressMode A = DecodeAddress(Op, Op->Dest, MemoryAccessType::DEFAULT, false);
 
-  A = SelectAddressMode(this, A, CTX->GetGPROpSize(), CTX->HostFeatures.SupportsTSOImm9, false, false, Width);
+  A = SelectAddressMode(this, A, GetGPROpSize(), CTX->HostFeatures.SupportsTSOImm9, false, false, Width);
   _StoreStackMem(SourceSize, Width, A.Base, A.Index, OpSize::iInvalid, A.IndexType, A.IndexScale, /*Float=*/true);
 
   if (Op->TableInfo->Flags & X86Tables::InstFlags::FLAGS_POP) {

FEXCore/Source/Interface/IR/PassManager.cpp

@@ -70,7 +70,7 @@ void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl* ctx) {
   FEX_CONFIG_OPT(DisablePasses, O0);
 
   if (!DisablePasses()) {
-    InsertPass(CreateX87StackOptimizationPass(ctx->HostFeatures, ctx->GetGPROpSize()));
+    InsertPass(CreateX87StackOptimizationPass(ctx->HostFeatures, ctx->Config.Is64BitMode ? IR::OpSize::i64Bit : IR::OpSize::i32Bit));
     InsertPass(CreateConstProp(ctx->HostFeatures.SupportsTSOImm9));
     InsertPass(CreateDeadFlagCalculationEliminination());
   }

FEXCore/include/FEXCore/Core/CoreState.h

@@ -121,9 +121,48 @@ struct CPUState {
   uint64_t mm[8][2] {};
 
   // 32bit x86 state
-  struct {
-    uint32_t base;
+  struct gdt_segment {
+    uint16_t Limit0;
+    uint16_t Base0;
+    uint16_t Base1  : 8;
+    uint16_t Type   : 4;
+    uint16_t S      : 1;
+    uint16_t DPL    : 2;
+    uint16_t P      : 1;
+    uint16_t Limit1 : 4;
+    uint16_t AVL    : 1;
+    uint16_t L      : 1;
+    uint16_t D      : 1;
+    uint16_t G      : 1;
+    uint16_t Base2  : 8;
   } gdt[32] {};
+
+  static uint32_t CalculateGDTBase(gdt_segment GDT) {
+    uint32_t Base{};
+    Base |= GDT.Base2 << 24;
+    Base |= GDT.Base1 << 16;
+    Base |= GDT.Base0;
+    return Base;
+  }
+
+  static uint32_t CalculateGDTLimit(gdt_segment GDT) {
+    uint32_t Limit{};
+    Limit |= GDT.Limit1 << 16;
+    Limit |= GDT.Limit0;
+    return Limit;
+  }
+
+  static void SetGDTBase(gdt_segment *GDT, uint32_t Base) {
+    GDT->Base0 = Base;
+    GDT->Base1 = Base >> 16;
+    GDT->Base2 = Base >> 24;
+  }
+
+  static void SetGDTLimit(gdt_segment *GDT, uint32_t Limit) {
+    GDT->Limit0 = Limit;
+    GDT->Limit1 = Limit >> 16;
+  }
+
   uint16_t FCW {0x37F};
   uint8_t AbridgedFTW {};
 
@@ -135,6 +174,7 @@ struct CPUState {
 
   static constexpr size_t FLAG_SIZE = sizeof(flags[0]);
   static constexpr size_t GDT_SIZE = sizeof(gdt[0]);
+  static_assert(GDT_SIZE == sizeof(uint64_t), "Segments required to be 8-byte in size.");
   static constexpr size_t GPR_REG_SIZE = sizeof(gregs[0]);
   static constexpr size_t XMM_AVX_REG_SIZE = sizeof(xmm.avx.data[0]);
   static constexpr size_t XMM_SSE_REG_SIZE = XMM_AVX_REG_SIZE / 2;

Source/Tools/LinuxEmulation/LinuxSyscalls/SignalDelegator/GuestFramesManagement.cpp

@@ -199,12 +199,12 @@ void SignalDelegator::RestoreFrame_ia32(FEXCore::Core::InternalThreadState* Thre
     Frame->State.gs_idx = guest_uctx->sc.gs;
     Frame->State.ss_idx = guest_uctx->sc.ss;
 
-    Frame->State.cs_cached = Frame->State.gdt[Frame->State.cs_idx >> 3].base;
-    Frame->State.ds_cached = Frame->State.gdt[Frame->State.ds_idx >> 3].base;
-    Frame->State.es_cached = Frame->State.gdt[Frame->State.es_idx >> 3].base;
-    Frame->State.fs_cached = Frame->State.gdt[Frame->State.fs_idx >> 3].base;
-    Frame->State.gs_cached = Frame->State.gdt[Frame->State.gs_idx >> 3].base;
-    Frame->State.ss_cached = Frame->State.gdt[Frame->State.ss_idx >> 3].base;
+    Frame->State.cs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.cs_idx >> 3]);
+    Frame->State.ds_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.ds_idx >> 3]);
+    Frame->State.es_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.es_idx >> 3]);
+    Frame->State.fs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.fs_idx >> 3]);
+    Frame->State.gs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.gs_idx >> 3]);
+    Frame->State.ss_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.ss_idx >> 3]);
 
 #define COPY_REG(x, y) Frame->State.gregs[FEXCore::X86State::REG_##x] = guest_uctx->sc.y;
     COPY_REG(RDI, di);
@@ -272,12 +272,12 @@ void SignalDelegator::RestoreRTFrame_ia32(FEXCore::Core::InternalThreadState* Th
     Frame->State.gs_idx = guest_uctx->uc.uc_mcontext.gregs[FEXCore::x86::FEX_REG_GS];
     Frame->State.ss_idx = guest_uctx->uc.uc_mcontext.gregs[FEXCore::x86::FEX_REG_SS];
 
-    Frame->State.cs_cached = Frame->State.gdt[Frame->State.cs_idx >> 3].base;
-    Frame->State.ds_cached = Frame->State.gdt[Frame->State.ds_idx >> 3].base;
-    Frame->State.es_cached = Frame->State.gdt[Frame->State.es_idx >> 3].base;
-    Frame->State.fs_cached = Frame->State.gdt[Frame->State.fs_idx >> 3].base;
-    Frame->State.gs_cached = Frame->State.gdt[Frame->State.gs_idx >> 3].base;
-    Frame->State.ss_cached = Frame->State.gdt[Frame->State.ss_idx >> 3].base;
+    Frame->State.cs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.cs_idx >> 3]);
+    Frame->State.ds_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.ds_idx >> 3]);
+    Frame->State.es_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.es_idx >> 3]);
+    Frame->State.fs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.fs_idx >> 3]);
+    Frame->State.gs_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.gs_idx >> 3]);
+    Frame->State.ss_cached = Frame->State.CalculateGDTBase(Frame->State.gdt[Frame->State.ss_idx >> 3]);
 
 #define COPY_REG(x) Frame->State.gregs[FEXCore::X86State::REG_##x] = guest_uctx->uc.uc_mcontext.gregs[FEXCore::x86::FEX_REG_##x];
     COPY_REG(RDI);

Source/Tools/LinuxEmulation/LinuxSyscalls/x32/Thread.cpp

@@ -54,8 +54,8 @@ uint64_t SetThreadArea(FEXCore::Core::CpuStateFrame* Frame, void* tls) {
   if (u_info->entry_number == -1) {
     for (uint32_t i = TLS_NextEntry; i < TLS_MaxEntry; ++i) {
       auto GDT = &Frame->State.gdt[i];
-      if (GDT->base == 0) {
-        // If the base is zero then it isn't present with our setup
+      if (Frame->State.CalculateGDTLimit(*GDT) == 0) {
+        // If the limit is zero then it isn't present with our setup
         u_info->entry_number = i;
         break;
       }
@@ -69,29 +69,30 @@ uint64_t SetThreadArea(FEXCore::Core::CpuStateFrame* Frame, void* tls) {
 
   // Now we need to update the thread's GDT to handle this change
   auto GDT = &Frame->State.gdt[u_info->entry_number];
-  GDT->base = u_info->base_addr;
+  Frame->State.SetGDTBase(GDT, u_info->base_addr);
+  Frame->State.SetGDTLimit(GDT, 0xF'FFFFU);
 
   // With the segment register optimization we need to check all of the segment registers and update.
   const auto GetEntry = [](auto value) {
     return value >> 3;
   };
   if (GetEntry(Frame->State.cs_idx) == u_info->entry_number) {
-    Frame->State.cs_cached = GDT->base;
+    Frame->State.cs_cached = Frame->State.CalculateGDTBase(*GDT);
   }
   if (GetEntry(Frame->State.ds_idx) == u_info->entry_number) {
-    Frame->State.ds_cached = GDT->base;
+    Frame->State.ds_cached = Frame->State.CalculateGDTBase(*GDT);
   }
   if (GetEntry(Frame->State.es_idx) == u_info->entry_number) {
-    Frame->State.es_cached = GDT->base;
+    Frame->State.es_cached = Frame->State.CalculateGDTBase(*GDT);
   }
   if (GetEntry(Frame->State.fs_idx) == u_info->entry_number) {
-    Frame->State.fs_cached = GDT->base;
+    Frame->State.fs_cached = Frame->State.CalculateGDTBase(*GDT);
   }
   if (GetEntry(Frame->State.gs_idx) == u_info->entry_number) {
-    Frame->State.gs_cached = GDT->base;
+    Frame->State.gs_cached = Frame->State.CalculateGDTBase(*GDT);
   }
   if (GetEntry(Frame->State.ss_idx) == u_info->entry_number) {
-    Frame->State.ss_cached = GDT->base;
+    Frame->State.ss_cached = Frame->State.CalculateGDTBase(*GDT);
   }
   return 0;
 }
@@ -164,7 +165,7 @@ void RegisterThread(FEX::HLE::SyscallHandler* Handler) {
     memset(u_info, 0, sizeof(*u_info));
 
     // FEX only stores base instead of the full GDT
-    u_info->base_addr = GDT->base;
+    u_info->base_addr = Frame->State.CalculateGDTBase(*GDT);
 
     // Fill the rest of the structure with expected data (even if wrong at the moment)
     if (u_info->base_addr) {

Source/Windows/ARM64EC/Module.cpp

@@ -379,7 +379,8 @@ static void LoadStateFromECContext(FEXCore::Core::InternalThreadState* Thread, C
 
     // The TEB is the only populated GDT entry by default
     const auto TEB = reinterpret_cast<uint64_t>(NtCurrentTeb());
-    State.gdt[(Context.SegGs & 0xffff) >> 3].base = TEB;
+    State.SetGDTBase(&State.gdt[(Context.SegGs & 0xffff) >> 3], TEB);
+    State.SetGDTLimit(&State.gdt[(Context.SegGs & 0xffff) >> 3], 0xF'FFFFU);
     State.gs_cached = TEB;
     State.fs_cached = 0;
     State.es_cached = 0;

Source/Windows/WOW64/Module.cpp

@@ -189,7 +189,8 @@ void LoadStateFromWowContext(FEXCore::Core::InternalThreadState* Thread, uint64_
   State.gs_idx = Context->SegGs & 0xffff;
 
   // The TEB is the only populated GDT entry by default
-  State.gdt[(Context->SegFs & 0xffff) >> 3].base = WowTEB;
+  State.SetGDTBase(&State.gdt[(Context->SegFs & 0xffff) >> 3], WowTEB);
+  State.SetGDTLimit(&State.gdt[(Context->SegFs & 0xffff) >> 3], 0xF'FFFFU);
   State.fs_cached = WowTEB;
   State.es_cached = 0;
   State.cs_cached = 0;

unittests/InstructionCountCI/AVX128/FMA4.json

@@ -18,8 +18,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -32,8 +32,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -46,8 +46,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -60,8 +60,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -74,8 +74,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -88,8 +88,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -102,8 +102,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -116,8 +116,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -130,8 +130,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -144,8 +144,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -158,8 +158,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -172,8 +172,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -186,8 +186,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -200,8 +200,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -214,8 +214,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -228,8 +228,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -242,8 +242,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -256,8 +256,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -270,8 +270,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -284,8 +284,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -298,8 +298,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -312,8 +312,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -326,8 +326,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -340,8 +340,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -354,8 +354,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -368,8 +368,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -382,8 +382,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -396,8 +396,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -410,8 +410,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     },
@@ -424,8 +424,8 @@
         "mov w20, #0x10000",
         "str x20, [x28, #24]",
         "mov w1, #0x401",
-        "str x1, [x28, #1328]",
-        "ldr x0, [x28, #2712]",
+        "str x1, [x28, #1456]",
+        "ldr x0, [x28, #2840]",
         "br x0"
       ]
     }

unittests/InstructionCountCI/AVX128/VEX_map1.json

@@ -485,7 +485,7 @@
       ],
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #2928]",
+        "ldr q3, [x28, #3056]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -499,7 +499,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #32]",
         "ushr v3.4s, v16.4s, #31",
-        "ldr q4, [x28, #2928]",
+        "ldr q4, [x28, #3056]",
         "ushl v3.4s, v3.4s, v4.4s",
         "addv s3, v3.4s",
         "mov w20, v3.s[0]",
@@ -1122,7 +1122,7 @@
         "Map 1 0b01 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -1134,7 +1134,7 @@
         "Map 1 0b01 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q2, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -1146,7 +1146,7 @@
         "Map 1 0b01 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q2, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -1171,7 +1171,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q3, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1185,7 +1185,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q3, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1199,7 +1199,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q3, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1223,7 +1223,7 @@
         "Map 1 0b10 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2464]",
+        "ldr x0, [x28, #2592]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -1235,7 +1235,7 @@
         "Map 1 0b10 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2464]",
+        "ldr x0, [x28, #2592]",
         "ldr q2, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -1247,7 +1247,7 @@
         "Map 1 0b10 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2464]",
+        "ldr x0, [x28, #2592]",
         "ldr q2, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -1274,7 +1274,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
-        "ldr x0, [x28, #2464]",
+        "ldr x0, [x28, #2592]",
         "ldr q3, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1288,7 +1288,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
-        "ldr x0, [x28, #2464]",
+        "ldr x0, [x28, #2592]",
         "ldr q3, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1302,7 +1302,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
-        "ldr x0, [x28, #2464]",
+        "ldr x0, [x28, #2592]",
         "ldr q3, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1326,7 +1326,7 @@
         "Map 1 0b11 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2456]",
+        "ldr x0, [x28, #2584]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -1338,7 +1338,7 @@
         "Map 1 0b11 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2456]",
+        "ldr x0, [x28, #2584]",
         "ldr q2, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -1350,7 +1350,7 @@
         "Map 1 0b11 0x70 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2456]",
+        "ldr x0, [x28, #2584]",
         "ldr q2, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -1377,7 +1377,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
-        "ldr x0, [x28, #2456]",
+        "ldr x0, [x28, #2584]",
         "ldr q3, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1391,7 +1391,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
-        "ldr x0, [x28, #2456]",
+        "ldr x0, [x28, #2584]",
         "ldr q3, [x0, #32]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -1405,7 +1405,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
-        "ldr x0, [x28, #2456]",
+        "ldr x0, [x28, #2584]",
         "ldr q3, [x0, #48]",
         "tbl v16.16b, {v17.16b}, v3.16b",
         "tbl v2.16b, {v2.16b}, v3.16b",
@@ -2288,7 +2288,7 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -2302,7 +2302,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
         "ldr q3, [x28, #64]",
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q4, [x0, #16]",
         "tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
         "tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2315,7 +2315,7 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q2, [x0, #32]",
         "tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -2329,7 +2329,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
         "ldr q3, [x28, #64]",
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q4, [x0, #32]",
         "tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
         "tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -2342,7 +2342,7 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q2, [x0, #48]",
         "tbl v16.16b, {v17.16b, v18.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
@@ -2356,7 +2356,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
         "ldr q3, [x28, #64]",
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q4, [x0, #48]",
         "tbl v16.16b, {v17.16b, v18.16b}, v4.16b",
         "tbl v2.16b, {v2.16b, v3.16b}, v4.16b",
@@ -3763,7 +3763,7 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.2d, v17.2d, v2.2d",
         "stp xzr, xzr, [x28, #32]"
@@ -3777,7 +3777,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
         "ldr q3, [x28, #64]",
-        "ldr q4, [x28, #2832]",
+        "ldr q4, [x28, #2960]",
         "eor v5.16b, v18.16b, v4.16b",
         "fadd v16.2d, v17.2d, v5.2d",
         "eor v3.16b, v3.16b, v4.16b",
@@ -3791,7 +3791,7 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.4s, v17.4s, v2.4s",
         "stp xzr, xzr, [x28, #32]"
@@ -3805,7 +3805,7 @@
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #48]",
         "ldr q3, [x28, #64]",
-        "ldr q4, [x28, #2800]",
+        "ldr q4, [x28, #2928]",
         "eor v5.16b, v18.16b, v4.16b",
         "fadd v16.4s, v17.4s, v5.4s",
         "eor v3.16b, v3.16b, v4.16b",
@@ -3976,7 +3976,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3056]",
+        "ldr q2, [x28, #3184]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
@@ -3992,7 +3992,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x28, #32]",
-        "ldr q3, [x28, #3056]",
+        "ldr q3, [x28, #3184]",
         "cmlt v4.16b, v16.16b, #0",
         "and v4.16b, v4.16b, v3.16b",
         "addp v4.16b, v4.16b, v4.16b",

unittests/InstructionCountCI/AVX128/VEX_map2.json

@@ -1917,7 +1917,7 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2768]",
+        "ldr q2, [x28, #2896]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
@@ -4485,7 +4485,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4502,7 +4502,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2800]",
+        "ldr q5, [x28, #2928]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4518,7 +4518,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4535,7 +4535,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2832]",
+        "ldr q5, [x28, #2960]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4551,7 +4551,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2864]",
+        "ldr q2, [x28, #2992]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4568,7 +4568,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2864]",
+        "ldr q5, [x28, #2992]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -4584,7 +4584,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2896]",
+        "ldr q2, [x28, #3024]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -4601,7 +4601,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2896]",
+        "ldr q5, [x28, #3024]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -5541,7 +5541,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5558,7 +5558,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2800]",
+        "ldr q5, [x28, #2928]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5574,7 +5574,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5591,7 +5591,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2832]",
+        "ldr q5, [x28, #2960]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5607,7 +5607,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2864]",
+        "ldr q2, [x28, #2992]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5624,7 +5624,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2864]",
+        "ldr q5, [x28, #2992]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -5640,7 +5640,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2896]",
+        "ldr q2, [x28, #3024]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5657,7 +5657,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2896]",
+        "ldr q5, [x28, #3024]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -5673,7 +5673,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5689,7 +5689,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2800]",
+        "ldr q5, [x28, #2928]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5704,7 +5704,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5720,7 +5720,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2832]",
+        "ldr q5, [x28, #2960]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5735,7 +5735,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2864]",
+        "ldr q2, [x28, #2992]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5751,7 +5751,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2864]",
+        "ldr q5, [x28, #2992]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -5766,7 +5766,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2896]",
+        "ldr q2, [x28, #3024]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -5782,7 +5782,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2896]",
+        "ldr q5, [x28, #3024]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",

unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json

@@ -2843,7 +2843,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2860,7 +2860,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2800]",
+        "ldr q5, [x28, #2928]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2876,7 +2876,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2893,7 +2893,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2832]",
+        "ldr q5, [x28, #2960]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2909,7 +2909,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2864]",
+        "ldr q2, [x28, #2992]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2926,7 +2926,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2864]",
+        "ldr q5, [x28, #2992]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v16.4s, v18.4s",
@@ -2942,7 +2942,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2896]",
+        "ldr q2, [x28, #3024]",
         "eor v2.16b, v17.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -2959,7 +2959,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2896]",
+        "ldr q5, [x28, #3024]",
         "eor v6.16b, v17.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v16.2d, v18.2d",
@@ -3879,7 +3879,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3896,7 +3896,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2800]",
+        "ldr q5, [x28, #2928]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3912,7 +3912,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3929,7 +3929,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2832]",
+        "ldr q5, [x28, #2960]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3945,7 +3945,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2864]",
+        "ldr q2, [x28, #2992]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3962,7 +3962,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2864]",
+        "ldr q5, [x28, #2992]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.4s, v17.4s, v16.4s",
@@ -3978,7 +3978,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2896]",
+        "ldr q2, [x28, #3024]",
         "eor v2.16b, v18.16b, v2.16b",
         "mov v0.16b, v2.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -3995,7 +3995,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2896]",
+        "ldr q5, [x28, #3024]",
         "eor v6.16b, v18.16b, v5.16b",
         "mov v0.16b, v6.16b",
         "fmla v0.2d, v17.2d, v16.2d",
@@ -4011,7 +4011,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4027,7 +4027,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2800]",
+        "ldr q5, [x28, #2928]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4042,7 +4042,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4058,7 +4058,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2832]",
+        "ldr q5, [x28, #2960]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4073,7 +4073,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2864]",
+        "ldr q2, [x28, #2992]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4089,7 +4089,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2864]",
+        "ldr q5, [x28, #2992]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.4s, v17.4s, v18.4s",
@@ -4104,7 +4104,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2896]",
+        "ldr q2, [x28, #3024]",
         "eor v2.16b, v16.16b, v2.16b",
         "mov v16.16b, v2.16b",
         "fmla v16.2d, v17.2d, v18.2d",
@@ -4120,7 +4120,7 @@
         "ldr q2, [x28, #32]",
         "ldr q3, [x28, #48]",
         "ldr q4, [x28, #64]",
-        "ldr q5, [x28, #2896]",
+        "ldr q5, [x28, #3024]",
         "eor v6.16b, v16.16b, v5.16b",
         "mov v16.16b, v6.16b",
         "fmla v16.2d, v17.2d, v18.2d",

unittests/InstructionCountCI/AVX128/VEX_map3.json

@@ -337,7 +337,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2960]",
+        "ldr q2, [x28, #3088]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
       ]
@@ -348,7 +348,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2976]",
+        "ldr q2, [x28, #3104]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
       ]
@@ -369,7 +369,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2992]",
+        "ldr q2, [x28, #3120]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
       ]
@@ -391,7 +391,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3008]",
+        "ldr q2, [x28, #3136]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
       ]
@@ -412,7 +412,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3024]",
+        "ldr q2, [x28, #3152]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
       ]
@@ -423,7 +423,7 @@
         "Map 3 0b01 0x02 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3168]",
         "tbx v16.16b, {v17.16b}, v2.16b",
         "stp xzr, xzr, [x28, #32]"
       ]
@@ -3488,7 +3488,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "ldr q3, [x28, #2944]",
+        "ldr q3, [x28, #3072]",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v2.16b",
         "tbl v16.16b, {v16.16b}, v3.16b",
@@ -3502,7 +3502,7 @@
       ],
       "ExpectedArm64ASM": [
         "movi v2.2d, #0x0",
-        "ldr q3, [x28, #2944]",
+        "ldr q3, [x28, #3072]",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v2.16b",
         "tbl v16.16b, {v16.16b}, v3.16b",

unittests/InstructionCountCI/Crypto/H0F38.json

@@ -31,7 +31,7 @@
         "0x66 0x0f 0x38 0xca"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q2, [x0, #432]",
         "tbl v3.16b, {v16.16b}, v2.16b",
         "tbl v4.16b, {v17.16b}, v2.16b",

unittests/InstructionCountCI/Crypto/H0F3A.json

@@ -55,7 +55,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2944]",
+        "ldr q2, [x28, #3072]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -68,7 +68,7 @@
         "0x66 0x0f 0x3a 0xdf"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2944]",
+        "ldr q2, [x28, #3072]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -84,9 +84,9 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3328]",
+        "ldr q2, [x28, #3456]",
         "movi v3.2d, #0x0",
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q4, [x0, #432]",
         "tbl v5.16b, {v16.16b}, v4.16b",
         "tbl v6.16b, {v17.16b}, v4.16b",
@@ -101,9 +101,9 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3344]",
+        "ldr q2, [x28, #3472]",
         "movi v3.2d, #0x0",
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q4, [x0, #432]",
         "tbl v5.16b, {v16.16b}, v4.16b",
         "tbl v6.16b, {v17.16b}, v4.16b",
@@ -118,9 +118,9 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3360]",
+        "ldr q2, [x28, #3488]",
         "movi v3.2d, #0x0",
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q4, [x0, #432]",
         "tbl v5.16b, {v16.16b}, v4.16b",
         "tbl v6.16b, {v17.16b}, v4.16b",
@@ -135,9 +135,9 @@
         "0x66 0x0f 0x3a 0xcc"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3376]",
+        "ldr q2, [x28, #3504]",
         "movi v3.2d, #0x0",
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q4, [x0, #432]",
         "tbl v5.16b, {v16.16b}, v4.16b",
         "tbl v6.16b, {v17.16b}, v4.16b",

unittests/InstructionCountCI/DDD.json

@@ -29,7 +29,7 @@
         "scvtf v2.2s, v2.2s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -44,7 +44,7 @@
         "scvtf v2.2s, v2.2s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -61,7 +61,7 @@
         "sxtl v2.4s, v2.4h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -77,7 +77,7 @@
         "fcvtzs v2.2s, v2.2s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -93,7 +93,7 @@
         "fdiv v2.4s, v0.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -113,7 +113,7 @@
         "bit v3.8b, v2.8b, v0.8b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d3, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -129,7 +129,7 @@
         "fsub v2.4s, v4.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -146,7 +146,7 @@
         "mov v2.s[1], v3.s[0]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -160,7 +160,7 @@
         "fcmge v2.4s, v3.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -175,7 +175,7 @@
         "bif v3.16b, v2.16b, v0.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d3, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -192,7 +192,7 @@
         "dup v2.2s, v2.s[0]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -213,7 +213,7 @@
         "dup v2.2s, v3.s[0]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -227,7 +227,7 @@
         "fsub v2.4s, v3.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -241,7 +241,7 @@
         "fadd v2.4s, v3.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -255,7 +255,7 @@
         "fcmgt v2.4s, v3.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -270,7 +270,7 @@
         "bit v3.16b, v2.16b, v0.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d3, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -282,7 +282,7 @@
         "ldr d2, [x28, #1056]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -299,7 +299,7 @@
         "ldr d2, [x28, #1056]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -318,7 +318,7 @@
         "fsub v2.4s, v2.4s, v3.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -332,7 +332,7 @@
         "fcmeq v2.4s, v3.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -346,7 +346,7 @@
         "fmul v2.4s, v3.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -358,7 +358,7 @@
         "ldr d2, [x28, #1056]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -384,7 +384,7 @@
         "shrn v2.4h, v2.4s, #16",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -397,7 +397,7 @@
         "rev64 v2.2s, v2.2s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -411,7 +411,7 @@
         "urhadd v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]

unittests/InstructionCountCI/FEXOpt/MultiInst.json

@@ -236,7 +236,7 @@
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x0], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x0], #64",
         "mov w0, #0xffff",
-        "str x0, [x28, #1312]",
+        "str x0, [x28, #1440]",
         "sub sp, sp, #0x40 (64)",
         "str x4, [sp]",
         "str x11, [sp, #8]",
@@ -245,8 +245,8 @@
         "str x14, [sp, #32]",
         "str x12, [sp, #40]",
         "str x13, [sp, #48]",
-        "ldr x0, [x28, #1392]",
-        "ldr x3, [x28, #1400]",
+        "ldr x0, [x28, #1520]",
+        "ldr x3, [x28, #1528]",
         "mov x1, x28",
         "mov x2, sp",
         "blr x3",
@@ -268,7 +268,7 @@
         "ldp x16, x17, [x28, #384]",
         "ldp x19, x29, [x28, #400]",
         "ldp w26, w27, [x28, #16]",
-        "str xzr, [x28, #1312]",
+        "str xzr, [x28, #1440]",
         "ld1 {v2.2d, v3.2d}, [sp], #32",
         "ld1 {v4.2d, v5.2d, v6.2d, v7.2d}, [sp], #64",
         "ld1 {v8.2d, v9.2d, v10.2d, v11.2d}, [sp], #64",

unittests/InstructionCountCI/FlagM/HotBlocks.json

@@ -895,8 +895,8 @@
         "mov v0.16b, v16.16b",
         "mov v1.16b, v17.16b",
         "mov w0, #0xd",
-        "ldr x1, [x28, #2128]",
-        "ldr x3, [x28, #2136]",
+        "ldr x1, [x28, #2256]",
+        "ldr x3, [x28, #2264]",
         "blr x1",
         "ldr x30, [sp], #16",
         "mov w20, w0",

unittests/InstructionCountCI/FlagM/HotBlocks_32Bit.json

@@ -354,11 +354,11 @@
         "ldrb w20, [x28, #1019]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "mov w22, #0x1",
         "lsl w20, w22, w20",
         "bic w20, w21, w20",
-        "strb w20, [x28, #1298]"
+        "strb w20, [x28, #1426]"
       ]
     }
   }

unittests/InstructionCountCI/FlagM/Primary_32Bit.json

@@ -21,14 +21,18 @@
       ]
     },
     "pop es": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 10,
       "Comment": "0x07",
       "ExpectedArm64ASM": [
         "ldr w20, [x8], #4",
         "strh w20, [x28, #928]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #944]"
       ]
     },
@@ -49,7 +53,7 @@
       ]
     },
     "pop ss": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 20,
       "Comment": "0x17",
       "ExpectedArm64ASM": [
         "ldr w20, [x8], #4",
@@ -64,8 +68,12 @@
         "strb w21, [x28, #984]",
         "strh w20, [x28, #932]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #952]",
         "msr nzcv, x12"
       ]
@@ -79,14 +87,18 @@
       ]
     },
     "pop ds": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 10,
       "Comment": "0x1f",
       "ExpectedArm64ASM": [
         "ldr w20, [x8], #4",
         "strh w20, [x28, #934]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #956]"
       ]
     },

unittests/InstructionCountCI/FlagM/Secondary.json

@@ -1604,7 +1604,7 @@
       "Comment": "0x0f 0xd7",
       "ExpectedArm64ASM": [
         "ldr d2, [x28, #1040]",
-        "ldr d3, [x28, #3056]",
+        "ldr d3, [x28, #3184]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.16b, v2.16b, v3.16b",
         "addp v2.16b, v2.16b, v2.16b",

unittests/InstructionCountCI/FlagM/SecondaryGroup.json

@@ -818,7 +818,7 @@
         "ushr v2.8h, v2.8h, #15",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -832,7 +832,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -874,7 +874,7 @@
         "sshr v2.8h, v2.8h, #15",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -888,7 +888,7 @@
         "sshr v2.8h, v2.8h, #15",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -930,7 +930,7 @@
         "shl v2.8h, v2.8h, #15",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -944,7 +944,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -986,7 +986,7 @@
         "ushr v2.4s, v2.4s, #31",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1000,7 +1000,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1042,7 +1042,7 @@
         "sshr v2.4s, v2.4s, #31",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1056,7 +1056,7 @@
         "sshr v2.4s, v2.4s, #31",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1098,7 +1098,7 @@
         "shl v2.4s, v2.4s, #31",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1112,7 +1112,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1154,7 +1154,7 @@
         "ushr v2.2d, v2.2d, #63",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1168,7 +1168,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1233,7 +1233,7 @@
         "shl v2.2d, v2.2d, #63",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1247,7 +1247,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1278,7 +1278,7 @@
       "ExpectedInstructionCount": 41,
       "Comment": "GROUP15 0x0F 0xAE /0",
       "ExpectedArm64ASM": [
-        "ldrh w20, [x28, #1296]",
+        "ldrh w20, [x28, #1424]",
         "strh w20, [x4]",
         "ldrb w20, [x28, #1019]",
         "lsl x20, x20, #11",
@@ -1293,7 +1293,7 @@
         "ldrb w21, [x28, #1008]",
         "orr x20, x20, x21",
         "strh w20, [x4, #2]",
-        "ldrb w20, [x28, #1298]",
+        "ldrb w20, [x28, #1426]",
         "strb w20, [x4, #4]",
         "ldr q2, [x28, #1040]",
         "ldr q3, [x28, #1056]",
@@ -1340,7 +1340,7 @@
       "Comment": "GROUP15 0x0F 0xAE /1",
       "ExpectedArm64ASM": [
         "ldrh w20, [x4]",
-        "strh w20, [x28, #1296]",
+        "strh w20, [x28, #1424]",
         "ldrh w20, [x4, #2]",
         "ubfx w21, w20, #11, #3",
         "strb w21, [x28, #1019]",
@@ -1376,7 +1376,7 @@
         "lsr x1, x22, #2",
         "bfi x0, x1, #24, #1",
         "msr fpcr, x0",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str q9, [x28, #1152]",
         "str q8, [x28, #1136]",
         "str q7, [x28, #1120]",
@@ -1464,7 +1464,7 @@
         "ubfx x20, x4, #0, #1",
         "cbnz x20, #+0x8",
         "b #+0x78",
-        "ldrh w20, [x28, #1296]",
+        "ldrh w20, [x28, #1424]",
         "strh w20, [x4]",
         "ldrb w20, [x28, #1019]",
         "lsl x20, x20, #11",
@@ -1479,7 +1479,7 @@
         "ldrb w21, [x28, #1008]",
         "orr x20, x20, x21",
         "strh w20, [x4, #2]",
-        "ldrb w20, [x28, #1298]",
+        "ldrb w20, [x28, #1426]",
         "strb w20, [x4, #4]",
         "ldr q2, [x28, #1040]",
         "ldr q3, [x28, #1056]",
@@ -1541,7 +1541,7 @@
         "ubfx x20, x4, #0, #1",
         "cbnz x20, #+0x8",
         "b #+0x78",
-        "ldrh w20, [x28, #1296]",
+        "ldrh w20, [x28, #1424]",
         "strh w20, [x4]",
         "ldrb w20, [x28, #1019]",
         "lsl x20, x20, #11",
@@ -1556,7 +1556,7 @@
         "ldrb w21, [x28, #1008]",
         "orr x20, x20, x21",
         "strh w20, [x4, #2]",
-        "ldrb w20, [x28, #1298]",
+        "ldrb w20, [x28, #1426]",
         "strb w20, [x4, #4]",
         "ldr q2, [x28, #1040]",
         "ldr q3, [x28, #1056]",
@@ -1628,7 +1628,7 @@
         "cbnz x20, #+0x8",
         "b #+0x74",
         "ldrh w20, [x4]",
-        "strh w20, [x28, #1296]",
+        "strh w20, [x28, #1424]",
         "ldrh w20, [x4, #2]",
         "ubfx w21, w20, #11, #3",
         "strb w21, [x28, #1019]",
@@ -1645,7 +1645,7 @@
         "ldp q4, q5, [x4, #64]",
         "ldp q6, q7, [x4, #96]",
         "ldp q8, q9, [x4, #128]",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str q9, [x28, #1152]",
         "str q8, [x28, #1136]",
         "str q7, [x28, #1120]",
@@ -1656,14 +1656,14 @@
         "str q2, [x28, #1040]",
         "b #+0x48",
         "mov w20, #0x37f",
-        "strh w20, [x28, #1296]",
+        "strh w20, [x28, #1424]",
         "strb wzr, [x28, #1019]",
         "strb wzr, [x28, #1016]",
         "strb wzr, [x28, #1017]",
         "strb wzr, [x28, #1018]",
         "strb wzr, [x28, #1022]",
         "movi v2.2d, #0x0",
-        "strb wzr, [x28, #1298]",
+        "strb wzr, [x28, #1426]",
         "str q2, [x28, #1152]",
         "str q2, [x28, #1136]",
         "str q2, [x28, #1120]",

unittests/InstructionCountCI/FlagM/SecondaryModRM.json

@@ -42,8 +42,8 @@
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
         "mov w1, w7",
-        "ldr x0, [x28, #1368]",
-        "ldr x2, [x28, #1384]",
+        "ldr x0, [x28, #1496]",
+        "ldr x2, [x28, #1512]",
         "blr x2",
         "ldr x25, [x28, #1024]",
         "ldr w4, [x28, #1000]",

unittests/InstructionCountCI/FlagM/Secondary_OpSize.json

@@ -37,7 +37,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3056]",
+        "ldr q2, [x28, #3184]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",

unittests/InstructionCountCI/FlagM/VEX_map1.json

@@ -68,7 +68,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3056]",
+        "ldr q2, [x28, #3184]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
@@ -83,7 +83,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2288]",
+        "ldr x0, [x28, #2416]",
         "ld1b {z2.b}, p7/z, [x0]",
         "mrs x0, nzcv",
         "mov z0.d, #0",

unittests/InstructionCountCI/H0F38.json

@@ -25,7 +25,7 @@
         "tbl v2.8b, {v2.16b}, v3.8b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -52,7 +52,7 @@
         "addp v2.4h, v3.4h, v2.4h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -77,7 +77,7 @@
         "addp v2.2s, v3.2s, v2.2s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -104,7 +104,7 @@
         "sqadd v2.8h, v4.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -136,7 +136,7 @@
         "sqxtn v2.4h, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -175,7 +175,7 @@
         "sub v2.8h, v4.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -204,7 +204,7 @@
         "sub v2.4s, v4.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -233,7 +233,7 @@
         "sqsub v2.8h, v4.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -262,7 +262,7 @@
         "mul v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -291,7 +291,7 @@
         "mul v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -320,7 +320,7 @@
         "mul v2.4s, v3.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -352,7 +352,7 @@
         "shrn v2.4h, v2.4s, #1",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -469,7 +469,7 @@
         "abs v2.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -493,7 +493,7 @@
         "abs v2.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -517,7 +517,7 @@
         "abs v2.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -685,7 +685,7 @@
         "0x66 0x0f 0x38 0x41"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2768]",
+        "ldr q2, [x28, #2896]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",

unittests/InstructionCountCI/H0F3A.json

@@ -23,7 +23,7 @@
         "ldr d2, [x28, #1056]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -39,7 +39,7 @@
         "ext v2.8b, v2.8b, v3.8b, #1",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -53,7 +53,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -327,7 +327,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2960]",
+        "ldr q2, [x28, #3088]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -337,7 +337,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2976]",
+        "ldr q2, [x28, #3104]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -356,7 +356,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2992]",
+        "ldr q2, [x28, #3120]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -376,7 +376,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3008]",
+        "ldr q2, [x28, #3136]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -395,7 +395,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3024]",
+        "ldr q2, [x28, #3152]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -405,7 +405,7 @@
         "0x66 0x0f 0x3a 0x0c"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3040]",
+        "ldr q2, [x28, #3168]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]
     },
@@ -474,7 +474,7 @@
         "0x66 0x0f 0x3a 0x0e"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2504]",
+        "ldr x0, [x28, #2632]",
         "ldr q2, [x0, #3440]",
         "tbx v16.16b, {v17.16b}, v2.16b"
       ]

unittests/InstructionCountCI/Primary.json

@@ -2474,38 +2474,50 @@
       "Comment": "0x8e"
     },
     "mov es, ax": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 10,
       "Comment": "0x8e",
       "ExpectedArm64ASM": [
         "uxth w20, w4",
         "strh w20, [x28, #928]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #944]"
       ]
     },
     "mov ss, ax": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 10,
       "Comment": "0x8e",
       "ExpectedArm64ASM": [
         "uxth w20, w4",
         "strh w20, [x28, #932]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #952]"
       ]
     },
     "mov ds, ax": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 10,
       "Comment": "0x8e",
       "ExpectedArm64ASM": [
         "uxth w20, w4",
         "strh w20, [x28, #934]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #956]"
       ]
     },

unittests/InstructionCountCI/PrimaryGroup.json

@@ -2786,7 +2786,7 @@
         "mov x0, x5",
         "mov x1, x4",
         "mov x2, x6",
-        "ldr x3, [x28, #3424]",
+        "ldr x3, [x28, #3552]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",
@@ -2837,7 +2837,7 @@
         "mov x0, x5",
         "mov x1, x4",
         "mov x2, x6",
-        "ldr x3, [x28, #3432]",
+        "ldr x3, [x28, #3560]",
         "str x30, [sp, #-16]!",
         "blr x3",
         "ldr x30, [sp], #16",

unittests/InstructionCountCI/Primary_32Bit.json

@@ -20,14 +20,18 @@
       ]
     },
     "pop es": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 10,
       "Comment": "0x07",
       "ExpectedArm64ASM": [
         "ldr w20, [x8], #4",
         "strh w20, [x28, #928]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #944]"
       ]
     },
@@ -48,7 +52,7 @@
       ]
     },
     "pop ss": {
-      "ExpectedInstructionCount": 16,
+      "ExpectedInstructionCount": 20,
       "Comment": "0x17",
       "ExpectedArm64ASM": [
         "ldr w20, [x8], #4",
@@ -63,8 +67,12 @@
         "strb w21, [x28, #984]",
         "strh w20, [x28, #932]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #952]",
         "msr nzcv, x12"
       ]
@@ -78,14 +86,18 @@
       ]
     },
     "pop ds": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 10,
       "Comment": "0x1f",
       "ExpectedArm64ASM": [
         "ldr w20, [x8], #4",
         "strh w20, [x28, #934]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #956]"
       ]
     },

unittests/InstructionCountCI/RPRES/DDD.json

@@ -23,7 +23,7 @@
         "fmul v2.2s, v0.2s, v1.2s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -44,7 +44,7 @@
         "bit v3.8b, v2.8b, v0.8b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d3, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -62,7 +62,7 @@
         "dup v2.2s, v2.s[0]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -84,7 +84,7 @@
         "dup v2.2s, v3.s[0]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]

unittests/InstructionCountCI/SSE42_Strings.json

@@ -41,8 +41,8 @@
         "0x66 0x0f 0x3A 0x60"
       ],
       "ExpectedArm64ASM": [
-        "ldr x3, [x28, #2112]",
-        "ldr x0, [x28, #2120]",
+        "ldr x3, [x28, #2240]",
+        "ldr x0, [x28, #2248]",
         "stp x0, x30, [sp, #-16]!",
         "mov x0, x4",
         "mov x1, x5",
@@ -66,8 +66,8 @@
         "0x66 0x0f 0x3A 0x61"
       ],
       "ExpectedArm64ASM": [
-        "ldr x3, [x28, #2112]",
-        "ldr x0, [x28, #2120]",
+        "ldr x3, [x28, #2240]",
+        "ldr x0, [x28, #2248]",
         "stp x0, x30, [sp, #-16]!",
         "mov x0, x4",
         "mov x1, x5",
@@ -99,8 +99,8 @@
         "mov v0.16b, v16.16b",
         "mov v1.16b, v17.16b",
         "mov w0, #0x0",
-        "ldr x1, [x28, #2128]",
-        "ldr x3, [x28, #2136]",
+        "ldr x1, [x28, #2256]",
+        "ldr x3, [x28, #2264]",
         "blr x1",
         "ldr x30, [sp], #16",
         "mov w20, w0",
@@ -122,8 +122,8 @@
         "mov v0.16b, v16.16b",
         "mov v1.16b, v17.16b",
         "mov w0, #0x0",
-        "ldr x1, [x28, #2128]",
-        "ldr x3, [x28, #2136]",
+        "ldr x1, [x28, #2256]",
+        "ldr x3, [x28, #2264]",
         "blr x1",
         "ldr x30, [sp], #16",
         "mov w20, w0",

unittests/InstructionCountCI/Secondary.json

@@ -24,7 +24,7 @@
       "ExpectedInstructionCount": 1,
       "Comment": "0x0f 0x0b",
       "ExpectedArm64ASM": [
-        "strb wzr, [x28, #1298]"
+        "strb wzr, [x28, #1426]"
       ]
     },
     "movups xmm0, xmm0": {
@@ -178,7 +178,7 @@
         "ldr d2, [x4]",
         "frint32z v2.4s, v2.4s",
         "fcvtzs v2.2s, v2.2s",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -191,7 +191,7 @@
         "mov w20, #0xffff",
         "frint32z v2.4s, v16.4s",
         "fcvtzs v2.4s, v2.4s",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -205,7 +205,7 @@
         "ldr d2, [x4]",
         "frint32x v2.4s, v2.4s",
         "fcvtzs v2.2s, v2.2s",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -218,7 +218,7 @@
         "mov w20, #0xffff",
         "frint32x v2.4s, v16.4s",
         "fcvtzs v2.4s, v2.4s",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -648,7 +648,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #2928]",
+        "ldr q3, [x28, #3056]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -659,7 +659,7 @@
       "Comment": "0x0f 0x50",
       "ExpectedArm64ASM": [
         "ushr v2.4s, v16.4s, #31",
-        "ldr q3, [x28, #2928]",
+        "ldr q3, [x28, #3056]",
         "ushl v2.4s, v2.4s, v3.4s",
         "addv s2, v2.4s",
         "mov w4, v2.s[0]"
@@ -803,7 +803,7 @@
         "zip1 v2.8b, v2.8b, v3.8b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -817,7 +817,7 @@
         "zip1 v2.8b, v2.8b, v3.8b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -831,7 +831,7 @@
         "zip1 v2.4h, v2.4h, v3.4h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -845,7 +845,7 @@
         "zip1 v2.4h, v2.4h, v3.4h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -859,7 +859,7 @@
         "zip1 v2.2s, v2.2s, v3.2s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -873,7 +873,7 @@
         "zip1 v2.2s, v2.2s, v3.2s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -888,7 +888,7 @@
         "sqxtn v2.8b, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -903,7 +903,7 @@
         "sqxtn v2.8b, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -917,7 +917,7 @@
         "sqxtn v2.8b, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -931,7 +931,7 @@
         "cmgt v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -945,7 +945,7 @@
         "cmgt v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -959,7 +959,7 @@
         "cmgt v2.4s, v3.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -973,7 +973,7 @@
         "zip2 v2.8b, v2.8b, v3.8b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -987,7 +987,7 @@
         "zip2 v2.8b, v2.8b, v3.8b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1001,7 +1001,7 @@
         "zip2 v2.4h, v2.4h, v3.4h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1015,7 +1015,7 @@
         "zip2 v2.4h, v2.4h, v3.4h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1029,7 +1029,7 @@
         "zip2 v2.2s, v2.2s, v3.2s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1043,7 +1043,7 @@
         "zip2 v2.2s, v2.2s, v3.2s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1058,7 +1058,7 @@
         "sqxtn v2.4h, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1070,7 +1070,7 @@
         "fmov s2, w4",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1082,7 +1082,7 @@
         "ldr s2, [x4]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1094,7 +1094,7 @@
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
         "ldr d2, [x28, #1040]",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1106,7 +1106,7 @@
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
         "ldr d2, [x28, #1056]",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1118,7 +1118,7 @@
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
         "ldr d2, [x4]",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1131,7 +1131,7 @@
         "dup v2.4h, v2.h[0]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1144,7 +1144,7 @@
         "dup v2.4h, v2.h[0]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1154,12 +1154,12 @@
       "Comment": "0x0f 0x70",
       "ExpectedArm64ASM": [
         "ldr d2, [x28, #1056]",
-        "ldr x0, [x28, #2456]",
+        "ldr x0, [x28, #2584]",
         "ldr d3, [x0, #16]",
         "tbl v2.8b, {v2.16b}, v3.8b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1169,12 +1169,12 @@
       "Comment": "0x0f 0x70",
       "ExpectedArm64ASM": [
         "ldr d2, [x4]",
-        "ldr x0, [x28, #2456]",
+        "ldr x0, [x28, #2584]",
         "ldr d3, [x0, #16]",
         "tbl v2.8b, {v2.16b}, v3.8b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1187,7 +1187,7 @@
         "dup v2.4h, v2.h[3]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1200,7 +1200,7 @@
         "dup v2.4h, v2.h[3]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1214,7 +1214,7 @@
         "cmeq v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1228,7 +1228,7 @@
         "cmeq v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1242,7 +1242,7 @@
         "cmeq v2.4s, v3.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1251,7 +1251,7 @@
       "ExpectedInstructionCount": 1,
       "Comment": "0x0f 0x77",
       "ExpectedArm64ASM": [
-        "strb wzr, [x28, #1298]"
+        "strb wzr, [x28, #1426]"
       ]
     },
     "movd eax, mm0": {
@@ -1281,7 +1281,7 @@
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
         "ldr d2, [x28, #1040]",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1056]",
         "strh w20, [x28, #1064]"
       ]
@@ -1294,7 +1294,7 @@
         "mov w20, #0xffff",
         "ldr d2, [x28, #1040]",
         "str d2, [x4]",
-        "strb w20, [x28, #1298]"
+        "strb w20, [x28, #1426]"
       ]
     },
     "seto al": {
@@ -1440,14 +1440,18 @@
       ]
     },
     "pop fs": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 10,
       "Comment": "0x0f 0xa1",
       "ExpectedArm64ASM": [
         "ldr x20, [x8], #8",
         "strh w20, [x28, #938]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #968]"
       ]
     },
@@ -1835,14 +1839,18 @@
       ]
     },
     "pop gs": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 10,
       "Comment": "0x0f 0xa9",
       "ExpectedArm64ASM": [
         "ldr x20, [x8], #8",
         "strh w20, [x28, #936]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #960]"
       ]
     },
@@ -2872,7 +2880,7 @@
         "mov v2.h[0], w4",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -2885,7 +2893,7 @@
         "mov v2.h[1], w4",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -2898,7 +2906,7 @@
         "mov v2.h[2], w4",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -2911,7 +2919,7 @@
         "mov v2.h[3], w4",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -2924,7 +2932,7 @@
         "mov v2.h[0], w4",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -2937,7 +2945,7 @@
         "ld1 {v2.h}[0], [x4]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -2950,7 +2958,7 @@
         "ld1 {v2.h}[1], [x4]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -2963,7 +2971,7 @@
         "ld1 {v2.h}[2], [x4]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -2976,7 +2984,7 @@
         "ld1 {v2.h}[3], [x4]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -2989,7 +2997,7 @@
         "ld1 {v2.h}[0], [x4]",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3512,7 +3520,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v16.16b, v17.16b}, v2.16b"
       ]
@@ -3521,7 +3529,7 @@
       "ExpectedInstructionCount": 5,
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q2, [x0, #16]",
         "mov v0.16b, v17.16b",
         "mov v1.16b, v16.16b",
@@ -3533,7 +3541,7 @@
       "Comment": "0x0f 0xc6",
       "ExpectedArm64ASM": [
         "ldr q2, [x4]",
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q3, [x0, #16]",
         "mov v0.16b, v16.16b",
         "mov v1.16b, v2.16b",
@@ -3577,7 +3585,7 @@
         "ushl v2.8h, v2.8h, v0.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3595,7 +3603,7 @@
         "ushl v2.4s, v2.4s, v0.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3613,7 +3621,7 @@
         "ushl v2.2d, v2.2d, v0.2d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3627,7 +3635,7 @@
         "add v2.2d, v3.2d, v2.2d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3641,7 +3649,7 @@
         "mul v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3651,7 +3659,7 @@
       "Comment": "0x0f 0xd7",
       "ExpectedArm64ASM": [
         "ldr d2, [x28, #1040]",
-        "ldr d3, [x28, #3056]",
+        "ldr d3, [x28, #3184]",
         "cmlt v2.16b, v2.16b, #0",
         "and v2.16b, v2.16b, v3.16b",
         "addp v2.16b, v2.16b, v2.16b",
@@ -3669,7 +3677,7 @@
         "uqsub v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3683,7 +3691,7 @@
         "uqsub v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3697,7 +3705,7 @@
         "umin v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3711,7 +3719,7 @@
         "and v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3725,7 +3733,7 @@
         "uqadd v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3739,7 +3747,7 @@
         "uqadd v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3753,7 +3761,7 @@
         "umax v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3767,7 +3775,7 @@
         "bic v2.16b, v2.16b, v3.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3781,7 +3789,7 @@
         "urhadd v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3799,7 +3807,7 @@
         "sshl v2.8h, v2.8h, v0.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3817,7 +3825,7 @@
         "sshl v2.4s, v2.4s, v0.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3831,7 +3839,7 @@
         "urhadd v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3846,7 +3854,7 @@
         "shrn v2.4h, v2.4s, #16",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3861,7 +3869,7 @@
         "shrn v2.4h, v2.4s, #16",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3883,7 +3891,7 @@
         "sqsub v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3897,7 +3905,7 @@
         "sqsub v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3911,7 +3919,7 @@
         "smin v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3925,7 +3933,7 @@
         "orr v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3939,7 +3947,7 @@
         "sqadd v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3953,7 +3961,7 @@
         "sqadd v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3967,7 +3975,7 @@
         "smax v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3981,7 +3989,7 @@
         "eor v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -3993,7 +4001,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4010,7 +4018,7 @@
         "ushl v2.8h, v2.8h, v0.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4027,7 +4035,7 @@
         "ushl v2.4s, v2.4s, v0.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4044,7 +4052,7 @@
         "ushl v2.2d, v2.2d, v0.2d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4058,7 +4066,7 @@
         "umull v2.2d, v2.2s, v3.2s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4073,7 +4081,7 @@
         "addp v2.4s, v2.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4088,7 +4096,7 @@
         "addv h2, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4114,7 +4122,7 @@
         "sub v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4128,7 +4136,7 @@
         "sub v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4142,7 +4150,7 @@
         "sub v2.4s, v3.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4156,7 +4164,7 @@
         "sub v2.2d, v3.2d, v2.2d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4170,7 +4178,7 @@
         "add v2.16b, v3.16b, v2.16b",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4184,7 +4192,7 @@
         "add v2.8h, v3.8h, v2.8h",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -4198,7 +4206,7 @@
         "add v2.4s, v3.4s, v2.4s",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]

unittests/InstructionCountCI/SecondaryGroup.json

@@ -1032,7 +1032,7 @@
         "str x25, [x28, #1024]",
         "str x8, [x28, #320]",
         "mov w0, #0x100",
-        "str x0, [x28, #1312]",
+        "str x0, [x28, #1440]",
         "sub sp, sp, #0x10 (16)",
         "mov w8, #0xa8",
         "mov x0, sp",
@@ -1044,7 +1044,7 @@
         "ldr w8, [x28, #1000]",
         "msr nzcv, x8",
         "ldr x8, [x28, #320]",
-        "str xzr, [x28, #1312]",
+        "str xzr, [x28, #1440]",
         "orr x20, x0, x1, lsl #12",
         "mov w4, w20"
       ]
@@ -1058,7 +1058,7 @@
         "str x25, [x28, #1024]",
         "str x8, [x28, #320]",
         "mov w0, #0x100",
-        "str x0, [x28, #1312]",
+        "str x0, [x28, #1440]",
         "sub sp, sp, #0x10 (16)",
         "mov w8, #0xa8",
         "mov x0, sp",
@@ -1070,7 +1070,7 @@
         "ldr w8, [x28, #1000]",
         "msr nzcv, x8",
         "ldr x8, [x28, #320]",
-        "str xzr, [x28, #1312]",
+        "str xzr, [x28, #1440]",
         "orr x20, x0, x1, lsl #12",
         "mov w4, w20"
       ]
@@ -1090,7 +1090,7 @@
         "ushr v2.8h, v2.8h, #15",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1104,7 +1104,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1146,7 +1146,7 @@
         "sshr v2.8h, v2.8h, #15",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1160,7 +1160,7 @@
         "sshr v2.8h, v2.8h, #15",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1202,7 +1202,7 @@
         "shl v2.8h, v2.8h, #15",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1216,7 +1216,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1258,7 +1258,7 @@
         "ushr v2.4s, v2.4s, #31",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1272,7 +1272,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1314,7 +1314,7 @@
         "sshr v2.4s, v2.4s, #31",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1328,7 +1328,7 @@
         "sshr v2.4s, v2.4s, #31",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1370,7 +1370,7 @@
         "shl v2.4s, v2.4s, #31",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1384,7 +1384,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1426,7 +1426,7 @@
         "ushr v2.2d, v2.2d, #63",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1440,7 +1440,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1505,7 +1505,7 @@
         "shl v2.2d, v2.2d, #63",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1519,7 +1519,7 @@
         "movi v2.2d, #0x0",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -1550,7 +1550,7 @@
       "ExpectedInstructionCount": 41,
       "Comment": "GROUP15 0x0F 0xAE /0",
       "ExpectedArm64ASM": [
-        "ldrh w20, [x28, #1296]",
+        "ldrh w20, [x28, #1424]",
         "strh w20, [x4]",
         "ldrb w20, [x28, #1019]",
         "lsl x20, x20, #11",
@@ -1565,7 +1565,7 @@
         "ldrb w21, [x28, #1008]",
         "orr x20, x20, x21",
         "strh w20, [x4, #2]",
-        "ldrb w20, [x28, #1298]",
+        "ldrb w20, [x28, #1426]",
         "strb w20, [x4, #4]",
         "ldr q2, [x28, #1040]",
         "ldr q3, [x28, #1056]",
@@ -1612,7 +1612,7 @@
       "Comment": "GROUP15 0x0F 0xAE /1",
       "ExpectedArm64ASM": [
         "ldrh w20, [x4]",
-        "strh w20, [x28, #1296]",
+        "strh w20, [x28, #1424]",
         "ldrh w20, [x4, #2]",
         "ubfx w21, w20, #11, #3",
         "strb w21, [x28, #1019]",
@@ -1648,7 +1648,7 @@
         "lsr x1, x22, #2",
         "bfi x0, x1, #24, #1",
         "msr fpcr, x0",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str q9, [x28, #1152]",
         "str q8, [x28, #1136]",
         "str q7, [x28, #1120]",
@@ -1736,7 +1736,7 @@
         "ubfx x20, x4, #0, #1",
         "cbnz x20, #+0x8",
         "b #+0x78",
-        "ldrh w20, [x28, #1296]",
+        "ldrh w20, [x28, #1424]",
         "strh w20, [x4]",
         "ldrb w20, [x28, #1019]",
         "lsl x20, x20, #11",
@@ -1751,7 +1751,7 @@
         "ldrb w21, [x28, #1008]",
         "orr x20, x20, x21",
         "strh w20, [x4, #2]",
-        "ldrb w20, [x28, #1298]",
+        "ldrb w20, [x28, #1426]",
         "strb w20, [x4, #4]",
         "ldr q2, [x28, #1040]",
         "ldr q3, [x28, #1056]",
@@ -1823,7 +1823,7 @@
         "cbnz x20, #+0x8",
         "b #+0x74",
         "ldrh w20, [x4]",
-        "strh w20, [x28, #1296]",
+        "strh w20, [x28, #1424]",
         "ldrh w20, [x4, #2]",
         "ubfx w21, w20, #11, #3",
         "strb w21, [x28, #1019]",
@@ -1840,7 +1840,7 @@
         "ldp q4, q5, [x4, #64]",
         "ldp q6, q7, [x4, #96]",
         "ldp q8, q9, [x4, #128]",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str q9, [x28, #1152]",
         "str q8, [x28, #1136]",
         "str q7, [x28, #1120]",
@@ -1851,14 +1851,14 @@
         "str q2, [x28, #1040]",
         "b #+0x48",
         "mov w20, #0x37f",
-        "strh w20, [x28, #1296]",
+        "strh w20, [x28, #1424]",
         "strb wzr, [x28, #1019]",
         "strb wzr, [x28, #1016]",
         "strb wzr, [x28, #1017]",
         "strb wzr, [x28, #1018]",
         "strb wzr, [x28, #1022]",
         "movi v2.2d, #0x0",
-        "strb wzr, [x28, #1298]",
+        "strb wzr, [x28, #1426]",
         "str q2, [x28, #1152]",
         "str q2, [x28, #1136]",
         "str q2, [x28, #1120]",

unittests/InstructionCountCI/SecondaryModRM.json

@@ -42,8 +42,8 @@
         "st1 {v24.2d, v25.2d, v26.2d, v27.2d}, [x3], #64",
         "st1 {v28.2d, v29.2d, v30.2d, v31.2d}, [x3], #64",
         "mov w1, w7",
-        "ldr x0, [x28, #1368]",
-        "ldr x2, [x28, #1384]",
+        "ldr x0, [x28, #1496]",
+        "ldr x2, [x28, #1512]",
         "blr x2",
         "ldr x25, [x28, #1024]",
         "ldr w4, [x28, #1000]",

unittests/InstructionCountCI/Secondary_32Bit.json

@@ -18,14 +18,18 @@
       ]
     },
     "pop fs": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 10,
       "Comment": "0x0f 0xa1",
       "ExpectedArm64ASM": [
         "ldr w20, [x8], #4",
         "strh w20, [x28, #938]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #968]"
       ]
     },
@@ -38,14 +42,18 @@
       ]
     },
     "pop gs": {
-      "ExpectedInstructionCount": 6,
+      "ExpectedInstructionCount": 10,
       "Comment": "0x0f 0xa9",
       "ExpectedArm64ASM": [
         "ldr w20, [x8], #4",
         "strh w20, [x28, #936]",
         "ubfx w20, w20, #3, #13",
-        "add x0, x28, x20, lsl #2",
-        "ldr w20, [x0, #1168]",
+        "add x0, x28, x20, lsl #3",
+        "ldr x20, [x0, #1168]",
+        "lsr x21, x20, #32",
+        "and w22, w21, #0xff000000",
+        "orr w20, w22, w20, lsr #16",
+        "bfi w20, w21, #16, #8",
         "str w20, [x28, #960]"
       ]
     }

unittests/InstructionCountCI/Secondary_OpSize.json

@@ -133,7 +133,7 @@
         "frint32z v2.2d, v16.2d",
         "fcvtzs v2.2d, v2.2d",
         "xtn v2.2s, v2.2d",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -147,7 +147,7 @@
         "frint32x v2.2d, v16.2d",
         "fcvtzs v2.2d, v2.2d",
         "xtn v2.2s, v2.2d",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -522,7 +522,7 @@
         "0x66 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b"
       ]
@@ -536,7 +536,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x4]",
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q3, [x0, #16]",
         "tbl v16.16b, {v2.16b}, v3.16b"
       ]
@@ -674,7 +674,7 @@
       ],
       "ExpectedArm64ASM": [
         "ldr q2, [x4]",
-        "ldr x0, [x28, #2472]",
+        "ldr x0, [x28, #2600]",
         "ldr q3, [x0, #2480]",
         "tbl v16.16b, {v2.16b}, v3.16b"
       ]
@@ -1226,7 +1226,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0x66 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.2d, v16.2d, v2.2d"
       ]
@@ -1282,7 +1282,7 @@
       "ExpectedInstructionCount": 7,
       "Comment": "0x66 0x0f 0xd7",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3056]",
+        "ldr q2, [x28, #3184]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",

unittests/InstructionCountCI/Secondary_REP.json

@@ -118,7 +118,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, s16",
         "mov w21, #0x80000000",
-        "ldr s2, [x28, #3184]",
+        "ldr s2, [x28, #3312]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel w4, w20, w21, gt",
@@ -132,7 +132,7 @@
         "ldr s2, [x6]",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3184]",
+        "ldr s3, [x28, #3312]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -145,7 +145,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, s16",
         "mov x21, #0x8000000000000000",
-        "ldr s2, [x28, #3216]",
+        "ldr s2, [x28, #3344]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel x4, x20, x21, gt",
@@ -159,7 +159,7 @@
         "ldr s2, [x6]",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3216]",
+        "ldr s3, [x28, #3344]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -173,7 +173,7 @@
         "frinti s2, s16",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3184]",
+        "ldr s3, [x28, #3312]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -188,7 +188,7 @@
         "frinti s2, s2",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3184]",
+        "ldr s3, [x28, #3312]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -202,7 +202,7 @@
         "frinti s2, s16",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3216]",
+        "ldr s3, [x28, #3344]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -217,7 +217,7 @@
         "frinti s2, s2",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3216]",
+        "ldr s3, [x28, #3344]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -296,8 +296,8 @@
       "ExpectedInstructionCount": 6,
       "Comment": "0xf3 0x0f 0x5b",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3280]",
-        "ldr q3, [x28, #3184]",
+        "ldr q2, [x28, #3408]",
+        "ldr q3, [x28, #3312]",
         "fcvtzs v4.4s, v17.4s",
         "fcmgt v3.4s, v3.4s, v17.4s",
         "mov v16.16b, v3.16b",
@@ -397,7 +397,7 @@
         "0xf3 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2464]",
+        "ldr x0, [x28, #2592]",
         "ldr q2, [x0, #1280]",
         "tbl v16.16b, {v17.16b}, v2.16b"
       ]
@@ -410,7 +410,7 @@
         "0xf3 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2464]",
+        "ldr x0, [x28, #2592]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b"
       ]

unittests/InstructionCountCI/Secondary_REPNE.json

@@ -290,7 +290,7 @@
         "0xf2 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2456]",
+        "ldr x0, [x28, #2584]",
         "ldr q2, [x0, #1280]",
         "tbl v16.16b, {v17.16b}, v2.16b"
       ]
@@ -303,7 +303,7 @@
         "0xf2 0x0f 0x70"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2456]",
+        "ldr x0, [x28, #2584]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b}, v2.16b"
       ]
@@ -459,7 +459,7 @@
       "ExpectedInstructionCount": 3,
       "Comment": "0xf2 0x0f 0xd0",
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v17.16b, v2.16b",
         "fadd v16.4s, v16.4s, v2.4s"
       ]
@@ -470,7 +470,7 @@
       "ExpectedArm64ASM": [
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d16, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]

unittests/InstructionCountCI/Secondary_SVE128.json

@@ -41,7 +41,7 @@
         "lsr z2.h, p6/m, z2.h, z3.d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -55,7 +55,7 @@
         "lsr z2.s, p6/m, z2.s, z3.d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -69,7 +69,7 @@
         "lsr z2.d, p6/m, z2.d, z3.d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -83,7 +83,7 @@
         "asr z2.h, p6/m, z2.h, z3.d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -97,7 +97,7 @@
         "asr z2.s, p6/m, z2.s, z3.d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -111,7 +111,7 @@
         "lsl z2.h, p6/m, z2.h, z3.d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -125,7 +125,7 @@
         "lsl z2.s, p6/m, z2.s, z3.d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]
@@ -139,7 +139,7 @@
         "lsl z2.d, p6/m, z2.d, z3.d",
         "strb wzr, [x28, #1019]",
         "mov w20, #0xffff",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "str d2, [x28, #1040]",
         "strh w20, [x28, #1048]"
       ]

unittests/InstructionCountCI/VEX_map1.json

@@ -2788,7 +2788,7 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q2, [x0, #16]",
         "tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
       ]
@@ -2857,7 +2857,7 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q2, [x0, #32]",
         "tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
       ]
@@ -2926,7 +2926,7 @@
         "Map 1 0b00 0xC6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2480]",
+        "ldr x0, [x28, #2608]",
         "ldr q2, [x0, #48]",
         "tbl v16.16b, {v17.16b, v18.16b}, v2.16b"
       ]
@@ -3271,7 +3271,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, s16",
         "mov w21, #0x80000000",
-        "ldr s2, [x28, #3184]",
+        "ldr s2, [x28, #3312]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel w4, w20, w21, gt",
@@ -3286,7 +3286,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, s16",
         "mov x21, #0x8000000000000000",
-        "ldr s2, [x28, #3216]",
+        "ldr s2, [x28, #3344]",
         "mrs x22, nzcv",
         "fcmp s2, s16",
         "csel x4, x20, x21, gt",
@@ -3301,7 +3301,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs w20, d16",
         "mov w21, #0x80000000",
-        "ldr d2, [x28, #3232]",
+        "ldr d2, [x28, #3360]",
         "mrs x22, nzcv",
         "fcmp d2, d16",
         "csel w4, w20, w21, gt",
@@ -3316,7 +3316,7 @@
       "ExpectedArm64ASM": [
         "fcvtzs x20, d16",
         "mov x21, #0x8000000000000000",
-        "ldr d2, [x28, #3264]",
+        "ldr d2, [x28, #3392]",
         "mrs x22, nzcv",
         "fcmp d2, d16",
         "csel x4, x20, x21, gt",
@@ -3332,7 +3332,7 @@
         "frinti s2, s16",
         "fcvtzs w20, s2",
         "mov w21, #0x80000000",
-        "ldr s3, [x28, #3184]",
+        "ldr s3, [x28, #3312]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel w4, w20, w21, gt",
@@ -3348,7 +3348,7 @@
         "frinti s2, s16",
         "fcvtzs x20, s2",
         "mov x21, #0x8000000000000000",
-        "ldr s3, [x28, #3216]",
+        "ldr s3, [x28, #3344]",
         "mrs x22, nzcv",
         "fcmp s3, s2",
         "csel x4, x20, x21, gt",
@@ -3364,7 +3364,7 @@
         "frinti d2, d16",
         "fcvtzs w20, d2",
         "mov w21, #0x80000000",
-        "ldr d3, [x28, #3232]",
+        "ldr d3, [x28, #3360]",
         "mrs x22, nzcv",
         "fcmp d3, d2",
         "csel w4, w20, w21, gt",
@@ -3380,7 +3380,7 @@
         "frinti d2, d16",
         "fcvtzs x20, d2",
         "mov x21, #0x8000000000000000",
-        "ldr d3, [x28, #3264]",
+        "ldr d3, [x28, #3392]",
         "mrs x22, nzcv",
         "fcmp d3, d2",
         "csel x4, x20, x21, gt",
@@ -3643,8 +3643,8 @@
       ],
       "ExpectedArm64ASM": [
         "frinti v2.4s, v17.4s",
-        "ldr q3, [x28, #3280]",
-        "ldr q4, [x28, #3184]",
+        "ldr q3, [x28, #3408]",
+        "ldr q4, [x28, #3312]",
         "fcvtzs v5.4s, v2.4s",
         "fcmgt v2.4s, v4.4s, v2.4s",
         "mov v16.16b, v2.16b",
@@ -3658,9 +3658,9 @@
       ],
       "ExpectedArm64ASM": [
         "frinti z2.s, p7/m, z17.s",
-        "ldr x0, [x28, #2400]",
+        "ldr x0, [x28, #2528]",
         "ld1b {z3.b}, p7/z, [x0]",
-        "ldr x0, [x28, #2352]",
+        "ldr x0, [x28, #2480]",
         "ld1b {z4.b}, p7/z, [x0]",
         "fcvtzs z5.s, p7/m, z2.s",
         "fcmgt p0.s, p7/z, z4.s, z2.s",
@@ -3678,8 +3678,8 @@
         "Map 1 0b10 0x5b 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3280]",
-        "ldr q3, [x28, #3184]",
+        "ldr q2, [x28, #3408]",
+        "ldr q3, [x28, #3312]",
         "fcvtzs v4.4s, v17.4s",
         "fcmgt v3.4s, v3.4s, v17.4s",
         "mov v16.16b, v3.16b",
@@ -3692,9 +3692,9 @@
         "Map 1 0b10 0x5b 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2400]",
+        "ldr x0, [x28, #2528]",
         "ld1b {z2.b}, p7/z, [x0]",
-        "ldr x0, [x28, #2352]",
+        "ldr x0, [x28, #2480]",
         "ld1b {z3.b}, p7/z, [x0]",
         "fcvtzs z4.s, p7/m, z17.s",
         "fcmgt p0.s, p7/z, z3.s, z17.s",
@@ -4427,7 +4427,7 @@
         "Map 1 0b01 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.2d, v17.2d, v2.2d"
       ]
@@ -4438,7 +4438,7 @@
         "Map 1 0b01 0xd0 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2176]",
+        "ldr x0, [x28, #2304]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z18.d, z2.d",
         "fadd z16.d, z17.d, z2.d"
@@ -4450,7 +4450,7 @@
         "Map 1 0b11 0xd0 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v18.16b, v2.16b",
         "fadd v16.4s, v17.4s, v2.4s"
       ]
@@ -4461,7 +4461,7 @@
         "Map 1 0b11 0xd0 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2160]",
+        "ldr x0, [x28, #2288]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z18.d, z2.d",
         "fadd z16.s, z17.s, z2.s"
@@ -4587,7 +4587,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3056]",
+        "ldr q2, [x28, #3184]",
         "cmlt v3.16b, v16.16b, #0",
         "and v2.16b, v3.16b, v2.16b",
         "addp v2.16b, v2.16b, v2.16b",
@@ -4602,7 +4602,7 @@
         "Map 1 0b01 0xd7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2288]",
+        "ldr x0, [x28, #2416]",
         "ld1b {z2.b}, p7/z, [x0]",
         "mrs x0, nzcv",
         "mov z0.d, #0",
@@ -4979,8 +4979,8 @@
         "Map 1 0b01 0xe6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr d2, [x28, #3280]",
-        "ldr q3, [x28, #3232]",
+        "ldr d2, [x28, #3408]",
+        "ldr q3, [x28, #3360]",
         "fcvtzs z4.s, p6/m, z17.d",
         "uzp1 z4.s, z4.s, z4.s",
         "mov v4.8b, v4.8b",
@@ -4996,8 +4996,8 @@
         "Map 1 0b01 0xe6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3280]",
-        "ldr x0, [x28, #2376]",
+        "ldr q2, [x28, #3408]",
+        "ldr x0, [x28, #2504]",
         "ld1b {z3.b}, p7/z, [x0]",
         "fcvtzs z4.s, p7/m, z17.d",
         "uzp1 z4.s, z4.s, z4.s",
@@ -5040,8 +5040,8 @@
       ],
       "ExpectedArm64ASM": [
         "frinti v2.2d, v17.2d",
-        "ldr d3, [x28, #3280]",
-        "ldr q4, [x28, #3232]",
+        "ldr d3, [x28, #3408]",
+        "ldr q4, [x28, #3360]",
         "fcvtzs z5.s, p6/m, z2.d",
         "uzp1 z5.s, z5.s, z5.s",
         "mov v5.8b, v5.8b",
@@ -5058,8 +5058,8 @@
       ],
       "ExpectedArm64ASM": [
         "frinti z2.d, p7/m, z17.d",
-        "ldr q3, [x28, #3280]",
-        "ldr x0, [x28, #2376]",
+        "ldr q3, [x28, #3408]",
+        "ldr x0, [x28, #2504]",
         "ld1b {z4.b}, p7/z, [x0]",
         "fcvtzs z5.s, p7/m, z2.d",
         "uzp1 z5.s, z5.s, z5.s",

unittests/InstructionCountCI/VEX_map1_FRINTTS.json

@@ -112,9 +112,9 @@
       ],
       "ExpectedArm64ASM": [
         "frinti z2.s, p7/m, z17.s",
-        "ldr x0, [x28, #2400]",
+        "ldr x0, [x28, #2528]",
         "ld1b {z3.b}, p7/z, [x0]",
-        "ldr x0, [x28, #2352]",
+        "ldr x0, [x28, #2480]",
         "ld1b {z4.b}, p7/z, [x0]",
         "fcvtzs z5.s, p7/m, z2.s",
         "fcmgt p0.s, p7/z, z4.s, z2.s",
@@ -142,9 +142,9 @@
         "Map 1 0b10 0x5b 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2400]",
+        "ldr x0, [x28, #2528]",
         "ld1b {z2.b}, p7/z, [x0]",
-        "ldr x0, [x28, #2352]",
+        "ldr x0, [x28, #2480]",
         "ld1b {z3.b}, p7/z, [x0]",
         "fcvtzs z4.s, p7/m, z17.s",
         "fcmgt p0.s, p7/z, z3.s, z17.s",
@@ -173,8 +173,8 @@
         "Map 1 0b01 0xe6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #3280]",
-        "ldr x0, [x28, #2376]",
+        "ldr q2, [x28, #3408]",
+        "ldr x0, [x28, #2504]",
         "ld1b {z3.b}, p7/z, [x0]",
         "fcvtzs z4.s, p7/m, z17.d",
         "uzp1 z4.s, z4.s, z4.s",
@@ -208,8 +208,8 @@
       ],
       "ExpectedArm64ASM": [
         "frinti z2.d, p7/m, z17.d",
-        "ldr q3, [x28, #3280]",
-        "ldr x0, [x28, #2376]",
+        "ldr q3, [x28, #3408]",
+        "ldr x0, [x28, #2504]",
         "ld1b {z4.b}, p7/z, [x0]",
         "fcvtzs z5.s, p7/m, z2.d",
         "uzp1 z5.s, z5.s, z5.s",

unittests/InstructionCountCI/VEX_map2.json

@@ -1603,7 +1603,7 @@
         "Map 2 0b01 0x41 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2768]",
+        "ldr q2, [x28, #2896]",
         "zip1 v3.8h, v2.8h, v17.8h",
         "zip2 v2.8h, v2.8h, v17.8h",
         "umin v2.4s, v3.4s, v2.4s",
@@ -3657,7 +3657,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.4s, v16.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -3669,7 +3669,7 @@
         "Map 2 0b01 0x96 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2160]",
+        "ldr x0, [x28, #2288]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z17.d, z2.d",
         "mov z0.d, z2.d",
@@ -3683,7 +3683,7 @@
         "Map 2 0b01 0x96 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.2d, v16.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -3695,7 +3695,7 @@
         "Map 2 0b01 0x96 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2176]",
+        "ldr x0, [x28, #2304]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z17.d, z2.d",
         "mov z0.d, z2.d",
@@ -3709,7 +3709,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2864]",
+        "ldr q2, [x28, #2992]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.4s, v16.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -3721,7 +3721,7 @@
         "Map 2 0b01 0x97 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2192]",
+        "ldr x0, [x28, #2320]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z17.d, z2.d",
         "mov z0.d, z2.d",
@@ -3735,7 +3735,7 @@
         "Map 2 0b01 0x97 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2896]",
+        "ldr q2, [x28, #3024]",
         "eor v2.16b, v17.16b, v2.16b",
         "fmla v2.2d, v16.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -3747,7 +3747,7 @@
         "Map 2 0b01 0x97 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2208]",
+        "ldr x0, [x28, #2336]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z17.d, z2.d",
         "mov z0.d, z2.d",
@@ -4609,7 +4609,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.4s, v17.4s, v16.4s",
         "mov v16.16b, v2.16b"
@@ -4621,7 +4621,7 @@
         "Map 2 0b01 0xa6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2160]",
+        "ldr x0, [x28, #2288]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z18.d, z2.d",
         "mov z0.d, z2.d",
@@ -4635,7 +4635,7 @@
         "Map 2 0b01 0xa6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.2d, v17.2d, v16.2d",
         "mov v16.16b, v2.16b"
@@ -4647,7 +4647,7 @@
         "Map 2 0b01 0xa6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2176]",
+        "ldr x0, [x28, #2304]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z18.d, z2.d",
         "mov z0.d, z2.d",
@@ -4661,7 +4661,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2864]",
+        "ldr q2, [x28, #2992]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.4s, v17.4s, v16.4s",
         "mov v16.16b, v2.16b"
@@ -4673,7 +4673,7 @@
         "Map 2 0b01 0xa7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2192]",
+        "ldr x0, [x28, #2320]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z18.d, z2.d",
         "mov z0.d, z2.d",
@@ -4687,7 +4687,7 @@
         "Map 2 0b01 0xa7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2896]",
+        "ldr q2, [x28, #3024]",
         "eor v2.16b, v18.16b, v2.16b",
         "fmla v2.2d, v17.2d, v16.2d",
         "mov v16.16b, v2.16b"
@@ -4699,7 +4699,7 @@
         "Map 2 0b01 0xa7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2208]",
+        "ldr x0, [x28, #2336]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z18.d, z2.d",
         "mov z0.d, z2.d",
@@ -4713,7 +4713,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2800]",
+        "ldr q2, [x28, #2928]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.4s, v17.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -4725,7 +4725,7 @@
         "Map 2 0b01 0xb6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2160]",
+        "ldr x0, [x28, #2288]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z16.d, z2.d",
         "mov z16.d, z2.d",
@@ -4738,7 +4738,7 @@
         "Map 2 0b01 0xb6 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2832]",
+        "ldr q2, [x28, #2960]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.2d, v17.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -4750,7 +4750,7 @@
         "Map 2 0b01 0xb6 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2176]",
+        "ldr x0, [x28, #2304]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z16.d, z2.d",
         "mov z16.d, z2.d",
@@ -4763,7 +4763,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2864]",
+        "ldr q2, [x28, #2992]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.4s, v17.4s, v18.4s",
         "mov v16.16b, v2.16b"
@@ -4775,7 +4775,7 @@
         "Map 2 0b01 0xb7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2192]",
+        "ldr x0, [x28, #2320]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z16.d, z2.d",
         "mov z16.d, z2.d",
@@ -4788,7 +4788,7 @@
         "Map 2 0b01 0xb7 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2896]",
+        "ldr q2, [x28, #3024]",
         "eor v2.16b, v16.16b, v2.16b",
         "fmla v2.2d, v17.2d, v18.2d",
         "mov v16.16b, v2.16b"
@@ -4800,7 +4800,7 @@
         "Map 2 0b01 0xb7 256-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr x0, [x28, #2208]",
+        "ldr x0, [x28, #2336]",
         "ld1b {z2.b}, p7/z, [x0]",
         "eor z2.d, z16.d, z2.d",
         "mov z16.d, z2.d",

unittests/InstructionCountCI/VEX_map3.json

@@ -5372,7 +5372,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2944]",
+        "ldr q2, [x28, #3072]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",
@@ -5385,7 +5385,7 @@
         "Map 3 0b01 0xdf 128-bit"
       ],
       "ExpectedArm64ASM": [
-        "ldr q2, [x28, #2944]",
+        "ldr q2, [x28, #3072]",
         "movi v3.2d, #0x0",
         "mov v16.16b, v17.16b",
         "aese v16.16b, v3.16b",

unittests/InstructionCountCI/X87ldst-SVE.json

@@ -21,11 +21,11 @@
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
         "st1h {z2.h}, p2, [x4]",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "mov w22, #0x1",
         "lsl w22, w22, w20",
         "bic w21, w21, w22",
-        "strb w21, [x28, #1298]",
+        "strb w21, [x28, #1426]",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]"
@@ -43,11 +43,11 @@
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
         "st1h {z2.h}, p2, [x4]",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "mov w22, #0x1",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
-        "strb w21, [x28, #1298]",
+        "strb w21, [x28, #1426]",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]",
@@ -55,10 +55,10 @@
         "ldr q2, [x0, #1040]",
         "add x21, x4, #0xa (10)",
         "st1h {z2.h}, p2, [x21]",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "lsl w22, w22, w20",
         "bic w21, w21, w22",
-        "strb w21, [x28, #1298]",
+        "strb w21, [x28, #1426]",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]"
@@ -82,11 +82,11 @@
         "add x0, x28, x20, lsl #4",
         "ldr q2, [x0, #1040]",
         "st1h {z2.h}, p2, [x4]",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "mov w22, #0x1",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
-        "strb w21, [x28, #1298]",
+        "strb w21, [x28, #1426]",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]",
@@ -94,10 +94,10 @@
         "ldr q2, [x0, #1040]",
         "add x21, x4, #0xa (10)",
         "st1h {z2.h}, p2, [x21]",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
-        "strb w21, [x28, #1298]",
+        "strb w21, [x28, #1426]",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]",
@@ -105,10 +105,10 @@
         "ldr q2, [x0, #1040]",
         "add x21, x4, #0x14 (20)",
         "st1h {z2.h}, p2, [x21]",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
-        "strb w21, [x28, #1298]",
+        "strb w21, [x28, #1426]",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]",
@@ -116,10 +116,10 @@
         "ldr q2, [x0, #1040]",
         "add x21, x4, #0x1e (30)",
         "st1h {z2.h}, p2, [x21]",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
-        "strb w21, [x28, #1298]",
+        "strb w21, [x28, #1426]",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]",
@@ -127,10 +127,10 @@
         "ldr q2, [x0, #1040]",
         "add x21, x4, #0x28 (40)",
         "st1h {z2.h}, p2, [x21]",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
-        "strb w21, [x28, #1298]",
+        "strb w21, [x28, #1426]",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]",
@@ -138,10 +138,10 @@
         "ldr q2, [x0, #1040]",
         "add x21, x4, #0x32 (50)",
         "st1h {z2.h}, p2, [x21]",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
-        "strb w21, [x28, #1298]",
+        "strb w21, [x28, #1426]",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]",
@@ -149,10 +149,10 @@
         "ldr q2, [x0, #1040]",
         "add x21, x4, #0x3c (60)",
         "st1h {z2.h}, p2, [x21]",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "lsl w23, w22, w20",
         "bic w21, w21, w23",
-        "strb w21, [x28, #1298]",
+        "strb w21, [x28, #1426]",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]",
@@ -160,10 +160,10 @@
         "ldr q2, [x0, #1040]",
         "add x21, x4, #0x46 (70)",
         "st1h {z2.h}, p2, [x21]",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "lsl w22, w22, w20",
         "bic w21, w21, w22",
-        "strb w21, [x28, #1298]",
+        "strb w21, [x28, #1426]",
         "add w20, w20, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]"
@@ -181,10 +181,10 @@
         "strb w20, [x28, #1019]",
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
-        "ldrb w22, [x28, #1298]",
+        "ldrb w22, [x28, #1426]",
         "lsl w20, w21, w20",
         "orr w20, w22, w20",
-        "strb w20, [x28, #1298]"
+        "strb w20, [x28, #1426]"
       ]
     },
     "2-load 80bit": {
@@ -210,11 +210,11 @@
         "str q2, [x0, #1040]",
         "mov w21, #0x8",
         "sub w20, w21, w20",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "mov w22, #0x303",
         "lsr w20, w22, w20",
         "orr w20, w21, w20",
-        "strb w20, [x28, #1298]"
+        "strb w20, [x28, #1426]"
       ]
     },
     "8-load 80bit": {
@@ -281,7 +281,7 @@
         "add x0, x28, x20, lsl #4",
         "str q2, [x0, #1040]",
         "mov w20, #0xff",
-        "strb w20, [x28, #1298]"
+        "strb w20, [x28, #1426]"
       ]
     }
   }

unittests/InstructionCountCI/x87_32Bit.json

@@ -30,11 +30,11 @@
         "ldrb w20, [x28, #1019]",
         "add w20, w20, #0x7 (7)",
         "and w20, w20, #0x7",
-        "ldrb w21, [x28, #1298]",
+        "ldrb w21, [x28, #1426]",
         "mov w22, #0x1",
         "lsl w20, w22, w20",
         "bic w20, w21, w20",
-        "strb w20, [x28, #1298]"
+        "strb w20, [x28, #1426]"
       ]
     }
   }

unittests/InstructionCountCI/x87_f64_32Bit.json

@@ -28,11 +28,11 @@
         "ldr d2, [x0, #1040]",
         "fcvt s2, d2",
         "str s2, [x20]",
-        "ldrb w20, [x28, #1298]",
+        "ldrb w20, [x28, #1426]",
         "mov w22, #0x1",
         "lsl w22, w22, w21",
         "bic w20, w20, w22",
-        "strb w20, [x28, #1298]",
+        "strb w20, [x28, #1426]",
         "add w20, w21, #0x1 (1)",
         "and w20, w20, #0x7",
         "strb w20, [x28, #1019]"