Merge pull request #4824 from bylaws/tf2

OpDispatcher: Force a recheck of TF after POPF

FEXCore/Source/Interface/Core/JIT/BranchOps.cpp

@@ -146,6 +146,15 @@ DEF_OP(ExitFunction) {
         } else {
           stp<ARMEmitter::IndexType::PRE>(ARMEmitter::XReg::zr, ARMEmitter::XReg::zr, REG_CALLRET_SP, -0x10);
         }
+      } else if (Op->Hint == IR::BranchHint::CheckTF) {
+        ARMEmitter::ForwardLabel TFUnset;
+        ldrb(TMP1, STATE_PTR(CpuStateFrame, State.flags[X86State::RFLAG_TF_RAW_LOC]));
+        cbz(ARMEmitter::Size::i32Bit, TMP1, &TFUnset);
+        LoadConstant(ARMEmitter::Size::i64Bit, TMP1, NewRIP);
+        str(TMP1, STATE, offsetof(FEXCore::Core::CpuStateFrame, State.rip));
+        ldr(TMP2, STATE, offsetof(FEXCore::Core::CpuStateFrame, Pointers.Common.DispatcherLoopTop));
+        blr(TMP2);
+        Bind(&TFUnset);
       }
 
       EmitLinkedBranch(NewRIP, Op->Hint == IR::BranchHint::Call);

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -3604,6 +3604,10 @@ void OpDispatchBuilder::POPFOp(OpcodeArgs) {
   Src = _Or(OpSize::i64Bit, Src, Constant(0x202));
 
   SetPackedRFLAG(false, Src);
+
+  auto NewRIP = GetRelocatedPC(Op);
+  ExitFunction(NewRIP, BranchHint::CheckTF);
+  BlockSetRIP = true;
 }
 
 void OpDispatchBuilder::NEGOp(OpcodeArgs) {

FEXCore/Source/Interface/IR/IR.h

@@ -621,11 +621,7 @@ enum class ShiftType : uint8_t {
   ROR,
 };
 
-enum class BranchHint : uint8_t {
-  None = 0,
-  Call,
-  Return,
-};
+enum class BranchHint : uint8_t { None = 0, Call, Return, CheckTF };
 
 
 // Converts a size stored as an integer in to an OpSize enum.

unittests/InstructionCountCI/FlagM/Primary.json

@@ -1752,7 +1752,7 @@
       ]
     },
     "popf": {
-      "ExpectedInstructionCount": 39,
+      "ExpectedInstructionCount": 40,
       "Comment": "0x9d",
       "ExpectedArm64ASM": [
         "ldr x20, [x8], #8",
@@ -1793,6 +1793,7 @@
         "strb w21, [x28, #996]",
         "ubfx w21, w27, #21, #1",
         "strb w21, [x28, #997]",
+        "mov w21, #0x10001",
         "strb w20, [x28, #986]"
       ]
     },

unittests/InstructionCountCI/Primary.json

@@ -2733,7 +2733,7 @@
       ]
     },
     "popf": {
-      "ExpectedInstructionCount": 43,
+      "ExpectedInstructionCount": 44,
       "Comment": "0x9d",
       "ExpectedArm64ASM": [
         "ldr x20, [x8], #8",
@@ -2777,6 +2777,7 @@
         "strb w21, [x28, #996]",
         "ubfx w21, w27, #21, #1",
         "strb w21, [x28, #997]",
+        "mov w21, #0x10001",
         "msr nzcv, x22",
         "strb w20, [x28, #986]"
       ]