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https://github.com/FEX-Emu/FEX.git
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Merge pull request #2396 from lioncash/narrow
ARMEmitter: Finish off SVE Misc category
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+254
-14
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+159
-8
@@ -1910,16 +1910,60 @@ public:
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//
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// SVE Misc
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// SVE2 bitwise shift left long
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// XXX:
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void sshllb(SubRegSize size, ZRegister zd, ZRegister zn, uint32_t shift) {
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SVE2BitwiseShiftLeftLong(size, 0b00, zd, zn, shift);
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}
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void sshllt(SubRegSize size, ZRegister zd, ZRegister zn, uint32_t shift) {
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SVE2BitwiseShiftLeftLong(size, 0b01, zd, zn, shift);
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}
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void ushllb(SubRegSize size, ZRegister zd, ZRegister zn, uint32_t shift) {
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SVE2BitwiseShiftLeftLong(size, 0b10, zd, zn, shift);
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}
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void ushllt(SubRegSize size, ZRegister zd, ZRegister zn, uint32_t shift) {
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SVE2BitwiseShiftLeftLong(size, 0b11, zd, zn, shift);
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}
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// SVE2 integer add/subtract interleaved long
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// XXX:
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void saddlbt(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2IntegerAddSubInterleavedLong(size, 0b00, zd, zn, zm);
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}
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void ssublbt(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2IntegerAddSubInterleavedLong(size, 0b10, zd, zn, zm);
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}
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void ssubltb(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2IntegerAddSubInterleavedLong(size, 0b11, zd, zn, zm);
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}
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// SVE2 bitwise exclusive-or interleaved
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// XXX:
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void eorbt(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2BitwiseXorInterleaved(size, 0b0, zd, zn, zm);
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}
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void eortb(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2BitwiseXorInterleaved(size, 0b1, zd, zn, zm);
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}
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// SVE integer matrix multiply accumulate
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// XXX:
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void smmla(ZRegister zda, ZRegister zn, ZRegister zm) {
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SVEIntegerMatrixMulAccumulate(0b00, zda, zn, zm);
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}
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void usmmla(ZRegister zda, ZRegister zn, ZRegister zm) {
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SVEIntegerMatrixMulAccumulate(0b10, zda, zn, zm);
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}
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void ummla(ZRegister zda, ZRegister zn, ZRegister zm) {
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SVEIntegerMatrixMulAccumulate(0b11, zda, zn, zm);
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}
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// SVE2 bitwise permute
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// XXX:
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//
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void bext(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2BitwisePermute(size, 0b00, zd, zn, zm);
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}
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void bdep(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2BitwisePermute(size, 0b01, zd, zn, zm);
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}
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void bgrp(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2BitwisePermute(size, 0b10, zd, zn, zm);
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}
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// SVE2 Accumulate
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// SVE2 complex integer add
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// XXX:
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@@ -2075,9 +2119,33 @@ public:
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Instr |= zd.Idx();
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dc32(Instr);
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}
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// SVE2 integer add/subtract narrow high part
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// XXX:
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//
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void addhnb(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2IntegerAddSubNarrowHighPart(size, 0b000, zd, zn, zm);
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}
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void addhnt(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2IntegerAddSubNarrowHighPart(size, 0b001, zd, zn, zm);
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}
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void raddhnb(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2IntegerAddSubNarrowHighPart(size, 0b010, zd, zn, zm);
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}
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void raddhnt(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2IntegerAddSubNarrowHighPart(size, 0b011, zd, zn, zm);
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}
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void subhnb(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2IntegerAddSubNarrowHighPart(size, 0b100, zd, zn, zm);
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}
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void subhnt(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2IntegerAddSubNarrowHighPart(size, 0b101, zd, zn, zm);
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}
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void rsubhnb(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2IntegerAddSubNarrowHighPart(size, 0b110, zd, zn, zm);
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}
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void rsubhnt(SubRegSize size, ZRegister zd, ZRegister zn, ZRegister zm) {
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SVE2IntegerAddSubNarrowHighPart(size, 0b111, zd, zn, zm);
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}
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// SVE2 Crypto Extensions
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// SVE2 crypto unary operations
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// XXX:
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@@ -3498,6 +3566,89 @@ private:
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dc32(Instr);
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}
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void SVE2IntegerAddSubNarrowHighPart(SubRegSize size, uint32_t opc, ZRegister zd, ZRegister zn, ZRegister zm) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i64Bit && size != SubRegSize::i128Bit,
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"Can't use 64-bit or 128-bit element size");
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uint32_t Instr = 0b0100'0101'0010'0000'0110'0000'0000'0000;
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Instr |= (FEXCore::ToUnderlying(size) + 1) << 22;
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Instr |= zm.Idx() << 16;
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Instr |= opc << 10;
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Instr |= zn.Idx() << 5;
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Instr |= zd.Idx();
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dc32(Instr);
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}
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void SVE2BitwisePermute(SubRegSize size, uint32_t opc, ZRegister zd, ZRegister zn, ZRegister zm) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i128Bit, "Can't use 128-bit element size");
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uint32_t Instr = 0b0100'0101'0000'0000'1011'0000'0000'0000;
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Instr |= FEXCore::ToUnderlying(size) << 22;
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Instr |= zm.Idx() << 16;
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Instr |= opc << 10;
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Instr |= zn.Idx() << 5;
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Instr |= zd.Idx();
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dc32(Instr);
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}
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void SVE2BitwiseXorInterleaved(SubRegSize size, uint32_t opc, ZRegister zd, ZRegister zn, ZRegister zm) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i128Bit, "Can't use 128-bit element size");
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uint32_t Instr = 0b0100'0101'0000'0000'1001'0000'0000'0000;
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Instr |= FEXCore::ToUnderlying(size) << 22;
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Instr |= zm.Idx() << 16;
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Instr |= opc << 10;
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Instr |= zn.Idx() << 5;
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Instr |= zd.Idx();
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dc32(Instr);
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}
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void SVEIntegerMatrixMulAccumulate(uint32_t opc, ZRegister zda, ZRegister zn, ZRegister zm) {
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uint32_t Instr = 0b0100'0101'0000'0000'1001'1000'0000'0000;
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Instr |= opc << 22;
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Instr |= zm.Idx() << 16;
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Instr |= zn.Idx() << 5;
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Instr |= zda.Idx();
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dc32(Instr);
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}
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void SVE2IntegerAddSubInterleavedLong(SubRegSize size, uint32_t opc, ZRegister zd, ZRegister zn, ZRegister zm) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i128Bit,
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"Can't use 8-bit or 128-bit element size");
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uint32_t Instr = 0b0100'0101'0000'0000'1000'0000'0000'0000;
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Instr |= FEXCore::ToUnderlying(size) << 22;
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Instr |= zm.Idx() << 16;
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Instr |= opc << 10;
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Instr |= zn.Idx() << 5;
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Instr |= zd.Idx();
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dc32(Instr);
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}
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void SVE2BitwiseShiftLeftLong(SubRegSize size, uint32_t opc, ZRegister zd, ZRegister zn, uint32_t shift) {
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LOGMAN_THROW_A_FMT(size != SubRegSize::i8Bit && size != SubRegSize::i128Bit,
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"Can't use 8-bit or 128-bit element size");
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const auto Underlying = FEXCore::ToUnderlying(size);
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const auto ElementSize = SubRegSizeInBits(static_cast<SubRegSize>(Underlying - 1));
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LOGMAN_THROW_A_FMT(shift >= 0 && shift < ElementSize,
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"Shift must be within 0-{}", ElementSize - 1);
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uint32_t Instr = 0b0100'0101'0000'0000'1010'0000'0000'0000;
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Instr |= shift << 16;
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Instr |= opc << 10;
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Instr |= zn.Idx() << 5;
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Instr |= zd.Idx();
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if (size == SubRegSize::i64Bit) {
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Instr |= 1U << 22;
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} else {
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Instr |= (1U << 19) << (Underlying - 1);
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}
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dc32(Instr);
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}
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// SVE floating-point round to integral value
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void frintX(uint32_t opc, FEXCore::ARMEmitter::SubRegSize size, FEXCore::ARMEmitter::ZRegister zd, FEXCore::ARMEmitter::PRegister pg, FEXCore::ARMEmitter::ZRegister zn) {
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// opc = round mode
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+95
-6
@@ -1783,19 +1783,78 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 integer multiply long") {
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TEST_SINGLE(umullt(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "umullt z30.d, z29.s, z28.s");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 bitwise shift left long") {
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// TODO: Implement in emitter.
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TEST_SINGLE(sshllb(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, 0), "sshllb z30.h, z29.b, #0");
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TEST_SINGLE(sshllb(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, 7), "sshllb z30.h, z29.b, #7");
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TEST_SINGLE(sshllb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, 0), "sshllb z30.s, z29.h, #0");
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TEST_SINGLE(sshllb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, 15), "sshllb z30.s, z29.h, #15");
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TEST_SINGLE(sshllb(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, 0), "sshllb z30.d, z29.s, #0");
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TEST_SINGLE(sshllb(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, 31), "sshllb z30.d, z29.s, #31");
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TEST_SINGLE(sshllt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, 0), "sshllt z30.h, z29.b, #0");
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TEST_SINGLE(sshllt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, 7), "sshllt z30.h, z29.b, #7");
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TEST_SINGLE(sshllt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, 0), "sshllt z30.s, z29.h, #0");
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TEST_SINGLE(sshllt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, 15), "sshllt z30.s, z29.h, #15");
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TEST_SINGLE(sshllt(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, 0), "sshllt z30.d, z29.s, #0");
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TEST_SINGLE(sshllt(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, 31), "sshllt z30.d, z29.s, #31");
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TEST_SINGLE(ushllb(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, 0), "ushllb z30.h, z29.b, #0");
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TEST_SINGLE(ushllb(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, 7), "ushllb z30.h, z29.b, #7");
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TEST_SINGLE(ushllb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, 0), "ushllb z30.s, z29.h, #0");
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TEST_SINGLE(ushllb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, 15), "ushllb z30.s, z29.h, #15");
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TEST_SINGLE(ushllb(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, 0), "ushllb z30.d, z29.s, #0");
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TEST_SINGLE(ushllb(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, 31), "ushllb z30.d, z29.s, #31");
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TEST_SINGLE(ushllt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, 0), "ushllt z30.h, z29.b, #0");
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TEST_SINGLE(ushllt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, 7), "ushllt z30.h, z29.b, #7");
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TEST_SINGLE(ushllt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, 0), "ushllt z30.s, z29.h, #0");
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TEST_SINGLE(ushllt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, 15), "ushllt z30.s, z29.h, #15");
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TEST_SINGLE(ushllt(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, 0), "ushllt z30.d, z29.s, #0");
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TEST_SINGLE(ushllt(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, 31), "ushllt z30.d, z29.s, #31");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 integer add/subtract interleaved long") {
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// TODO: Implement in emitter.
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TEST_SINGLE(saddlbt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "saddlbt z30.h, z29.b, z28.b");
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TEST_SINGLE(saddlbt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "saddlbt z30.s, z29.h, z28.h");
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TEST_SINGLE(saddlbt(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "saddlbt z30.d, z29.s, z28.s");
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TEST_SINGLE(ssublbt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "ssublbt z30.h, z29.b, z28.b");
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TEST_SINGLE(ssublbt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "ssublbt z30.s, z29.h, z28.h");
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TEST_SINGLE(ssublbt(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "ssublbt z30.d, z29.s, z28.s");
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TEST_SINGLE(ssubltb(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "ssubltb z30.h, z29.b, z28.b");
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TEST_SINGLE(ssubltb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "ssubltb z30.s, z29.h, z28.h");
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TEST_SINGLE(ssubltb(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "ssubltb z30.d, z29.s, z28.s");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 bitwise exclusive-or interleaved") {
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// TODO: Implement in emitter.
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TEST_SINGLE(eorbt(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "eorbt z30.b, z29.b, z28.b");
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TEST_SINGLE(eorbt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "eorbt z30.h, z29.h, z28.h");
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TEST_SINGLE(eorbt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "eorbt z30.s, z29.s, z28.s");
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TEST_SINGLE(eorbt(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "eorbt z30.d, z29.d, z28.d");
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TEST_SINGLE(eortb(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "eortb z30.b, z29.b, z28.b");
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TEST_SINGLE(eortb(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "eortb z30.h, z29.h, z28.h");
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TEST_SINGLE(eortb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "eortb z30.s, z29.s, z28.s");
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TEST_SINGLE(eortb(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "eortb z30.d, z29.d, z28.d");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE integer matrix multiply accumulate") {
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// TODO: Implement in emitter.
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TEST_SINGLE(smmla(ZReg::z30, ZReg::z29, ZReg::z28), "smmla z30.s, z29.b, z28.b");
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TEST_SINGLE(usmmla(ZReg::z30, ZReg::z29, ZReg::z28), "usmmla z30.s, z29.b, z28.b");
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TEST_SINGLE(ummla(ZReg::z30, ZReg::z29, ZReg::z28), "ummla z30.s, z29.b, z28.b");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 bitwise permute") {
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// TODO: Implement in emitter.
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TEST_SINGLE(bext(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bext z30.b, z29.b, z28.b");
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TEST_SINGLE(bext(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bext z30.h, z29.h, z28.h");
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TEST_SINGLE(bext(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bext z30.s, z29.s, z28.s");
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TEST_SINGLE(bext(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bext z30.d, z29.d, z28.d");
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TEST_SINGLE(bdep(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bdep z30.b, z29.b, z28.b");
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TEST_SINGLE(bdep(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bdep z30.h, z29.h, z28.h");
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TEST_SINGLE(bdep(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bdep z30.s, z29.s, z28.s");
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TEST_SINGLE(bdep(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bdep z30.d, z29.d, z28.d");
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TEST_SINGLE(bgrp(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bgrp z30.b, z29.b, z28.b");
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TEST_SINGLE(bgrp(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bgrp z30.h, z29.h, z28.h");
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TEST_SINGLE(bgrp(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bgrp z30.s, z29.s, z28.s");
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TEST_SINGLE(bgrp(SubRegSize::i64Bit, ZReg::z30, ZReg::z29, ZReg::z28), "bgrp z30.d, z29.d, z28.d");
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}
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TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 complex integer add") {
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// TODO: Implement in emitter.
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@@ -1960,7 +2019,37 @@ TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 bitwise shift right narro
|
||||
TEST_SINGLE(uqrshrnt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, 32), "uqrshrnt z30.s, z29.d, #32");
|
||||
}
|
||||
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 integer add/subtract narrow high part") {
|
||||
// TODO: Implement in emitter.
|
||||
TEST_SINGLE(addhnb(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "addhnb z30.b, z29.h, z28.h");
|
||||
TEST_SINGLE(addhnb(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "addhnb z30.h, z29.s, z28.s");
|
||||
TEST_SINGLE(addhnb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "addhnb z30.s, z29.d, z28.d");
|
||||
|
||||
TEST_SINGLE(addhnt(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "addhnt z30.b, z29.h, z28.h");
|
||||
TEST_SINGLE(addhnt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "addhnt z30.h, z29.s, z28.s");
|
||||
TEST_SINGLE(addhnt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "addhnt z30.s, z29.d, z28.d");
|
||||
|
||||
TEST_SINGLE(raddhnb(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "raddhnb z30.b, z29.h, z28.h");
|
||||
TEST_SINGLE(raddhnb(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "raddhnb z30.h, z29.s, z28.s");
|
||||
TEST_SINGLE(raddhnb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "raddhnb z30.s, z29.d, z28.d");
|
||||
|
||||
TEST_SINGLE(raddhnt(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "raddhnt z30.b, z29.h, z28.h");
|
||||
TEST_SINGLE(raddhnt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "raddhnt z30.h, z29.s, z28.s");
|
||||
TEST_SINGLE(raddhnt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "raddhnt z30.s, z29.d, z28.d");
|
||||
|
||||
TEST_SINGLE(subhnb(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "subhnb z30.b, z29.h, z28.h");
|
||||
TEST_SINGLE(subhnb(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "subhnb z30.h, z29.s, z28.s");
|
||||
TEST_SINGLE(subhnb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "subhnb z30.s, z29.d, z28.d");
|
||||
|
||||
TEST_SINGLE(subhnt(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "subhnt z30.b, z29.h, z28.h");
|
||||
TEST_SINGLE(subhnt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "subhnt z30.h, z29.s, z28.s");
|
||||
TEST_SINGLE(subhnt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "subhnt z30.s, z29.d, z28.d");
|
||||
|
||||
TEST_SINGLE(rsubhnb(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "rsubhnb z30.b, z29.h, z28.h");
|
||||
TEST_SINGLE(rsubhnb(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "rsubhnb z30.h, z29.s, z28.s");
|
||||
TEST_SINGLE(rsubhnb(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "rsubhnb z30.s, z29.d, z28.d");
|
||||
|
||||
TEST_SINGLE(rsubhnt(SubRegSize::i8Bit, ZReg::z30, ZReg::z29, ZReg::z28), "rsubhnt z30.b, z29.h, z28.h");
|
||||
TEST_SINGLE(rsubhnt(SubRegSize::i16Bit, ZReg::z30, ZReg::z29, ZReg::z28), "rsubhnt z30.h, z29.s, z28.s");
|
||||
TEST_SINGLE(rsubhnt(SubRegSize::i32Bit, ZReg::z30, ZReg::z29, ZReg::z28), "rsubhnt z30.s, z29.d, z28.d");
|
||||
}
|
||||
TEST_CASE_METHOD(TestDisassembler, "Emitter: SVE: SVE2 Histogram Computation") {
|
||||
TEST_SINGLE(histcnt(SubRegSize::i32Bit, ZReg::z30, PReg::p6.Merging(), ZReg::z29, ZReg::z28), "histcnt z30.s, p6/z, z29.s, z28.s");
|
||||
|
||||
Reference in new issue
Block a user