PassManager: Simplify pass initialization

We don't conditionally add any passes, so we can simplify the interface
so that we just add all existing passes at once. Makes the core
initialization process a little more straightforward.

FEXCore/Source/Interface/Core/Core.cpp

@@ -395,7 +395,7 @@ void ContextImpl::InitializeCompiler(FEXCore::Core::InternalThreadState* Thread)
   Thread->OpDispatcher->SetMultiblock(Config.Multiblock);
   Thread->LookupCache = fextl::make_unique<FEXCore::LookupCache>(this);
   Thread->FrontendDecoder = fextl::make_unique<FEXCore::Frontend::Decoder>(Thread);
-  Thread->PassManager = fextl::make_unique<FEXCore::IR::PassManager>();
+  Thread->PassManager = fextl::make_unique<FEXCore::IR::PassManager>(this);
 
   Thread->CurrentFrame->State.L1Pointer = Thread->LookupCache->GetL1Pointer();
   Thread->CurrentFrame->State.L1Mask = Thread->LookupCache->GetScaledL1PointerMask();
@@ -404,15 +404,13 @@ void ContextImpl::InitializeCompiler(FEXCore::Core::InternalThreadState* Thread)
 
   Dispatcher->InitThreadPointers(Thread);
 
-  Thread->PassManager->AddDefaultPasses(this);
-  Thread->PassManager->AddDefaultValidationPasses();
-
   Thread->PassManager->RegisterSyscallHandler(SyscallHandler);
 
   // Create CPU backend
-  Thread->PassManager->InsertRegisterAllocationPass(this);
   Thread->CPUBackend = FEXCore::CPU::CreateArm64JITCore(this, Thread);
 
+  // We finalize *after* the CPU backend is initialized, as the CPU backend will
+  // provide necessary register information to the register allocation pass.
   Thread->PassManager->Finalize();
 }
 

FEXCore/Source/Interface/IR/PassManager.cpp

@@ -66,25 +66,48 @@ void PassManager::Finalize() {
   }
 }
 
-void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl* ctx) {
+void PassManager::AddDefaultPasses(Context::ContextImpl* ctx) {
   FEX_CONFIG_OPT(DisablePasses, O0);
 
+  // We only specifically disable optimization passes if desired, as IR output should
+  // still be well-formed regardless of the modifications made to it.
   if (!DisablePasses()) {
     InsertPass(CreateX87StackOptimizationPass(ctx->HostFeatures, ctx->Config.Is64BitMode ? IR::OpSize::i64Bit : IR::OpSize::i32Bit));
     InsertPass(CreateDeadFlagCalculationEliminination());
   }
-}
 
-void PassManager::AddDefaultValidationPasses() {
+  InsertPass(IR::CreateRegisterAllocationPass(&ctx->CPUID), "RA");
+
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
   InsertValidationPass(Validation::CreateIRValidation(), "IRValidation");
 #endif
 }
 
-void PassManager::InsertRegisterAllocationPass(FEXCore::Context::ContextImpl* ctx) {
-  InsertPass(IR::CreateRegisterAllocationPass(&ctx->CPUID), "RA");
+Pass* PassManager::InsertPass(fextl::unique_ptr<Pass> Pass, fextl::string Name) {
+  auto PassPtr = InsertAt(Passes.end(), std::move(Pass))->get();
+
+  if (!Name.empty()) {
+    NameToPassMaping[Name] = PassPtr;
+  }
+  return PassPtr;
 }
 
+PassManager::PassArrayType::iterator PassManager::InsertAt(PassArrayType::iterator pos, fextl::unique_ptr<Pass> Pass) {
+  Pass->RegisterPassManager(this);
+  return Passes.insert(pos, std::move(Pass));
+}
+
+#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
+void PassManager::InsertValidationPass(fextl::unique_ptr<Pass> Pass, fextl::string Name) {
+  Pass->RegisterPassManager(this);
+  auto PassPtr = ValidationPasses.emplace_back(std::move(Pass)).get();
+
+  if (!Name.empty()) {
+    NameToPassMaping[Name] = PassPtr;
+  }
+}
+#endif
+
 void PassManager::Run(IREmitter* IREmit) {
   FEXCORE_PROFILE_SCOPED("PassManager::Run");
 

FEXCore/Source/Interface/IR/PassManager.h

@@ -44,21 +44,14 @@ protected:
 
 class PassManager final {
 public:
-  void AddDefaultPasses(FEXCore::Context::ContextImpl* ctx);
-  void AddDefaultValidationPasses();
-  Pass* InsertPass(fextl::unique_ptr<Pass> Pass, fextl::string Name = "") {
-    auto PassPtr = InsertAt(Passes.end(), std::move(Pass))->get();
-
-    if (!Name.empty()) {
-      NameToPassMaping[Name] = PassPtr;
-    }
-    return PassPtr;
+  explicit PassManager(Context::ContextImpl* CTX) {
+    AddDefaultPasses(CTX);
   }
 
-  void InsertRegisterAllocationPass(FEXCore::Context::ContextImpl* ctx);
-
   void Run(IREmitter* IREmit);
 
+  Pass* InsertPass(fextl::unique_ptr<Pass> Pass, fextl::string Name = "");
+
   bool HasPass(fextl::string Name) const {
     return NameToPassMaping.contains(Name);
   }
@@ -82,24 +75,17 @@ protected:
   FEXCore::HLE::SyscallHandler* SyscallHandler {};
 
 private:
+  void AddDefaultPasses(Context::ContextImpl* ctx);
+
   using PassArrayType = fextl::vector<fextl::unique_ptr<Pass>>;
-  PassArrayType::iterator InsertAt(PassArrayType::iterator pos, fextl::unique_ptr<Pass> Pass) {
-    Pass->RegisterPassManager(this);
-    return Passes.insert(pos, std::move(Pass));
-  }
+  PassArrayType::iterator InsertAt(PassArrayType::iterator pos, fextl::unique_ptr<Pass> Pass);
+
   PassArrayType Passes;
   fextl::unordered_map<fextl::string, Pass*> NameToPassMaping;
 
 #if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
   fextl::vector<fextl::unique_ptr<Pass>> ValidationPasses;
-  void InsertValidationPass(fextl::unique_ptr<Pass> Pass, fextl::string Name = "") {
-    Pass->RegisterPassManager(this);
-    auto PassPtr = ValidationPasses.emplace_back(std::move(Pass)).get();
-
-    if (!Name.empty()) {
-      NameToPassMaping[Name] = PassPtr;
-    }
-  }
+  void InsertValidationPass(fextl::unique_ptr<Pass> Pass, fextl::string Name = "");
 #endif
 
   FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);