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InstCountCI: Update

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Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2025-06-02 14:27:02 -04:00
1 parent d966ae145e
commit 27854aa091
12 files changed
+250 -358
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unittests/InstructionCountCI/Atomics.json
+26 -46
View File
@@ -91,7 +91,7 @@
"cinc w20, w7, lo",
"ldaddalb w20, w20, [x4]",
"eor x27, x20, x7",
"uxtb w21, w7",
"uxtb x21, w7",
"cinc w22, w21, lo",
"add w23, w20, w22",
"uxtb w26, w23",
@@ -115,7 +115,7 @@
"cinc w20, w7, lo",
"ldaddalh w20, w20, [x4]",
"eor x27, x20, x7",
"uxth w21, w7",
"uxth x21, w7",
"cinc w22, w21, lo",
"add w23, w20, w22",
"uxth w26, w23",
@@ -157,7 +157,7 @@
"ldaddalb w1, w20, [x4]",
"eor x27, x20, x7",
"uxtb w20, w20",
"uxtb w21, w7",
"uxtb x21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxtb w26, w23",
@@ -183,7 +183,7 @@
"ldaddalh w1, w20, [x4]",
"eor x27, x20, x7",
"uxth w20, w20",
"uxth w21, w7",
"uxth x21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxth w26, w23",
@@ -687,7 +687,7 @@
]
},
"lock adc byte [rax], 1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -701,16 +701,14 @@
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w27, #0x1",
"eor w22, w26, w27",
"bic w20, w22, w20",
"bic w20, w26, w27",
"ubfx x20, x20, #7, #1",
"bfi w21, w20, #28, #1",
"msr nzcv, x21"
]
},
"lock adc byte [rax], 0xFF": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -725,16 +723,14 @@
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"bic w20, w21, w20",
"bic w20, w21, w26",
"ubfx x20, x20, #7, #1",
"bfi w22, w20, #28, #1",
"msr nzcv, x22"
]
},
"lock adc word [rax], 0x100": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
@@ -748,16 +744,14 @@
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w27, #0x100",
"eor w22, w26, w27",
"bic w20, w22, w20",
"bic w20, w26, w27",
"ubfx x20, x20, #15, #1",
"bfi w21, w20, #28, #1",
"msr nzcv, x21"
]
},
"lock adc word [rax], 0xFFFF": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
@@ -772,9 +766,7 @@
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0xffff",
"eor w21, w26, w21",
"bic w20, w21, w20",
"bic w20, w21, w26",
"ubfx x20, x20, #15, #1",
"bfi w22, w20, #28, #1",
"msr nzcv, x22"
@@ -846,7 +838,7 @@
]
},
"lock adc word [rax], 1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -860,9 +852,7 @@
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w27, #0x1",
"eor w22, w26, w27",
"bic w20, w22, w20",
"bic w20, w26, w27",
"ubfx x20, x20, #15, #1",
"bfi w21, w20, #28, #1",
"msr nzcv, x21"
@@ -901,7 +891,7 @@
]
},
"lock sbb byte [rax], 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -917,16 +907,14 @@
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"ubfx x20, x20, #7, #1",
"bfi w22, w20, #28, #1",
"msr nzcv, x22"
]
},
"lock sbb byte [rax], 0xFF": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -943,16 +931,14 @@
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w26, w21",
"ubfx x20, x20, #7, #1",
"bfi w22, w20, #28, #1",
"msr nzcv, x22"
]
},
"lock sbb word [rax], 0x100": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
@@ -968,16 +954,14 @@
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0x100",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"ubfx x20, x20, #15, #1",
"bfi w22, w20, #28, #1",
"msr nzcv, x22"
]
},
"lock sbb word [rax], 0xFFFF": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
@@ -994,9 +978,7 @@
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0xffff",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w26, w21",
"ubfx x20, x20, #15, #1",
"bfi w22, w20, #28, #1",
"msr nzcv, x22"
@@ -1048,7 +1030,7 @@
]
},
"lock sbb word [rax], 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -1064,9 +1046,7 @@
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"ubfx x20, x20, #15, #1",
"bfi w22, w20, #28, #1",
"msr nzcv, x22"
@@ -1432,8 +1412,8 @@
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldeoral w20, w20, [x4]",
"mvn w20, w20",
"ldeoral w20, w21, [x4]",
"eor w20, w21, w20",
"subs w26, w20, #0x0 (0)"
]
},
unittests/InstructionCountCI/FEXOpt/MultiInst.json
+57 -65
View File
@@ -225,7 +225,7 @@
},
"positive rep movsb": {
"x86InstructionCount": 2,
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 43,
"Comment": [
"When direction flag is a compile time constant we can optimize",
"loads and stores can turn in to post-increment when known"
@@ -235,8 +235,7 @@
"rep movsb"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov w20, #0x1",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
@@ -273,17 +272,17 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x7",
"add x23, x0, x2",
"add x22, x1, x2",
"strb w21, [x28, #986]",
"mov x11, x23",
"mov x10, x22",
"mov x7, x20"
"add x22, x0, x2",
"add x21, x1, x2",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"mov x11, x22",
"mov x10, x21"
]
},
"positive rep movsw": {
"x86InstructionCount": 2,
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 43,
"Comment": [
"When direction flag is a compile time constant we can optimize",
"loads and stores can turn in to post-increment when known"
@@ -293,8 +292,7 @@
"rep movsw"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov w20, #0x1",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
@@ -331,17 +329,17 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x7",
"add x23, x0, x2, lsl #1",
"add x22, x1, x2, lsl #1",
"strb w21, [x28, #986]",
"mov x11, x23",
"mov x10, x22",
"mov x7, x20"
"add x22, x0, x2, lsl #1",
"add x21, x1, x2, lsl #1",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"mov x11, x22",
"mov x10, x21"
]
},
"positive rep movsd": {
"x86InstructionCount": 2,
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 43,
"Comment": [
"When direction flag is a compile time constant we can optimize",
"loads and stores can turn in to post-increment when known"
@@ -351,8 +349,7 @@
"rep movsd"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov w20, #0x1",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
@@ -389,17 +386,17 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x7",
"add x23, x0, x2, lsl #2",
"add x22, x1, x2, lsl #2",
"strb w21, [x28, #986]",
"mov x11, x23",
"mov x10, x22",
"mov x7, x20"
"add x22, x0, x2, lsl #2",
"add x21, x1, x2, lsl #2",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"mov x11, x22",
"mov x10, x21"
]
},
"positive rep movsq": {
"x86InstructionCount": 2,
"ExpectedInstructionCount": 44,
"ExpectedInstructionCount": 43,
"Comment": [
"When direction flag is a compile time constant we can optimize",
"loads and stores can turn in to post-increment when known"
@@ -409,8 +406,7 @@
"rep movsq"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov w20, #0x1",
"mov x0, x7",
"mov x1, x11",
"mov x2, x10",
@@ -447,12 +443,12 @@
"mov x0, x11",
"mov x1, x10",
"mov x2, x7",
"add x23, x0, x2, lsl #3",
"add x22, x1, x2, lsl #3",
"strb w21, [x28, #986]",
"mov x11, x23",
"mov x10, x22",
"mov x7, x20"
"add x22, x0, x2, lsl #3",
"add x21, x1, x2, lsl #3",
"mov w7, #0x0",
"strb w20, [x28, #986]",
"mov x11, x22",
"mov x10, x21"
]
},
"negative rep movsb": {
@@ -701,7 +697,7 @@
},
"positive rep stosb": {
"x86InstructionCount": 2,
"ExpectedInstructionCount": 30,
"ExpectedInstructionCount": 29,
"Comment": [
"When direction flag is a compile time constant we can optimize",
"loads and stores can turn in to post-increment when known"
@@ -711,15 +707,14 @@
"rep stosb"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"uxtb w22, w4",
"mov w20, #0x1",
"uxtb w21, w4",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x20 (32)",
"tbnz x0, #63, #+0x3c",
"dup v1.16b, w22",
"dup v1.16b, w21",
"sub x0, x0, #0x20 (32)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #32",
@@ -735,17 +730,17 @@
"tbz x0, #63, #-0x8",
"add x0, x0, #0x20 (32)",
"cbz x0, #+0x10",
"strb w22, [x1], #1",
"strb w21, [x1], #1",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x7",
"strb w21, [x28, #986]",
"mov x7, x20"
"mov w7, #0x0",
"strb w20, [x28, #986]"
]
},
"positive rep stosw": {
"x86InstructionCount": 2,
"ExpectedInstructionCount": 30,
"ExpectedInstructionCount": 29,
"Comment": [
"When direction flag is a compile time constant we can optimize",
"loads and stores can turn in to post-increment when known"
@@ -755,15 +750,14 @@
"rep stosw"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"uxth w22, w4",
"mov w20, #0x1",
"uxth w21, w4",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x10 (16)",
"tbnz x0, #63, #+0x3c",
"dup v1.8h, w22",
"dup v1.8h, w21",
"sub x0, x0, #0x10 (16)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #32",
@@ -779,17 +773,17 @@
"tbz x0, #63, #-0x8",
"add x0, x0, #0x10 (16)",
"cbz x0, #+0x10",
"strh w22, [x1], #2",
"strh w21, [x1], #2",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x7, lsl #1",
"strb w21, [x28, #986]",
"mov x7, x20"
"mov w7, #0x0",
"strb w20, [x28, #986]"
]
},
"positive rep stosd": {
"x86InstructionCount": 2,
"ExpectedInstructionCount": 30,
"ExpectedInstructionCount": 29,
"Comment": [
"When direction flag is a compile time constant we can optimize",
"loads and stores can turn in to post-increment when known"
@@ -799,15 +793,14 @@
"rep stosd"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov w22, w4",
"mov w20, #0x1",
"mov w21, w4",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x58",
"sub x0, x0, #0x8 (8)",
"tbnz x0, #63, #+0x3c",
"dup v1.4s, w22",
"dup v1.4s, w21",
"sub x0, x0, #0x8 (8)",
"tbnz x0, #63, #+0x14",
"stp q1, q1, [x1], #32",
@@ -823,17 +816,17 @@
"tbz x0, #63, #-0x8",
"add x0, x0, #0x8 (8)",
"cbz x0, #+0x10",
"str w22, [x1], #4",
"str w21, [x1], #4",
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x7, lsl #2",
"strb w21, [x28, #986]",
"mov x7, x20"
"mov w7, #0x0",
"strb w20, [x28, #986]"
]
},
"positive rep stosq": {
"x86InstructionCount": 2,
"ExpectedInstructionCount": 29,
"ExpectedInstructionCount": 28,
"Comment": [
"When direction flag is a compile time constant we can optimize",
"loads and stores can turn in to post-increment when known"
@@ -843,8 +836,7 @@
"rep stosq"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, #0x1",
"mov w20, #0x1",
"mov x0, x7",
"mov x1, x11",
"cbz x0, #+0x58",
@@ -870,8 +862,8 @@
"sub x0, x0, #0x1 (1)",
"cbnz x0, #-0x8",
"add x11, x11, x7, lsl #3",
"strb w21, [x28, #986]",
"mov x7, x20"
"mov w7, #0x0",
"strb w20, [x28, #986]"
]
},
"negative rep stosb": {
unittests/InstructionCountCI/FEXOpt/MultiInst_TSO_32bit.json
+2 -2
View File
@@ -74,9 +74,9 @@
"nop",
"ldapurh w20, [x7, #24]",
"nop",
"bfxil w4, w20, #0, #16",
"bfxil x4, x20, #0, #16",
"ldapurb w20, [x7, #26]",
"bfxil w6, w20, #0, #8"
"bfxil x6, x20, #0, #8"
]
},
"Store variables to memory": {
unittests/InstructionCountCI/FlagM/Atomics.json
+26 -46
View File
@@ -82,7 +82,7 @@
"cinc w20, w7, lo",
"ldaddalb w20, w20, [x4]",
"eor x27, x20, x7",
"uxtb w21, w7",
"uxtb x21, w7",
"cinc w22, w21, lo",
"add w23, w20, w22",
"uxtb w26, w23",
@@ -103,7 +103,7 @@
"cinc w20, w7, lo",
"ldaddalh w20, w20, [x4]",
"eor x27, x20, x7",
"uxth w21, w7",
"uxth x21, w7",
"cinc w22, w21, lo",
"add w23, w20, w22",
"uxth w26, w23",
@@ -138,7 +138,7 @@
"ldaddalb w1, w20, [x4]",
"eor x27, x20, x7",
"uxtb w20, w20",
"uxtb w21, w7",
"uxtb x21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxtb w26, w23",
@@ -161,7 +161,7 @@
"ldaddalh w1, w20, [x4]",
"eor x27, x20, x7",
"uxth w20, w20",
"uxth w21, w7",
"uxth x21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxth w26, w23",
@@ -580,7 +580,7 @@
]
},
"lock adc byte [rax], 1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -593,14 +593,12 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w27, #0x1",
"eor w21, w26, w27",
"bic w20, w21, w20",
"bic w20, w26, w27",
"rmif x20, #7, #nzcV"
]
},
"lock adc byte [rax], 0xFF": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -614,14 +612,12 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"bic w20, w21, w20",
"bic w20, w21, w26",
"rmif x20, #7, #nzcV"
]
},
"lock adc word [rax], 0x100": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
@@ -634,14 +630,12 @@
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"eor w20, w27, #0x100",
"eor w21, w26, w27",
"bic w20, w21, w20",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV"
]
},
"lock adc word [rax], 0xFFFF": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
@@ -655,9 +649,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xffff",
"eor w21, w26, w21",
"bic w20, w21, w20",
"bic w20, w21, w26",
"rmif x20, #15, #nzcV"
]
},
@@ -711,7 +703,7 @@
]
},
"lock adc word [rax], 1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -724,9 +716,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"eor w20, w27, #0x1",
"eor w21, w26, w27",
"bic w20, w21, w20",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV"
]
},
@@ -755,7 +745,7 @@
]
},
"lock sbb byte [rax], 1": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -770,14 +760,12 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"rmif x20, #7, #nzcV"
]
},
"lock sbb byte [rax], 0xFF": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -793,14 +781,12 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w26, w21",
"rmif x20, #7, #nzcV"
]
},
"lock sbb word [rax], 0x100": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
@@ -815,14 +801,12 @@
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x100",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"rmif x20, #15, #nzcV"
]
},
"lock sbb word [rax], 0xFFFF": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
@@ -838,9 +822,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xffff",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w26, w21",
"rmif x20, #15, #nzcV"
]
},
@@ -890,7 +872,7 @@
]
},
"lock sbb word [rax], 1": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -905,9 +887,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"rmif x20, #15, #nzcV"
]
},
@@ -1241,8 +1221,8 @@
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldeoral w20, w20, [x4]",
"mvn w20, w20",
"ldeoral w20, w21, [x4]",
"eor w20, w21, w20",
"subs w26, w20, #0x0 (0)"
]
},
unittests/InstructionCountCI/FlagM/HotBlocks.json
+1 -1
View File
@@ -411,7 +411,7 @@
"and x20, x7, #0x7",
"mov x21, x15",
"bfi w21, w15, #24, #8",
"neg w20, w20",
"neg x20, x20",
"ror w20, w21, w20",
"bfxil x15, x20, #0, #8",
"and w20, w15, w14",
unittests/InstructionCountCI/FlagM/Primary.json
+24 -40
View File
@@ -382,7 +382,7 @@
"Comment": "0x10",
"ExpectedArm64ASM": [
"eor x27, x6, x7",
"uxtb w20, w7",
"uxtb x20, w7",
"cinc w21, w20, lo",
"add w22, w6, w21",
"uxtb w26, w22",
@@ -402,7 +402,7 @@
"Comment": "0x11",
"ExpectedArm64ASM": [
"eor x27, x6, x7",
"uxth w20, w7",
"uxth x20, w7",
"cinc w21, w20, lo",
"add w22, w6, w21",
"uxth w26, w22",
@@ -447,7 +447,7 @@
],
"ExpectedArm64ASM": [
"eor x27, x7, x6",
"uxtb w20, w6",
"uxtb x20, w6",
"cinc w21, w20, lo",
"add w22, w7, w21",
"uxtb w26, w22",
@@ -470,7 +470,7 @@
],
"ExpectedArm64ASM": [
"eor x27, x7, x6",
"uxth w20, w6",
"uxth x20, w6",
"cinc w21, w20, lo",
"add w22, w7, w21",
"uxth w26, w22",
@@ -514,7 +514,7 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "0x14",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -525,9 +525,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w4, #0x1",
"eor w21, w26, w4",
"bic w20, w21, w20",
"bic w20, w26, w4",
"rmif x20, #7, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
@@ -536,7 +534,7 @@
]
},
"adc ax, 1": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -547,9 +545,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"eor w20, w4, #0x1",
"eor w21, w26, w4",
"bic w20, w21, w20",
"bic w20, w26, w4",
"rmif x20, #15, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
@@ -582,7 +578,7 @@
]
},
"adc al, -1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "0x14",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -594,15 +590,13 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w4, #0xff",
"eor w21, w26, w4",
"bic w20, w21, w20",
"bic w20, w4, w26",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"adc ax, -1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
@@ -614,9 +608,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"eor w20, w4, #0xffff",
"eor w21, w26, w4",
"bic w20, w21, w20",
"bic w20, w4, w26",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
@@ -651,7 +643,7 @@
"ExpectedArm64ASM": [
"eor x27, x6, x7",
"uxtb w20, w6",
"uxtb w21, w7",
"uxtb x21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxtb w26, w23",
@@ -672,7 +664,7 @@
"ExpectedArm64ASM": [
"eor x27, x6, x7",
"uxth w20, w6",
"uxth w21, w7",
"uxth x21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxth w26, w23",
@@ -714,7 +706,7 @@
"ExpectedArm64ASM": [
"eor x27, x7, x6",
"uxtb w20, w7",
"uxtb w21, w6",
"uxtb x21, w6",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxtb w26, w23",
@@ -738,7 +730,7 @@
"ExpectedArm64ASM": [
"eor x27, x7, x6",
"uxth w20, w7",
"uxth w21, w6",
"uxth x21, w6",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxth w26, w23",
@@ -778,7 +770,7 @@
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -790,9 +782,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"rmif x20, #7, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
@@ -801,7 +791,7 @@
]
},
"sbb ax, 1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -813,9 +803,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"rmif x20, #15, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #16",
@@ -844,7 +832,7 @@
]
},
"sbb al, -1": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -857,15 +845,13 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w26, w21",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"sbb ax, -1": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
@@ -878,9 +864,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #16",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xffff",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w26, w21",
"rmif x20, #15, #nzcV",
"bfxil x4, x26, #0, #16"
]
unittests/InstructionCountCI/FlagM/PrimaryGroup.json
+21 -29
View File
@@ -38,7 +38,7 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 16,
"ExpectedInstructionCount": 14,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -49,9 +49,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w4, #0x1",
"eor w21, w26, w4",
"bic w20, w21, w20",
"bic w20, w26, w4",
"rmif x20, #7, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
@@ -60,7 +58,7 @@
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -72,9 +70,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"rmif x20, #7, #nzcV",
"mov x20, x4",
"bfxil x20, x26, #0, #8",
@@ -151,7 +147,7 @@
]
},
"adc al, -1": {
"ExpectedInstructionCount": 14,
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -163,15 +159,13 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w4, #0xff",
"eor w21, w26, w4",
"bic w20, w21, w20",
"bic w20, w4, w26",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
},
"sbb al, -1": {
"ExpectedInstructionCount": 15,
"ExpectedInstructionCount": 13,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -184,9 +178,7 @@
"cset x20, hs",
"cmn wzr, w26, lsl #24",
"rmif x20, #63, #nzCv",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w26, w21",
"rmif x20, #7, #nzcV",
"bfxil x4, x26, #0, #8"
]
@@ -1594,7 +1586,7 @@
"and x20, x7, #0x7",
"mov x21, x4",
"bfi w21, w4, #24, #8",
"neg w20, w20",
"neg x20, x20",
"ror w20, w21, w20",
"bfxil x4, x20, #0, #8",
"and x21, x7, #0x1f",
@@ -1626,9 +1618,9 @@
"ExpectedInstructionCount": 27,
"Comment": "GROUP2 0xd2 /2",
"ExpectedArm64ASM": [
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cbz x20, #+0x68",
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"uxtb w21, w4",
"mov w22, #0x0",
"cset w23, lo",
@@ -1643,7 +1635,7 @@
"bfi x22, x21, #19, #8",
"bfi x22, x23, #27, #1",
"bfxil x22, x21, #0, #8",
"neg w21, w20",
"neg x21, x20",
"ror x21, x22, x21",
"bfxil x4, x21, #0, #8",
"mov w23, #0x3f",
@@ -1659,9 +1651,9 @@
"ExpectedInstructionCount": 17,
"Comment": "GROUP2 0xd2 /3",
"ExpectedArm64ASM": [
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cbz x20, #+0x40",
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cset w21, lo",
"uxtb w22, w4",
"bfi x22, x21, #8, #1",
@@ -1737,7 +1729,7 @@
"and x20, x7, #0x1f",
"mov x21, x4",
"bfi w21, w4, #16, #16",
"neg w22, w20",
"neg x22, x20",
"ror w21, w21, w22",
"bfxil x4, x21, #0, #16",
"cbz w20, #+0x14",
@@ -1752,7 +1744,7 @@
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x7, #0x1f",
"neg w21, w20",
"neg x21, x20",
"ror w4, w4, w21",
"cbz w20, #+0x14",
"eor x0, x4, x4, lsr #31",
@@ -1821,9 +1813,9 @@
"ExpectedInstructionCount": 23,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cbz x20, #+0x58",
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"uxth w21, w4",
"mov w22, #0x0",
"cset w23, lo",
@@ -1834,7 +1826,7 @@
"bfi x22, x21, #13, #16",
"bfi x22, x23, #29, #1",
"bfxil x22, x21, #0, #16",
"neg w21, w20",
"neg x21, x20",
"ror x21, x22, x21",
"bfxil x4, x21, #0, #16",
"mov w23, #0x3f",
@@ -1894,9 +1886,9 @@
"ExpectedInstructionCount": 16,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cbz x20, #+0x3c",
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cset w21, lo",
"uxth w22, w4",
"bfi x22, x21, #16, #1",
unittests/InstructionCountCI/FlagM/Primary_32Bit.json
+11 -11
View File
@@ -111,7 +111,7 @@
"add x23, x20, #0x60 (96)",
"cmp x21, #0x0 (0)",
"csel x26, x23, x20, eq",
"bfxil w4, w26, #0, #8",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24",
"rmif x21, #63, #nzCv",
"eor w27, w26, w22, lsl #4"
@@ -141,7 +141,7 @@
"sub x24, x20, #0x60 (96)",
"cmp x21, #0x0 (0)",
"csel x26, x24, x20, ne",
"bfxil w4, w26, #0, #8",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24",
"eor x20, x23, #0x1",
"rmif x20, #63, #nzCv",
@@ -164,7 +164,7 @@
"csel w20, w20, w4, lo",
"mov w21, #0xff0f",
"and w20, w20, w21",
"bfxil w4, w20, #0, #16"
"bfxil x4, x20, #0, #16"
]
},
"aas": {
@@ -183,7 +183,7 @@
"csel w20, w20, w4, lo",
"mov w21, #0xff0f",
"and w20, w20, w21",
"bfxil w4, w20, #0, #16"
"bfxil x4, x20, #0, #16"
]
},
"inc ax": {
@@ -195,7 +195,7 @@
"setf16 w26",
"bic w20, w26, w27",
"rmif x20, #15, #nzcV",
"bfxil w4, w26, #0, #16"
"bfxil x4, x26, #0, #16"
]
},
"inc eax": {
@@ -218,7 +218,7 @@
"setf16 w26",
"bic w20, w27, w26",
"rmif x20, #15, #nzcV",
"bfxil w4, w26, #0, #16"
"bfxil x4, x26, #0, #16"
]
},
"push ax": {
@@ -394,7 +394,7 @@
"udiv x2, x20, x21",
"msub x20, x2, x21, x20",
"add x26, x20, x22, lsl #8",
"bfxil w4, w26, #0, #16",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #24",
"cfinv"
]
@@ -408,7 +408,7 @@
"mul x20, x20, x21",
"add x20, x4, x20",
"and x26, x20, #0xff",
"bfxil w4, w26, #0, #16",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #24",
"cfinv"
]
@@ -426,7 +426,7 @@
"udiv x2, x20, x21",
"msub x20, x2, x21, x20",
"add x26, x20, x22, lsl #8",
"bfxil w4, w26, #0, #16",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #24",
"cfinv"
]
@@ -443,7 +443,7 @@
"mul x20, x20, x21",
"add x20, x4, x20",
"and x26, x20, #0xff",
"bfxil w4, w26, #0, #16",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #24",
"cfinv"
]
@@ -453,7 +453,7 @@
"Comment": "0xd6",
"ExpectedArm64ASM": [
"csetm w20, lo",
"bfxil w4, w20, #0, #8"
"bfxil x4, x20, #0, #8"
]
}
}
unittests/InstructionCountCI/Primary.json
+34 -48
View File
@@ -431,7 +431,7 @@
"Comment": "0x10",
"ExpectedArm64ASM": [
"eor x27, x6, x7",
"uxtb w20, w7",
"uxtb x20, w7",
"cinc w21, w20, lo",
"add w22, w6, w21",
"uxtb w26, w22",
@@ -454,7 +454,7 @@
"Comment": "0x11",
"ExpectedArm64ASM": [
"eor x27, x6, x7",
"uxth w20, w7",
"uxth x20, w7",
"cinc w21, w20, lo",
"add w22, w6, w21",
"uxth w26, w22",
@@ -510,7 +510,7 @@
],
"ExpectedArm64ASM": [
"eor x27, x7, x6",
"uxtb w20, w6",
"uxtb x20, w6",
"cinc w21, w20, lo",
"add w22, w7, w21",
"uxtb w26, w22",
@@ -536,7 +536,7 @@
],
"ExpectedArm64ASM": [
"eor x27, x7, x6",
"uxth w20, w6",
"uxth x20, w6",
"cinc w21, w20, lo",
"add w22, w7, w21",
"uxth w26, w22",
@@ -591,7 +591,7 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "0x14",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -603,9 +603,7 @@
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w4, #0x1",
"eor w22, w26, w4",
"bic w20, w22, w20",
"bic w20, w26, w4",
"ubfx x20, x20, #7, #1",
"bfi w21, w20, #28, #1",
"mov x20, x4",
@@ -616,7 +614,7 @@
]
},
"adc ax, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -628,9 +626,7 @@
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w4, #0x1",
"eor w22, w26, w4",
"bic w20, w22, w20",
"bic w20, w26, w4",
"ubfx x20, x20, #15, #1",
"bfi w21, w20, #28, #1",
"mov x20, x4",
@@ -673,7 +669,7 @@
]
},
"adc al, -1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "0x14",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -686,9 +682,7 @@
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w4, #0xff",
"eor w22, w26, w4",
"bic w20, w22, w20",
"bic w20, w4, w26",
"ubfx x20, x20, #7, #1",
"bfi w21, w20, #28, #1",
"bfxil x4, x26, #0, #8",
@@ -696,7 +690,7 @@
]
},
"adc ax, -1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "0x15",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
@@ -709,9 +703,7 @@
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w4, #0xffff",
"eor w22, w26, w4",
"bic w20, w22, w20",
"bic w20, w4, w26",
"ubfx x20, x20, #15, #1",
"bfi w21, w20, #28, #1",
"bfxil x4, x26, #0, #16",
@@ -756,7 +748,7 @@
"ExpectedArm64ASM": [
"eor x27, x6, x7",
"uxtb w20, w6",
"uxtb w21, w7",
"uxtb x21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxtb w26, w23",
@@ -780,7 +772,7 @@
"ExpectedArm64ASM": [
"eor x27, x6, x7",
"uxth w20, w6",
"uxth w21, w7",
"uxth x21, w7",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxth w26, w23",
@@ -825,7 +817,7 @@
"ExpectedArm64ASM": [
"eor x27, x7, x6",
"uxtb w20, w7",
"uxtb w21, w6",
"uxtb x21, w6",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxtb w26, w23",
@@ -852,7 +844,7 @@
"ExpectedArm64ASM": [
"eor x27, x7, x6",
"uxth w20, w7",
"uxth w21, w6",
"uxth x21, w6",
"cinc w22, w21, lo",
"sub w23, w20, w22",
"uxth w26, w23",
@@ -895,7 +887,7 @@
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -908,9 +900,7 @@
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"ubfx x20, x20, #7, #1",
"bfi w22, w20, #28, #1",
"mov x20, x4",
@@ -921,7 +911,7 @@
]
},
"sbb ax, 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -934,9 +924,7 @@
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"ubfx x20, x20, #15, #1",
"bfi w22, w20, #28, #1",
"mov x20, x4",
@@ -967,7 +955,7 @@
]
},
"sbb al, -1": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 16,
"Comment": "0x1C",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -981,9 +969,7 @@
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w26, w21",
"ubfx x20, x20, #7, #1",
"bfi w22, w20, #28, #1",
"bfxil x4, x26, #0, #8",
@@ -991,7 +977,7 @@
]
},
"sbb ax, -1": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 16,
"Comment": "0x1D",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
@@ -1005,9 +991,7 @@
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0xffff",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w26, w21",
"ubfx x20, x20, #15, #1",
"bfi w22, w20, #28, #1",
"bfxil x4, x26, #0, #16",
@@ -4490,21 +4474,23 @@
]
},
"clc": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "0xf8",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"orr w20, w20, #0x20000000",
"msr nzcv, x20"
"mov w20, #0x1",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"stc": {
"ExpectedInstructionCount": 3,
"ExpectedInstructionCount": 4,
"Comment": "0xf9",
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"and w20, w20, #0xdfffffff",
"msr nzcv, x20"
"mov w20, #0x0",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"cli": {
unittests/InstructionCountCI/PrimaryGroup.json
+21 -29
View File
@@ -45,7 +45,7 @@
]
},
"adc al, 1": {
"ExpectedInstructionCount": 19,
"ExpectedInstructionCount": 17,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -57,9 +57,7 @@
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w4, #0x1",
"eor w22, w26, w4",
"bic w20, w22, w20",
"bic w20, w26, w4",
"ubfx x20, x20, #7, #1",
"bfi w21, w20, #28, #1",
"mov x20, x4",
@@ -70,7 +68,7 @@
]
},
"sbb al, 1": {
"ExpectedInstructionCount": 20,
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
@@ -83,9 +81,7 @@
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0x1",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w21, w26",
"ubfx x20, x20, #7, #1",
"bfi w22, w20, #28, #1",
"mov x20, x4",
@@ -172,7 +168,7 @@
]
},
"adc al, -1": {
"ExpectedInstructionCount": 17,
"ExpectedInstructionCount": 15,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -185,9 +181,7 @@
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"eor w20, w4, #0xff",
"eor w22, w26, w4",
"bic w20, w22, w20",
"bic w20, w4, w26",
"ubfx x20, x20, #7, #1",
"bfi w21, w20, #28, #1",
"bfxil x4, x26, #0, #8",
@@ -195,7 +189,7 @@
]
},
"sbb al, -1": {
"ExpectedInstructionCount": 18,
"ExpectedInstructionCount": 16,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
@@ -209,9 +203,7 @@
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"bfi w22, w20, #29, #1",
"eor w20, w21, #0xff",
"eor w21, w26, w21",
"and w20, w21, w20",
"bic w20, w26, w21",
"ubfx x20, x20, #7, #1",
"bfi w22, w20, #28, #1",
"bfxil x4, x26, #0, #8",
@@ -1889,7 +1881,7 @@
"and x20, x7, #0x7",
"mov x21, x4",
"bfi w21, w4, #24, #8",
"neg w20, w20",
"neg x20, x20",
"ror w20, w21, w20",
"bfxil x4, x20, #0, #8",
"and x21, x7, #0x1f",
@@ -1927,9 +1919,9 @@
"ExpectedInstructionCount": 31,
"Comment": "GROUP2 0xd2 /2",
"ExpectedArm64ASM": [
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cbz x20, #+0x78",
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"uxtb w21, w4",
"mov w22, #0x0",
"cset w23, lo",
@@ -1944,7 +1936,7 @@
"bfi x22, x21, #19, #8",
"bfi x22, x23, #27, #1",
"bfxil x22, x21, #0, #8",
"neg w21, w20",
"neg x21, x20",
"ror x21, x22, x21",
"bfxil x4, x21, #0, #8",
"mov w23, #0x3f",
@@ -1964,9 +1956,9 @@
"ExpectedInstructionCount": 21,
"Comment": "GROUP2 0xd2 /3",
"ExpectedArm64ASM": [
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cbz x20, #+0x50",
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cset w21, lo",
"uxtb w22, w4",
"bfi x22, x21, #8, #1",
@@ -2055,7 +2047,7 @@
"and x20, x7, #0x1f",
"mov x21, x4",
"bfi w21, w4, #16, #16",
"neg w22, w20",
"neg x22, x20",
"ror w21, w21, w22",
"bfxil x4, x21, #0, #16",
"cbz w20, #+0x1c",
@@ -2072,7 +2064,7 @@
"Comment": "GROUP2 0xd3 /0",
"ExpectedArm64ASM": [
"and x20, x7, #0x1f",
"neg w21, w20",
"neg x21, x20",
"ror w4, w4, w21",
"cbz w20, #+0x1c",
"eor x0, x4, x4, lsr #31",
@@ -2157,9 +2149,9 @@
"ExpectedInstructionCount": 27,
"Comment": "GROUP2 0xd3 /2",
"ExpectedArm64ASM": [
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cbz x20, #+0x68",
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"uxth w21, w4",
"mov w22, #0x0",
"cset w23, lo",
@@ -2170,7 +2162,7 @@
"bfi x22, x21, #13, #16",
"bfi x22, x23, #29, #1",
"bfxil x22, x21, #0, #16",
"neg w21, w20",
"neg x21, x20",
"ror x21, x22, x21",
"bfxil x4, x21, #0, #16",
"mov w23, #0x3f",
@@ -2242,9 +2234,9 @@
"ExpectedInstructionCount": 20,
"Comment": "GROUP2 0xd3 /3",
"ExpectedArm64ASM": [
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cbz x20, #+0x4c",
"and w20, w7, #0x1f",
"and x20, x7, #0x1f",
"cset w21, lo",
"uxth w22, w4",
"bfi x22, x21, #16, #1",
unittests/InstructionCountCI/Primary_32Bit.json
+11 -11
View File
@@ -110,7 +110,7 @@
"add x23, x20, #0x60 (96)",
"cmp x21, #0x0 (0)",
"csel x26, x23, x20, eq",
"bfxil w4, w26, #0, #8",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
@@ -142,7 +142,7 @@
"sub x24, x20, #0x60 (96)",
"cmp x21, #0x0 (0)",
"csel x26, x24, x20, ne",
"bfxil w4, w26, #0, #8",
"bfxil x4, x26, #0, #8",
"cmn wzr, w26, lsl #24",
"eor x20, x23, #0x1",
"mrs x21, nzcv",
@@ -167,7 +167,7 @@
"csel w20, w20, w4, lo",
"mov w21, #0xff0f",
"and w20, w20, w21",
"bfxil w4, w20, #0, #16"
"bfxil x4, x20, #0, #16"
]
},
"aas": {
@@ -186,7 +186,7 @@
"csel w20, w20, w4, lo",
"mov w21, #0xff0f",
"and w20, w20, w21",
"bfxil w4, w20, #0, #16"
"bfxil x4, x20, #0, #16"
]
},
"inc ax": {
@@ -201,7 +201,7 @@
"add w26, w27, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"bfxil w4, w26, #0, #16",
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
]
},
@@ -230,7 +230,7 @@
"sub w26, w27, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"bfxil w4, w26, #0, #16",
"bfxil x4, x26, #0, #16",
"msr nzcv, x20"
]
},
@@ -319,7 +319,7 @@
"udiv x2, x20, x21",
"msub x20, x2, x21, x20",
"add x26, x20, x22, lsl #8",
"bfxil w4, w26, #0, #16",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -335,7 +335,7 @@
"mul x20, x20, x21",
"add x20, x4, x20",
"and x26, x20, #0xff",
"bfxil w4, w26, #0, #16",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -355,7 +355,7 @@
"udiv x2, x20, x21",
"msub x20, x2, x21, x20",
"add x26, x20, x22, lsl #8",
"bfxil w4, w26, #0, #16",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -374,7 +374,7 @@
"mul x20, x20, x21",
"add x20, x4, x20",
"and x26, x20, #0xff",
"bfxil w4, w26, #0, #16",
"bfxil x4, x26, #0, #16",
"cmn wzr, w26, lsl #24",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
@@ -386,7 +386,7 @@
"Comment": "0xd6",
"ExpectedArm64ASM": [
"csetm w20, lo",
"bfxil w4, w20, #0, #8"
"bfxil x4, x20, #0, #8"
]
}
}
unittests/InstructionCountCI/VEX_map1.json
+16 -30
View File
@@ -489,51 +489,42 @@
]
},
"vmovmskps rax, ymm0": {
"ExpectedInstructionCount": 41,
"ExpectedInstructionCount": 32,
"Comment": [
"Map 1 0b00 0x50 256-bit"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov w21, v16.s[0]",
"lsr w21, w21, #31",
"orr x20, x20, x21",
"mov w20, v16.s[0]",
"lsr w20, w20, #31",
"mov w21, v16.s[1]",
"lsr w21, w21, #31",
"lsl w21, w21, #1",
"orr x20, x20, x21",
"orr x20, x20, x21, lsl #1",
"mov w21, v16.s[2]",
"lsr w21, w21, #31",
"lsl w21, w21, #2",
"orr x20, x20, x21",
"orr x20, x20, x21, lsl #2",
"mov w21, v16.s[3]",
"lsr w21, w21, #31",
"lsl w21, w21, #3",
"orr x20, x20, x21",
"orr x20, x20, x21, lsl #3",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov w21, v16.s[0]",
"lsr w21, w21, #31",
"lsl w21, w21, #4",
"orr x20, x20, x21",
"orr x20, x20, x21, lsl #4",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov w21, v16.s[1]",
"lsr w21, w21, #31",
"lsl w21, w21, #5",
"orr x20, x20, x21",
"orr x20, x20, x21, lsl #5",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov w21, v16.s[2]",
"lsr w21, w21, #31",
"lsl w21, w21, #6",
"orr x20, x20, x21",
"orr x20, x20, x21, lsl #6",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov w21, v16.s[3]",
"lsr w21, w21, #31",
"lsl w21, w21, #7",
"orr x20, x20, x21",
"orr x20, x20, x21, lsl #7",
"mov w4, w20"
]
},
@@ -550,31 +541,26 @@
]
},
"vmovmskpd rax, ymm0": {
"ExpectedInstructionCount": 21,
"ExpectedInstructionCount": 16,
"Comment": [
"Map 1 0b01 0x50 256-bit"
],
"ExpectedArm64ASM": [
"mov w20, #0x0",
"mov x21, v16.d[0]",
"lsr x21, x21, #63",
"orr x20, x20, x21",
"mov x20, v16.d[0]",
"lsr x20, x20, #63",
"mov x21, v16.d[1]",
"lsr x21, x21, #63",
"lsl x21, x21, #1",
"orr x20, x20, x21",
"orr x20, x20, x21, lsl #1",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov x21, v16.d[0]",
"lsr x21, x21, #63",
"lsl x21, x21, #2",
"orr x20, x20, x21",
"orr x20, x20, x21, lsl #2",
"not p0.b, p7/z, p6.b",
"compact z0.d, p0, z16.d",
"mov x21, v16.d[1]",
"lsr x21, x21, #63",
"lsl x21, x21, #3",
"orr x20, x20, x21",
"orr x20, x20, x21, lsl #3",
"mov w4, w20"
]
},