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Merge pull request #3091 from Sonicadvance1/optimize_pinsr

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OpcodeDispatcher: Optimize pins{b,w,d,q}
This commit is contained in:
Mai authored and GitHub committed 2023-09-14 00:30:56 -04:00
2 parents d4c6749d2a 2bafa2c26f
commit 213d3c4e2b
6 files changed
+235 -123
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FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp
+10 -11
View File
@@ -1519,20 +1519,19 @@ OrderedNode* OpDispatchBuilder::PINSROpImpl(OpcodeArgs, size_t ElementSize,
const X86Tables::DecodedOperand& Imm) {
const auto Size = GetDstSize(Op);
const auto NumElements = Size / ElementSize;
OrderedNode *Src2{};
if (Src2Op.IsGPR()) {
Src2 = LoadSource(GPRClass, Op, Src2Op, Op->Flags, -1);
} else {
// If loading from memory then we only load the element size
Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, ElementSize, Op->Flags, -1);
}
OrderedNode *Src1 = LoadSource_WithOpSize(FPRClass, Op, Src1Op, Size, Op->Flags, -1);
LOGMAN_THROW_A_FMT(Imm.IsLiteral(), "Imm needs to be literal here");
const uint64_t Index = Imm.Data.Literal.Value & (NumElements - 1);
OrderedNode *Src1 = LoadSource_WithOpSize(FPRClass, Op, Src1Op, Size, Op->Flags, -1);
return _VInsGPR(Size, ElementSize, Index, Src1, Src2);
if (Src2Op.IsGPR()) {
// If the source is a GPR then convert directly from the GPR.
auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, CTX->GetGPRSize(), Op->Flags, -1);
return _VInsGPR(Size, ElementSize, Index, Src1, Src2);
}
// If loading from memory then we only load the element size
auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, ElementSize, Op->Flags, -1, false);
return _VLoadVectorElement(Size, ElementSize, Src1, Index, Src2);
}
template<size_t ElementSize>
unittests/InstructionCountCI/H0F3A.json
+98 -24
View File
@@ -800,36 +800,63 @@
]
},
"pinsrb xmm0, eax, 0000b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov v16.b[0], w20"
"mov v16.b[0], w4"
]
},
"pinsrb xmm0, eax, 0001b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov v16.b[1], w20"
"mov v16.b[1], w4"
]
},
"pinsrb xmm0, eax, 1111b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov v16.b[15], w20"
"mov v16.b[15], w4"
]
},
"pinsrb xmm0, [rax], 0000b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"ld1 {v16.b}[0], [x4]"
]
},
"pinsrb xmm0, [rax], 0001b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"ld1 {v16.b}[1], [x4]"
]
},
"pinsrb xmm0, [rax], 1111b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x20"
],
"ExpectedArm64ASM": [
"ld1 {v16.b}[15], [x4]"
]
},
"insertps xmm0, xmm1, 00000000b": {
@@ -863,36 +890,33 @@
]
},
"pinsrd xmm0, eax, 00b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov v16.s[0], w20"
"mov v16.s[0], w4"
]
},
"pinsrd xmm0, eax, 01b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov v16.s[1], w20"
"mov v16.s[1], w4"
]
},
"pinsrd xmm0, eax, 11b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov v16.s[3], w20"
"mov v16.s[3], w4"
]
},
"pinsrq xmm0, rax, 0b": {
@@ -915,6 +939,56 @@
"mov v16.d[1], x4"
]
},
"pinsrd xmm0, [rax], 00b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ld1 {v16.s}[0], [x4]"
]
},
"pinsrd xmm0, [rax], 01b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ld1 {v16.s}[1], [x4]"
]
},
"pinsrd xmm0, [rax], 11b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ld1 {v16.s}[3], [x4]"
]
},
"pinsrq xmm0, [rax], 0b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 REX.W 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ld1 {v16.d}[0], [x4]"
]
},
"pinsrq xmm0, [rax], 1b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": [
"0x66 REX.W 0x0f 0x3a 0x22"
],
"ExpectedArm64ASM": [
"ld1 {v16.d}[1], [x4]"
]
},
"dpps xmm0, xmm1, 00000000b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
unittests/InstructionCountCI/Secondary.json
+25 -35
View File
@@ -3452,112 +3452,102 @@
]
},
"pinsrw mm0, eax, 0": {
"ExpectedInstructionCount": 4,
"Optimal": "No",
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"ldr d2, [x28, #752]",
"mov v2.h[0], w20",
"mov v2.h[0], w4",
"str d2, [x28, #752]"
]
},
"pinsrw mm0, eax, 1": {
"ExpectedInstructionCount": 4,
"Optimal": "No",
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"ldr d2, [x28, #752]",
"mov v2.h[1], w20",
"mov v2.h[1], w4",
"str d2, [x28, #752]"
]
},
"pinsrw mm0, eax, 2": {
"ExpectedInstructionCount": 4,
"Optimal": "No",
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"ldr d2, [x28, #752]",
"mov v2.h[2], w20",
"mov v2.h[2], w4",
"str d2, [x28, #752]"
]
},
"pinsrw mm0, eax, 3": {
"ExpectedInstructionCount": 4,
"Optimal": "No",
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"ldr d2, [x28, #752]",
"mov v2.h[3], w20",
"mov v2.h[3], w4",
"str d2, [x28, #752]"
]
},
"pinsrw mm0, eax, 4": {
"ExpectedInstructionCount": 4,
"Optimal": "No",
"ExpectedInstructionCount": 3,
"Optimal": "Yes",
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"ldr d2, [x28, #752]",
"mov v2.h[0], w20",
"mov v2.h[0], w4",
"str d2, [x28, #752]"
]
},
"pinsrw mm0, [rax], 0": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"ldr d2, [x28, #752]",
"mov v2.h[0], w20",
"ld1 {v2.h}[0], [x4]",
"str d2, [x28, #752]"
]
},
"pinsrw mm0, [rax], 1": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"ldr d2, [x28, #752]",
"mov v2.h[1], w20",
"ld1 {v2.h}[1], [x4]",
"str d2, [x28, #752]"
]
},
"pinsrw mm0, [rax], 2": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"ldr d2, [x28, #752]",
"mov v2.h[2], w20",
"ld1 {v2.h}[2], [x4]",
"str d2, [x28, #752]"
]
},
"pinsrw mm0, [rax], 3": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"ldr d2, [x28, #752]",
"mov v2.h[3], w20",
"ld1 {v2.h}[3], [x4]",
"str d2, [x28, #752]"
]
},
"pinsrw mm0, [rax], 4": {
"ExpectedInstructionCount": 4,
"ExpectedInstructionCount": 3,
"Optimal": "No",
"Comment": "0x0f 0xc4",
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"ldr d2, [x28, #752]",
"mov v2.h[0], w20",
"ld1 {v2.h}[0], [x4]",
"str d2, [x28, #752]"
]
},
unittests/InstructionCountCI/Secondary_OpSize.json
+88 -32
View File
@@ -810,75 +810,131 @@
]
},
"pinsrw xmm0, eax, 000b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov v16.h[0], w20"
"mov v16.h[0], w4"
]
},
"pinsrw xmm0, eax, 001b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov v16.h[1], w20"
"mov v16.h[1], w4"
]
},
"pinsrw xmm0, eax, 010b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov v16.h[2], w20"
"mov v16.h[2], w4"
]
},
"pinsrw xmm0, eax, 011b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov v16.h[3], w20"
"mov v16.h[3], w4"
]
},
"pinsrw xmm0, eax, 100b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov v16.h[4], w20"
"mov v16.h[4], w4"
]
},
"pinsrw xmm0, eax, 101b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov v16.h[5], w20"
"mov v16.h[5], w4"
]
},
"pinsrw xmm0, eax, 110b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov v16.h[6], w20"
"mov v16.h[6], w4"
]
},
"pinsrw xmm0, eax, 111b": {
"ExpectedInstructionCount": 2,
"Optimal": "No",
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov v16.h[7], w20"
"mov v16.h[7], w4"
]
},
"pinsrw xmm0, [rax], 000b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"ld1 {v16.h}[0], [x4]"
]
},
"pinsrw xmm0, [rax], 001b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"ld1 {v16.h}[1], [x4]"
]
},
"pinsrw xmm0, [rax], 010b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"ld1 {v16.h}[2], [x4]"
]
},
"pinsrw xmm0, [rax], 011b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"ld1 {v16.h}[3], [x4]"
]
},
"pinsrw xmm0, [rax], 100b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"ld1 {v16.h}[4], [x4]"
]
},
"pinsrw xmm0, [rax], 101b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"ld1 {v16.h}[5], [x4]"
]
},
"pinsrw xmm0, [rax], 110b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"ld1 {v16.h}[6], [x4]"
]
},
"pinsrw xmm0, [rax], 111b": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x66 0x0f 0xc4",
"ExpectedArm64ASM": [
"ld1 {v16.h}[7], [x4]"
]
},
"pextrw eax, xmm0, 000b": {
unittests/InstructionCountCI/VEX_map1.json
+6 -9
View File
@@ -3067,43 +3067,40 @@
]
},
"vpinsrw xmm0, xmm1, eax, 000b": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"Map 1 0b01 0xC4 128-bit"
],
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov z2.d, p7/m, z17.d",
"mov v2.h[0], w20",
"mov v2.h[0], w4",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpinsrw xmm0, xmm1, eax, 001b": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"Map 1 0b01 0xC4 128-bit"
],
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov z2.d, p7/m, z17.d",
"mov v2.h[1], w20",
"mov v2.h[1], w4",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpinsrw xmm0, xmm1, eax, 111b": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"Map 1 0b01 0xC4 128-bit"
],
"ExpectedArm64ASM": [
"uxth w20, w4",
"mov z2.d, p7/m, z17.d",
"mov v2.h[7], w20",
"mov v2.h[7], w4",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
unittests/InstructionCountCI/VEX_map3.json
+8 -12
View File
@@ -3296,31 +3296,29 @@
]
},
"vpinsrb xmm0, xmm1, eax, 0": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"nearest rounding",
"Map 3 0b01 0x20 128-bit"
],
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov z2.d, p7/m, z17.d",
"mov v2.b[0], w20",
"mov v2.b[0], w4",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpinsrb xmm0, xmm1, eax, 15": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"nearest rounding",
"Map 3 0b01 0x20 128-bit"
],
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov z2.d, p7/m, z17.d",
"mov v2.b[15], w20",
"mov v2.b[15], w4",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
@@ -3369,31 +3367,29 @@
]
},
"vpinsrd xmm0, xmm1, eax, 0": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"nearest rounding",
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov z2.d, p7/m, z17.d",
"mov v2.s[0], w20",
"mov v2.s[0], w4",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]
},
"vpinsrd xmm0, xmm1, eax, 3": {
"ExpectedInstructionCount": 5,
"ExpectedInstructionCount": 4,
"Optimal": "No",
"Comment": [
"nearest rounding",
"Map 3 0b01 0x22 128-bit"
],
"ExpectedArm64ASM": [
"lsr w20, w4, #0",
"mov z2.d, p7/m, z17.d",
"mov v2.s[3], w20",
"mov v2.s[3], w4",
"mov v2.16b, v2.16b",
"mov z16.d, p7/m, z2.d"
]