From 5e7d793a6a40060e1bf1d656f0dca5325b755085 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Wed, 13 Sep 2023 14:08:40 -0700 Subject: [PATCH 1/2] OpcodeDispatcher: Optimize pins{b,w,d,q} Inserting from a GPR and memory can both be optimized. These are now optimal Needs #3088 merged first. --- .../Core/OpcodeDispatcher/Vector.cpp | 21 +++++++++---------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp index 9d90c46b7..e12330e03 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher/Vector.cpp @@ -1501,20 +1501,19 @@ OrderedNode* OpDispatchBuilder::PINSROpImpl(OpcodeArgs, size_t ElementSize, const X86Tables::DecodedOperand& Imm) { const auto Size = GetDstSize(Op); const auto NumElements = Size / ElementSize; - - OrderedNode *Src2{}; - if (Src2Op.IsGPR()) { - Src2 = LoadSource(GPRClass, Op, Src2Op, Op->Flags, -1); - } else { - // If loading from memory then we only load the element size - Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, ElementSize, Op->Flags, -1); - } - OrderedNode *Src1 = LoadSource_WithOpSize(FPRClass, Op, Src1Op, Size, Op->Flags, -1); - LOGMAN_THROW_A_FMT(Imm.IsLiteral(), "Imm needs to be literal here"); const uint64_t Index = Imm.Data.Literal.Value & (NumElements - 1); + OrderedNode *Src1 = LoadSource_WithOpSize(FPRClass, Op, Src1Op, Size, Op->Flags, -1); - return _VInsGPR(Size, ElementSize, Index, Src1, Src2); + if (Src2Op.IsGPR()) { + // If the source is a GPR then convert directly from the GPR. + auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, CTX->GetGPRSize(), Op->Flags, -1); + return _VInsGPR(Size, ElementSize, Index, Src1, Src2); + } + + // If loading from memory then we only load the element size + auto Src2 = LoadSource_WithOpSize(GPRClass, Op, Src2Op, ElementSize, Op->Flags, -1, false); + return _VLoadVectorElement(Size, ElementSize, Src1, Index, Src2); } template From 2bafa2c26fbb9694dbd186422a2c0a8bab3ac50e Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Wed, 13 Sep 2023 14:09:32 -0700 Subject: [PATCH 2/2] InstCountCI: Update for optimized pins{b,w,d,q} --- unittests/InstructionCountCI/H0F3A.json | 122 ++++++++++++++---- unittests/InstructionCountCI/Secondary.json | 60 ++++----- .../InstructionCountCI/Secondary_OpSize.json | 120 ++++++++++++----- unittests/InstructionCountCI/VEX_map1.json | 15 +-- unittests/InstructionCountCI/VEX_map3.json | 20 ++- 5 files changed, 225 insertions(+), 112 deletions(-) diff --git a/unittests/InstructionCountCI/H0F3A.json b/unittests/InstructionCountCI/H0F3A.json index c97ae2551..8d79da53e 100644 --- a/unittests/InstructionCountCI/H0F3A.json +++ b/unittests/InstructionCountCI/H0F3A.json @@ -724,36 +724,63 @@ ] }, "pinsrb xmm0, eax, 0000b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x20" ], "ExpectedArm64ASM": [ - "uxth w20, w4", - "mov v16.b[0], w20" + "mov v16.b[0], w4" ] }, "pinsrb xmm0, eax, 0001b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x20" ], "ExpectedArm64ASM": [ - "uxth w20, w4", - "mov v16.b[1], w20" + "mov v16.b[1], w4" ] }, "pinsrb xmm0, eax, 1111b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x20" ], "ExpectedArm64ASM": [ - "uxth w20, w4", - "mov v16.b[15], w20" + "mov v16.b[15], w4" + ] + }, + "pinsrb xmm0, [rax], 0000b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "0x66 0x0f 0x3a 0x20" + ], + "ExpectedArm64ASM": [ + "ld1 {v16.b}[0], [x4]" + ] + }, + "pinsrb xmm0, [rax], 0001b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "0x66 0x0f 0x3a 0x20" + ], + "ExpectedArm64ASM": [ + "ld1 {v16.b}[1], [x4]" + ] + }, + "pinsrb xmm0, [rax], 1111b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "0x66 0x0f 0x3a 0x20" + ], + "ExpectedArm64ASM": [ + "ld1 {v16.b}[15], [x4]" ] }, "insertps xmm0, xmm1, 00000000b": { @@ -787,36 +814,33 @@ ] }, "pinsrd xmm0, eax, 00b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x22" ], "ExpectedArm64ASM": [ - "lsr w20, w4, #0", - "mov v16.s[0], w20" + "mov v16.s[0], w4" ] }, "pinsrd xmm0, eax, 01b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x22" ], "ExpectedArm64ASM": [ - "lsr w20, w4, #0", - "mov v16.s[1], w20" + "mov v16.s[1], w4" ] }, "pinsrd xmm0, eax, 11b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": [ "0x66 0x0f 0x3a 0x22" ], "ExpectedArm64ASM": [ - "lsr w20, w4, #0", - "mov v16.s[3], w20" + "mov v16.s[3], w4" ] }, "pinsrq xmm0, rax, 0b": { @@ -839,6 +863,56 @@ "mov v16.d[1], x4" ] }, + "pinsrd xmm0, [rax], 00b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "0x66 0x0f 0x3a 0x22" + ], + "ExpectedArm64ASM": [ + "ld1 {v16.s}[0], [x4]" + ] + }, + "pinsrd xmm0, [rax], 01b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "0x66 0x0f 0x3a 0x22" + ], + "ExpectedArm64ASM": [ + "ld1 {v16.s}[1], [x4]" + ] + }, + "pinsrd xmm0, [rax], 11b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "0x66 0x0f 0x3a 0x22" + ], + "ExpectedArm64ASM": [ + "ld1 {v16.s}[3], [x4]" + ] + }, + "pinsrq xmm0, [rax], 0b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "0x66 REX.W 0x0f 0x3a 0x22" + ], + "ExpectedArm64ASM": [ + "ld1 {v16.d}[0], [x4]" + ] + }, + "pinsrq xmm0, [rax], 1b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": [ + "0x66 REX.W 0x0f 0x3a 0x22" + ], + "ExpectedArm64ASM": [ + "ld1 {v16.d}[1], [x4]" + ] + }, "dpps xmm0, xmm1, 00000000b": { "ExpectedInstructionCount": 1, "Optimal": "Yes", diff --git a/unittests/InstructionCountCI/Secondary.json b/unittests/InstructionCountCI/Secondary.json index aaf59879e..a2bf8af92 100644 --- a/unittests/InstructionCountCI/Secondary.json +++ b/unittests/InstructionCountCI/Secondary.json @@ -3452,112 +3452,102 @@ ] }, "pinsrw mm0, eax, 0": { - "ExpectedInstructionCount": 4, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", "ldr d2, [x28, #752]", - "mov v2.h[0], w20", + "mov v2.h[0], w4", "str d2, [x28, #752]" ] }, "pinsrw mm0, eax, 1": { - "ExpectedInstructionCount": 4, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", "ldr d2, [x28, #752]", - "mov v2.h[1], w20", + "mov v2.h[1], w4", "str d2, [x28, #752]" ] }, "pinsrw mm0, eax, 2": { - "ExpectedInstructionCount": 4, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", "ldr d2, [x28, #752]", - "mov v2.h[2], w20", + "mov v2.h[2], w4", "str d2, [x28, #752]" ] }, "pinsrw mm0, eax, 3": { - "ExpectedInstructionCount": 4, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", "ldr d2, [x28, #752]", - "mov v2.h[3], w20", + "mov v2.h[3], w4", "str d2, [x28, #752]" ] }, "pinsrw mm0, eax, 4": { - "ExpectedInstructionCount": 4, - "Optimal": "No", + "ExpectedInstructionCount": 3, + "Optimal": "Yes", "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", "ldr d2, [x28, #752]", - "mov v2.h[0], w20", + "mov v2.h[0], w4", "str d2, [x28, #752]" ] }, "pinsrw mm0, [rax], 0": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldrh w20, [x4]", "ldr d2, [x28, #752]", - "mov v2.h[0], w20", + "ld1 {v2.h}[0], [x4]", "str d2, [x28, #752]" ] }, "pinsrw mm0, [rax], 1": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldrh w20, [x4]", "ldr d2, [x28, #752]", - "mov v2.h[1], w20", + "ld1 {v2.h}[1], [x4]", "str d2, [x28, #752]" ] }, "pinsrw mm0, [rax], 2": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldrh w20, [x4]", "ldr d2, [x28, #752]", - "mov v2.h[2], w20", + "ld1 {v2.h}[2], [x4]", "str d2, [x28, #752]" ] }, "pinsrw mm0, [rax], 3": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldrh w20, [x4]", "ldr d2, [x28, #752]", - "mov v2.h[3], w20", + "ld1 {v2.h}[3], [x4]", "str d2, [x28, #752]" ] }, "pinsrw mm0, [rax], 4": { - "ExpectedInstructionCount": 4, + "ExpectedInstructionCount": 3, "Optimal": "No", "Comment": "0x0f 0xc4", "ExpectedArm64ASM": [ - "ldrh w20, [x4]", "ldr d2, [x28, #752]", - "mov v2.h[0], w20", + "ld1 {v2.h}[0], [x4]", "str d2, [x28, #752]" ] }, diff --git a/unittests/InstructionCountCI/Secondary_OpSize.json b/unittests/InstructionCountCI/Secondary_OpSize.json index cb6373d36..8d8606d50 100644 --- a/unittests/InstructionCountCI/Secondary_OpSize.json +++ b/unittests/InstructionCountCI/Secondary_OpSize.json @@ -810,75 +810,131 @@ ] }, "pinsrw xmm0, eax, 000b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": "0x66 0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", - "mov v16.h[0], w20" + "mov v16.h[0], w4" ] }, "pinsrw xmm0, eax, 001b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": "0x66 0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", - "mov v16.h[1], w20" + "mov v16.h[1], w4" ] }, "pinsrw xmm0, eax, 010b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": "0x66 0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", - "mov v16.h[2], w20" + "mov v16.h[2], w4" ] }, "pinsrw xmm0, eax, 011b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": "0x66 0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", - "mov v16.h[3], w20" + "mov v16.h[3], w4" ] }, "pinsrw xmm0, eax, 100b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": "0x66 0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", - "mov v16.h[4], w20" + "mov v16.h[4], w4" ] }, "pinsrw xmm0, eax, 101b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": "0x66 0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", - "mov v16.h[5], w20" + "mov v16.h[5], w4" ] }, "pinsrw xmm0, eax, 110b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": "0x66 0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", - "mov v16.h[6], w20" + "mov v16.h[6], w4" ] }, "pinsrw xmm0, eax, 111b": { - "ExpectedInstructionCount": 2, - "Optimal": "No", + "ExpectedInstructionCount": 1, + "Optimal": "Yes", "Comment": "0x66 0x0f 0xc4", "ExpectedArm64ASM": [ - "uxth w20, w4", - "mov v16.h[7], w20" + "mov v16.h[7], w4" + ] + }, + "pinsrw xmm0, [rax], 000b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "0x66 0x0f 0xc4", + "ExpectedArm64ASM": [ + "ld1 {v16.h}[0], [x4]" + ] + }, + "pinsrw xmm0, [rax], 001b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "0x66 0x0f 0xc4", + "ExpectedArm64ASM": [ + "ld1 {v16.h}[1], [x4]" + ] + }, + "pinsrw xmm0, [rax], 010b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "0x66 0x0f 0xc4", + "ExpectedArm64ASM": [ + "ld1 {v16.h}[2], [x4]" + ] + }, + "pinsrw xmm0, [rax], 011b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "0x66 0x0f 0xc4", + "ExpectedArm64ASM": [ + "ld1 {v16.h}[3], [x4]" + ] + }, + "pinsrw xmm0, [rax], 100b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "0x66 0x0f 0xc4", + "ExpectedArm64ASM": [ + "ld1 {v16.h}[4], [x4]" + ] + }, + "pinsrw xmm0, [rax], 101b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "0x66 0x0f 0xc4", + "ExpectedArm64ASM": [ + "ld1 {v16.h}[5], [x4]" + ] + }, + "pinsrw xmm0, [rax], 110b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "0x66 0x0f 0xc4", + "ExpectedArm64ASM": [ + "ld1 {v16.h}[6], [x4]" + ] + }, + "pinsrw xmm0, [rax], 111b": { + "ExpectedInstructionCount": 1, + "Optimal": "Yes", + "Comment": "0x66 0x0f 0xc4", + "ExpectedArm64ASM": [ + "ld1 {v16.h}[7], [x4]" ] }, "pextrw eax, xmm0, 000b": { diff --git a/unittests/InstructionCountCI/VEX_map1.json b/unittests/InstructionCountCI/VEX_map1.json index a668a252d..bb8fab4e7 100644 --- a/unittests/InstructionCountCI/VEX_map1.json +++ b/unittests/InstructionCountCI/VEX_map1.json @@ -3067,43 +3067,40 @@ ] }, "vpinsrw xmm0, xmm1, eax, 000b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "Map 1 0b01 0xC4 128-bit" ], "ExpectedArm64ASM": [ - "uxth w20, w4", "mov z2.d, p7/m, z17.d", - "mov v2.h[0], w20", + "mov v2.h[0], w4", "mov v2.16b, v2.16b", "mov z16.d, p7/m, z2.d" ] }, "vpinsrw xmm0, xmm1, eax, 001b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "Map 1 0b01 0xC4 128-bit" ], "ExpectedArm64ASM": [ - "uxth w20, w4", "mov z2.d, p7/m, z17.d", - "mov v2.h[1], w20", + "mov v2.h[1], w4", "mov v2.16b, v2.16b", "mov z16.d, p7/m, z2.d" ] }, "vpinsrw xmm0, xmm1, eax, 111b": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "Map 1 0b01 0xC4 128-bit" ], "ExpectedArm64ASM": [ - "uxth w20, w4", "mov z2.d, p7/m, z17.d", - "mov v2.h[7], w20", + "mov v2.h[7], w4", "mov v2.16b, v2.16b", "mov z16.d, p7/m, z2.d" ] diff --git a/unittests/InstructionCountCI/VEX_map3.json b/unittests/InstructionCountCI/VEX_map3.json index 3bb36d0f2..8ea86f624 100644 --- a/unittests/InstructionCountCI/VEX_map3.json +++ b/unittests/InstructionCountCI/VEX_map3.json @@ -3234,31 +3234,29 @@ ] }, "vpinsrb xmm0, xmm1, eax, 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "nearest rounding", "Map 3 0b01 0x20 128-bit" ], "ExpectedArm64ASM": [ - "lsr w20, w4, #0", "mov z2.d, p7/m, z17.d", - "mov v2.b[0], w20", + "mov v2.b[0], w4", "mov v2.16b, v2.16b", "mov z16.d, p7/m, z2.d" ] }, "vpinsrb xmm0, xmm1, eax, 15": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "nearest rounding", "Map 3 0b01 0x20 128-bit" ], "ExpectedArm64ASM": [ - "lsr w20, w4, #0", "mov z2.d, p7/m, z17.d", - "mov v2.b[15], w20", + "mov v2.b[15], w4", "mov v2.16b, v2.16b", "mov z16.d, p7/m, z2.d" ] @@ -3307,31 +3305,29 @@ ] }, "vpinsrd xmm0, xmm1, eax, 0": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "nearest rounding", "Map 3 0b01 0x22 128-bit" ], "ExpectedArm64ASM": [ - "lsr w20, w4, #0", "mov z2.d, p7/m, z17.d", - "mov v2.s[0], w20", + "mov v2.s[0], w4", "mov v2.16b, v2.16b", "mov z16.d, p7/m, z2.d" ] }, "vpinsrd xmm0, xmm1, eax, 3": { - "ExpectedInstructionCount": 5, + "ExpectedInstructionCount": 4, "Optimal": "No", "Comment": [ "nearest rounding", "Map 3 0b01 0x22 128-bit" ], "ExpectedArm64ASM": [ - "lsr w20, w4, #0", "mov z2.d, p7/m, z17.d", - "mov v2.s[3], w20", + "mov v2.s[3], w4", "mov v2.16b, v2.16b", "mov z16.d, p7/m, z2.d" ]