OpcodeDispatcher: Optimize lock btr

This is an atomicFetchCLR, removes two mvn instructions that are back to
back negating the source.

We didn't have this instruction combination in InstCountCI so will be a
bit hard to see.

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -3084,10 +3084,8 @@ void OpDispatchBuilder::BTROp(OpcodeArgs) {
 
     if (DestIsLockedMem(Op)) {
       HandledLock = true;
-      BitMask = _Not(OpSize::i64Bit, BitMask);
-      // XXX: Technically this can optimize to an AArch64 ldclralb
       // We don't current support this IR op though
-      Result = _AtomicFetchAnd(OpSize::i8Bit, BitMask, MemoryLocation);
+      Result = _AtomicFetchCLR(OpSize::i8Bit, BitMask, MemoryLocation);
       // Now shift in to the correct bit location
       Result = _Lshr(IR::SizeToOpSize(std::max<uint8_t>(4u, GetOpSize(Result))), Result, BitSelect);
     } else {