From 1a4d1d820bd293f5820db6143c6cd12cdabae4b7 Mon Sep 17 00:00:00 2001 From: Ryan Houdek Date: Thu, 21 Sep 2023 02:47:30 -0700 Subject: [PATCH] OpcodeDispatcher: Optimize lock btr This is an atomicFetchCLR, removes two mvn instructions that are back to back negating the source. We didn't have this instruction combination in InstCountCI so will be a bit hard to see. --- FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp index b86df9635..a5b5c945d 100644 --- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp +++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp @@ -3084,10 +3084,8 @@ void OpDispatchBuilder::BTROp(OpcodeArgs) { if (DestIsLockedMem(Op)) { HandledLock = true; - BitMask = _Not(OpSize::i64Bit, BitMask); - // XXX: Technically this can optimize to an AArch64 ldclralb // We don't current support this IR op though - Result = _AtomicFetchAnd(OpSize::i8Bit, BitMask, MemoryLocation); + Result = _AtomicFetchCLR(OpSize::i8Bit, BitMask, MemoryLocation); // Now shift in to the correct bit location Result = _Lshr(IR::SizeToOpSize(std::max(4u, GetOpSize(Result))), Result, BitSelect); } else {