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IR: reduce memcpy worstcase reg pressure

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This avoids a bunch of sharp edges for RA at a small cost when obscure
segment registers are used.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
This commit is contained in:
Alyssa Rosenzweig committed 2024-05-21 16:54:06 -04:00
1 parent 85776c2537
commit 1a467f0ebd
3 files changed
+22 -18
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FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+17 -2
View File
@@ -3305,12 +3305,27 @@ void OpDispatchBuilder::MOVSOp(OpcodeArgs) {
auto DstSegment = GetSegment(0, FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX, true);
auto SrcSegment = GetSegment(Op->Flags, FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX);
auto Result =
_MemCpy(CTX->IsAtomicTSOEnabled(), Size, DstSegment ?: InvalidNode, SrcSegment ?: InvalidNode, DstAddr, SrcAddr, Counter, LoadDir(1));
if (DstSegment) {
DstAddr = _Add(OpSize::i64Bit, DstAddr, DstSegment);
}
if (SrcSegment) {
SrcAddr = _Add(OpSize::i64Bit, SrcAddr, SrcSegment);
}
auto Result = _MemCpy(CTX->IsAtomicTSOEnabled(), Size, DstAddr, SrcAddr, Counter, LoadDir(1));
OrderedNode* Result_Dst = _ExtractElementPair(OpSize::i64Bit, Result, 0);
OrderedNode* Result_Src = _ExtractElementPair(OpSize::i64Bit, Result, 1);
if (DstSegment) {
Result_Dst = _Sub(OpSize::i64Bit, Result_Dst, DstSegment);
}
if (SrcSegment) {
Result_Src = _Sub(OpSize::i64Bit, Result_Src, SrcSegment);
}
StoreGPRRegister(X86State::REG_RCX, _Constant(0));
StoreGPRRegister(X86State::REG_RDI, Result_Dst);
StoreGPRRegister(X86State::REG_RSI, Result_Src);