diff --git a/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp b/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp
index 0928f1e00..03cfe7f6e 100644
--- a/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp
+++ b/FEXCore/Source/Interface/Core/JIT/Arm64/MemoryOps.cpp
@@ -1346,8 +1346,8 @@ DEF_OP(MemCpy) {
 
   const bool IsAtomic = Op->IsAtomic && MemcpySetTSOEnabled();
   const int32_t Size = Op->Size;
-  const auto MemRegDest = GetReg(Op->AddrDest.ID());
-  const auto MemRegSrc = GetReg(Op->AddrSrc.ID());
+  const auto MemRegDest = GetReg(Op->Dest.ID());
+  const auto MemRegSrc = GetReg(Op->Src.ID());
 
   const auto Length = GetReg(Op->Length.ID());
   uint64_t DirectionConstant;
@@ -1371,19 +1371,8 @@ DEF_OP(MemCpy) {
   ARMEmitter::SingleUseForwardLabel Done {};
 
   mov(TMP1, Length.X());
-  if (Op->PrefixDest.IsInvalid()) {
-    mov(TMP2, MemRegDest.X());
-  } else {
-    const auto Prefix = GetReg(Op->PrefixDest.ID());
-    add(TMP2, Prefix.X(), MemRegDest.X());
-  }
-
-  if (Op->PrefixSrc.IsInvalid()) {
-    mov(TMP3, MemRegSrc.X());
-  } else {
-    const auto Prefix = GetReg(Op->PrefixSrc.ID());
-    add(TMP3, Prefix.X(), MemRegSrc.X());
-  }
+  mov(TMP2, MemRegDest.X());
+  mov(TMP3, MemRegSrc.X());
 
   // TMP1 = Length
   // TMP2 = Dest
diff --git a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
index aa1fea1c9..a467bb22f 100644
--- a/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
+++ b/FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp
@@ -3305,12 +3305,27 @@ void OpDispatchBuilder::MOVSOp(OpcodeArgs) {
     auto DstSegment = GetSegment(0, FEXCore::X86Tables::DecodeFlags::FLAG_ES_PREFIX, true);
     auto SrcSegment = GetSegment(Op->Flags, FEXCore::X86Tables::DecodeFlags::FLAG_DS_PREFIX);
 
-    auto Result =
-      _MemCpy(CTX->IsAtomicTSOEnabled(), Size, DstSegment ?: InvalidNode, SrcSegment ?: InvalidNode, DstAddr, SrcAddr, Counter, LoadDir(1));
+    if (DstSegment) {
+      DstAddr = _Add(OpSize::i64Bit, DstAddr, DstSegment);
+    }
+
+    if (SrcSegment) {
+      SrcAddr = _Add(OpSize::i64Bit, SrcAddr, SrcSegment);
+    }
+
+    auto Result = _MemCpy(CTX->IsAtomicTSOEnabled(), Size, DstAddr, SrcAddr, Counter, LoadDir(1));
 
     OrderedNode* Result_Dst = _ExtractElementPair(OpSize::i64Bit, Result, 0);
     OrderedNode* Result_Src = _ExtractElementPair(OpSize::i64Bit, Result, 1);
 
+    if (DstSegment) {
+      Result_Dst = _Sub(OpSize::i64Bit, Result_Dst, DstSegment);
+    }
+
+    if (SrcSegment) {
+      Result_Src = _Sub(OpSize::i64Bit, Result_Src, SrcSegment);
+    }
+
     StoreGPRRegister(X86State::REG_RCX, _Constant(0));
     StoreGPRRegister(X86State::REG_RDI, Result_Dst);
     StoreGPRRegister(X86State::REG_RSI, Result_Src);
diff --git a/FEXCore/Source/Interface/IR/IR.json b/FEXCore/Source/Interface/IR/IR.json
index 03545b347..824355d94 100644
--- a/FEXCore/Source/Interface/IR/IR.json
+++ b/FEXCore/Source/Interface/IR/IR.json
@@ -561,7 +561,7 @@
         "HasSideEffects": true,
         "DestSize": "8"
       },
-      "GPRPair = MemCpy i1:$IsAtomic, u8:$Size, GPR:$PrefixDest, GPR:$PrefixSrc, GPR:$AddrDest, GPR:$AddrSrc, GPR:$Length, GPR:$Direction": {
+      "GPRPair = MemCpy i1:$IsAtomic, u8:$Size, GPR:$Dest, GPR:$Src, GPR:$Length, GPR:$Direction": {
         "Desc": ["Duplicates behaviour of x86 MOVS repeat",
                  "Returns the final addresses of destination and src addresses after they have been incremented or decremented"
                 ],