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InstcountCI: Update for changed codegen.
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@@ -1857,15 +1857,14 @@
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]
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},
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"imul eax, ebx, 257": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 7,
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"Comment": "0x69",
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"ExpectedArm64ASM": [
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"sxtw x20, w7",
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"mov w21, #0x101",
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"mul x20, x20, x21",
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"asr x21, x20, #32",
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"mov w4, w20",
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"sbfx x20, x20, #31, #1",
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"mov w20, #0x101",
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"mul x21, x7, x20",
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"asr x21, x21, #32",
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"mul w4, w7, w20",
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"sbfx x20, x4, #31, #1",
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"cmp x21, x20",
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"ccmn xzr, #0, #nzCV, eq"
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]
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@@ -1875,10 +1874,10 @@
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"Comment": "0x69",
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"ExpectedArm64ASM": [
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"mov w20, #0x101",
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"smulh x21, x7, x20",
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"mul x4, x7, x20",
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"smulh x20, x7, x20",
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"asr x21, x4, #63",
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"cmp x20, x21",
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"asr x20, x4, #63",
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"cmp x21, x20",
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"ccmn xzr, #0, #nzCV, eq"
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]
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},
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@@ -1897,15 +1896,14 @@
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]
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},
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"imul eax, ebx, 3": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 7,
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"Comment": "0x6b",
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"ExpectedArm64ASM": [
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"sxtw x20, w7",
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"mov w21, #0x3",
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"mul x20, x20, x21",
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"asr x21, x20, #32",
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"mov w4, w20",
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"sbfx x20, x20, #31, #1",
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"mov w20, #0x3",
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"mul x21, x7, x20",
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"asr x21, x21, #32",
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"mul w4, w7, w20",
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"sbfx x20, x4, #31, #1",
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"cmp x21, x20",
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"ccmn xzr, #0, #nzCV, eq"
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]
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@@ -1915,10 +1913,10 @@
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"Comment": "0x6b",
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"ExpectedArm64ASM": [
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"mov w20, #0x3",
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"smulh x21, x7, x20",
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"mul x4, x7, x20",
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"smulh x20, x7, x20",
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"asr x21, x4, #63",
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"cmp x20, x21",
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"asr x20, x4, #63",
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"cmp x21, x20",
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"ccmn xzr, #0, #nzCV, eq"
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]
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},
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@@ -1033,16 +1033,14 @@
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]
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},
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"imul eax, ebx": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 6,
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"Comment": "0x0f 0xaf",
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"ExpectedArm64ASM": [
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"sxtw x20, w4",
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"sxtw x21, w7",
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"mul x20, x20, x21",
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"asr x21, x20, #32",
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"mov w4, w20",
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"sbfx x20, x20, #31, #1",
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"cmp x21, x20",
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"mul x20, x4, x7",
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"asr x20, x20, #32",
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"mul w4, w4, w7",
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"sbfx x21, x4, #31, #1",
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"cmp x20, x21",
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"ccmn xzr, #0, #nzCV, eq"
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]
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},
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@@ -2087,15 +2087,14 @@
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]
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},
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"imul eax, ebx, 257": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 7,
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"Comment": "0x69",
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"ExpectedArm64ASM": [
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"sxtw x20, w7",
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"mov w21, #0x101",
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"mul x20, x20, x21",
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"asr x21, x20, #32",
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"mov w4, w20",
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"sbfx x20, x20, #31, #1",
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"mov w20, #0x101",
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"mul x21, x7, x20",
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"asr x21, x21, #32",
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"mul w4, w7, w20",
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"sbfx x20, x4, #31, #1",
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"cmp x21, x20",
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"ccmn xzr, #0, #nzCV, eq"
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]
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@@ -2105,10 +2104,10 @@
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"Comment": "0x69",
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"ExpectedArm64ASM": [
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"mov w20, #0x101",
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"smulh x21, x7, x20",
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"mul x4, x7, x20",
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"smulh x20, x7, x20",
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"asr x21, x4, #63",
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"cmp x20, x21",
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"asr x20, x4, #63",
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"cmp x21, x20",
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"ccmn xzr, #0, #nzCV, eq"
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]
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},
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@@ -2151,15 +2150,14 @@
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]
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},
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"imul eax, ebx, 3": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 7,
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"Comment": "0x6b",
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"ExpectedArm64ASM": [
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"sxtw x20, w7",
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"mov w21, #0x3",
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"mul x20, x20, x21",
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"asr x21, x20, #32",
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"mov w4, w20",
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"sbfx x20, x20, #31, #1",
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"mov w20, #0x3",
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"mul x21, x7, x20",
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"asr x21, x21, #32",
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"mul w4, w7, w20",
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"sbfx x20, x4, #31, #1",
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"cmp x21, x20",
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"ccmn xzr, #0, #nzCV, eq"
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]
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@@ -2169,10 +2167,10 @@
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"Comment": "0x6b",
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"ExpectedArm64ASM": [
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"mov w20, #0x3",
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"smulh x21, x7, x20",
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"mul x4, x7, x20",
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"smulh x20, x7, x20",
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"asr x21, x4, #63",
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"cmp x20, x21",
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"asr x20, x4, #63",
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"cmp x21, x20",
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"ccmn xzr, #0, #nzCV, eq"
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]
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},
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@@ -1879,16 +1879,14 @@
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]
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},
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"imul eax, ebx": {
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"ExpectedInstructionCount": 8,
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"ExpectedInstructionCount": 6,
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"Comment": "0x0f 0xaf",
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"ExpectedArm64ASM": [
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"sxtw x20, w4",
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"sxtw x21, w7",
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"mul x20, x20, x21",
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"asr x21, x20, #32",
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"mov w4, w20",
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"sbfx x20, x20, #31, #1",
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"cmp x21, x20",
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"mul x20, x4, x7",
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"asr x20, x20, #32",
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"mul w4, w4, w7",
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"sbfx x21, x4, #31, #1",
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"cmp x20, x21",
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"ccmn xzr, #0, #nzCV, eq"
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]
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},
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