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InstCountCI: Update
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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@@ -153,7 +153,7 @@
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},
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"signed div narrow": {
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"x86InstructionCount": 2,
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"ExpectedInstructionCount": 31,
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"ExpectedInstructionCount": 29,
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"Comment": [
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"div narrowing with known smaller sources",
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"dividend in rdx:rax"
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@@ -163,9 +163,7 @@
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"idiv rcx"
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],
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"ExpectedArm64ASM": [
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"mov w20, w4",
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"sbfx x20, x20, #31, #1",
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"mov w5, w20",
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"asr w5, w4, #31",
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"asr x0, x4, #63",
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"eor x0, x0, x5",
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"cbz x0, #+0x28",
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@@ -2598,21 +2598,18 @@
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]
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},
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"cwd": {
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"ExpectedInstructionCount": 3,
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"ExpectedInstructionCount": 2,
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"Comment": "0x98",
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"ExpectedArm64ASM": [
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"uxth w20, w4",
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"sbfx x20, x20, #15, #1",
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"sbfx w20, w4, #15, #1",
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"bfxil x5, x20, #0, #16"
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]
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},
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"cdq": {
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"ExpectedInstructionCount": 3,
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"ExpectedInstructionCount": 1,
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"Comment": "0x99",
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"ExpectedArm64ASM": [
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"mov w20, w4",
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"sbfx x20, x20, #31, #1",
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"mov w5, w20"
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"asr w5, w4, #31"
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]
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},
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"cqo": {
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