FEXCore: Fixes 16-bit operand size Leave

Weren't testing this edge case just like enter

FEXCore/Source/Interface/Core/OpcodeDispatcher.cpp

@@ -498,15 +498,18 @@ void OpDispatchBuilder::POPSegmentOp(OpcodeArgs, uint32_t SegmentReg) {
 }
 
 void OpDispatchBuilder::LEAVEOp(OpcodeArgs) {
+  const auto GPRSize = GetGPROpSize();
+  const auto OperandSize = (Op->Flags & FEXCore::X86Tables::DecodeFlags::FLAG_OPERAND_SIZE) ? OpSize::i16Bit : GPRSize;
+
   // First we move RBP in to RSP and then behave effectively like a pop
   auto SP = _RMWHandle(LoadGPRRegister(X86State::REG_RBP));
-  auto NewGPR = Pop(OpSizeFromSrc(Op), SP);
+  auto NewGPR = Pop(OperandSize, SP);
 
   // Store the new stack pointer
-  StoreGPRRegister(X86State::REG_RSP, SP);
+  StoreGPRRegister(X86State::REG_RSP, SP, OperandSize);
 
   // Store what we loaded to RBP
-  StoreGPRRegister(X86State::REG_RBP, NewGPR);
+  StoreGPRRegister(X86State::REG_RBP, NewGPR, OperandSize);
 }
 
 void OpDispatchBuilder::CALLOp(OpcodeArgs) {

unittests/ASM/Primary/Primary_C9_o16.asm

@@ -0,0 +1,26 @@
+%ifdef CONFIG
+{
+  "RegData": {
+    "RAX": "0x1",
+    "RBP": "0xe0004748",
+    "RSP": "0xe0000020"
+  }
+}
+%endif
+
+mov rsp, 0xe0000020
+mov rbp, 0x4142434445464748
+
+; Act like an ENTER frame without using ENTER
+sub rsp, 2
+mov [rsp], bp
+mov rbp, rsp
+call .target
+jmp .end
+
+.target:
+mov rax, 1
+o16 leave
+
+.end:
+hlt