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Merge pull request #4231 from Sonicadvance1/minor_div_opt
OpcodeDispatcher: Minor division improvement
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3 files changed
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-62
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@@ -3613,16 +3613,16 @@ void OpDispatchBuilder::DIVOp(OpcodeArgs) {
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auto ResultAX = _Bfi(GPRSize, 8, 8, UDivOp, URemOp);
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StoreGPRRegister(X86State::REG_RAX, ResultAX, OpSize::i16Bit);
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} else if (Size == OpSize::i16Bit) {
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Ref Src1 = LoadGPRRegister(X86State::REG_RAX, Size);
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Ref Src2 = LoadGPRRegister(X86State::REG_RDX, Size);
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Ref Src1 = LoadGPRRegister(X86State::REG_RAX);
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Ref Src2 = LoadGPRRegister(X86State::REG_RDX);
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auto UDivOp = _LUDiv(OpSize::i16Bit, Src1, Src2, Divisor);
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auto URemOp = _LURem(OpSize::i16Bit, Src1, Src2, Divisor);
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StoreGPRRegister(X86State::REG_RAX, UDivOp, Size);
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StoreGPRRegister(X86State::REG_RDX, URemOp, Size);
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} else if (Size == OpSize::i32Bit) {
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Ref Src1 = LoadGPRRegister(X86State::REG_RAX, Size);
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Ref Src2 = LoadGPRRegister(X86State::REG_RDX, Size);
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Ref Src1 = LoadGPRRegister(X86State::REG_RAX);
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Ref Src2 = LoadGPRRegister(X86State::REG_RDX);
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Ref UDivOp = _Bfe(OpSize::i32Bit, IR::OpSizeAsBits(Size), 0, _LUDiv(OpSize::i32Bit, Src1, Src2, Divisor));
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Ref URemOp = _Bfe(OpSize::i32Bit, IR::OpSizeAsBits(Size), 0, _LURem(OpSize::i32Bit, Src1, Src2, Divisor));
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@@ -3654,7 +3654,7 @@ void OpDispatchBuilder::IDIVOp(OpcodeArgs) {
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const auto Size = OpSizeFromSrc(Op);
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if (Size == OpSize::i8Bit) {
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Ref Src1 = LoadGPRRegister(X86State::REG_RAX, OpSize::i16Bit);
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Ref Src1 = LoadGPRRegister(X86State::REG_RAX);
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Src1 = _Sbfe(OpSize::i64Bit, 16, 0, Src1);
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Divisor = _Sbfe(OpSize::i64Bit, 8, 0, Divisor);
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@@ -3665,16 +3665,16 @@ void OpDispatchBuilder::IDIVOp(OpcodeArgs) {
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auto ResultAX = _Bfi(GPRSize, 8, 8, UDivOp, URemOp);
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StoreGPRRegister(X86State::REG_RAX, ResultAX, OpSize::i16Bit);
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} else if (Size == OpSize::i16Bit) {
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Ref Src1 = LoadGPRRegister(X86State::REG_RAX, Size);
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Ref Src2 = LoadGPRRegister(X86State::REG_RDX, Size);
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Ref Src1 = LoadGPRRegister(X86State::REG_RAX);
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Ref Src2 = LoadGPRRegister(X86State::REG_RDX);
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auto UDivOp = _LDiv(OpSize::i16Bit, Src1, Src2, Divisor);
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auto URemOp = _LRem(OpSize::i16Bit, Src1, Src2, Divisor);
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StoreGPRRegister(X86State::REG_RAX, UDivOp, Size);
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StoreGPRRegister(X86State::REG_RDX, URemOp, Size);
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} else if (Size == OpSize::i32Bit) {
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Ref Src1 = LoadGPRRegister(X86State::REG_RAX, Size);
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Ref Src2 = LoadGPRRegister(X86State::REG_RDX, Size);
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Ref Src1 = LoadGPRRegister(X86State::REG_RAX);
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Ref Src2 = LoadGPRRegister(X86State::REG_RDX);
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Ref UDivOp = _Bfe(OpSize::i32Bit, IR::OpSizeAsBits(Size), 0, _LDiv(OpSize::i32Bit, Src1, Src2, Divisor));
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Ref URemOp = _Bfe(OpSize::i32Bit, IR::OpSizeAsBits(Size), 0, _LRem(OpSize::i32Bit, Src1, Src2, Divisor));
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@@ -2196,12 +2196,11 @@
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]
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},
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"idiv bl": {
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"ExpectedInstructionCount": 9,
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"ExpectedInstructionCount": 8,
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"Comment": "GROUP2 0xf6 /7",
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"ExpectedArm64ASM": [
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"uxtb w20, w6",
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"uxth w21, w4",
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"sxth x21, w21",
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"sxth x21, w4",
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"sxtb x20, w20",
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"sdiv x22, x21, x20",
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"sdiv x0, x21, x20",
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@@ -2367,20 +2366,18 @@
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]
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},
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"div bx": {
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"ExpectedInstructionCount": 12,
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"ExpectedInstructionCount": 10,
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"Comment": "GROUP2 0xf7 /6",
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"ExpectedArm64ASM": [
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"uxth w20, w6",
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"uxth w21, w4",
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"uxth w22, w5",
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"uxth w0, w21",
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"bfi w0, w22, #16, #16",
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"udiv w23, w0, w20",
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"uxth w0, w21",
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"bfi w0, w22, #16, #16",
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"uxth w0, w4",
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"bfi w0, w5, #16, #16",
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"udiv w21, w0, w20",
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"uxth w0, w4",
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"bfi w0, w5, #16, #16",
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"udiv w1, w0, w20",
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"msub w20, w1, w20, w0",
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"bfxil x4, x23, #0, #16",
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"bfxil x4, x21, #0, #16",
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"bfxil x5, x20, #0, #16"
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]
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},
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@@ -2588,12 +2588,11 @@
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]
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},
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"idiv bl": {
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"ExpectedInstructionCount": 9,
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"ExpectedInstructionCount": 8,
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"Comment": "GROUP2 0xf6 /7",
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"ExpectedArm64ASM": [
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"uxtb w20, w6",
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"uxth w21, w4",
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"sxth x21, w21",
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"sxth x21, w4",
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"sxtb x20, w20",
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"sdiv x22, x21, x20",
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"sdiv x0, x21, x20",
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@@ -2786,39 +2785,36 @@
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]
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},
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"div bx": {
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"ExpectedInstructionCount": 12,
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"ExpectedInstructionCount": 10,
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"Comment": "GROUP2 0xf7 /6",
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"ExpectedArm64ASM": [
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"uxth w20, w6",
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"uxth w21, w4",
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"uxth w22, w5",
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"uxth w0, w21",
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"bfi w0, w22, #16, #16",
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"udiv w23, w0, w20",
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"uxth w0, w21",
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"bfi w0, w22, #16, #16",
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"uxth w0, w4",
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"bfi w0, w5, #16, #16",
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"udiv w21, w0, w20",
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"uxth w0, w4",
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"bfi w0, w5, #16, #16",
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"udiv w1, w0, w20",
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"msub w20, w1, w20, w0",
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"bfxil x4, x23, #0, #16",
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"bfxil x4, x21, #0, #16",
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"bfxil x5, x20, #0, #16"
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]
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},
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"div ebx": {
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"ExpectedInstructionCount": 12,
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"ExpectedInstructionCount": 11,
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"Comment": "GROUP2 0xf7 /6",
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"ExpectedArm64ASM": [
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"mov w20, w6",
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"mov w21, w4",
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"mov w22, w5",
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"mov x0, x21",
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"bfi x0, x22, #32, #32",
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"udiv x23, x0, x20",
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"mov w4, w23",
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"mov x0, x21",
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"bfi x0, x22, #32, #32",
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"mov x0, x4",
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"bfi x0, x5, #32, #32",
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"udiv x21, x0, x20",
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"mov w21, w21",
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"mov x0, x4",
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"bfi x0, x5, #32, #32",
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"udiv x1, x0, x20",
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"msub x20, x1, x20, x0",
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"mov w5, w20"
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"mov w5, w20",
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"mov x4, x21"
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]
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},
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"div rbx": {
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@@ -2852,43 +2848,40 @@
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]
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},
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"idiv bx": {
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"ExpectedInstructionCount": 14,
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"ExpectedInstructionCount": 12,
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"Comment": "GROUP2 0xf7 /7",
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"ExpectedArm64ASM": [
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"uxth w20, w6",
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"uxth w21, w4",
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"uxth w22, w5",
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"uxth w0, w21",
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"bfi w0, w22, #16, #16",
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"uxth w0, w4",
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"bfi w0, w5, #16, #16",
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"sxth w1, w20",
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"sdiv w23, w0, w1",
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"uxth w0, w21",
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"bfi w0, w22, #16, #16",
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"sdiv w21, w0, w1",
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"uxth w0, w4",
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"bfi w0, w5, #16, #16",
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"sxth w1, w20",
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"sdiv w2, w0, w1",
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"msub w20, w2, w1, w0",
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"bfxil x4, x23, #0, #16",
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"bfxil x4, x21, #0, #16",
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"bfxil x5, x20, #0, #16"
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]
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},
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"idiv ebx": {
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"ExpectedInstructionCount": 14,
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"ExpectedInstructionCount": 13,
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"Comment": "GROUP2 0xf7 /7",
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"ExpectedArm64ASM": [
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"mov w20, w6",
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"mov w21, w4",
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"mov w22, w5",
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"mov x0, x21",
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"bfi x0, x22, #32, #32",
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"mov x0, x4",
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"bfi x0, x5, #32, #32",
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"sxtw x1, w20",
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"sdiv x23, x0, x1",
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"mov w4, w23",
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"mov x0, x21",
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"bfi x0, x22, #32, #32",
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"sdiv x21, x0, x1",
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"mov w21, w21",
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"mov x0, x4",
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"bfi x0, x5, #32, #32",
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"sxtw x2, w20",
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"sdiv x1, x0, x2",
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"msub x20, x1, x2, x0",
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"mov w5, w20"
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"mov w5, w20",
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"mov x4, x21"
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]
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},
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"idiv rbx": {
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