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lioncash
5f9052a675
In the event that the host doesn't support the requirements for running AVX-enabled applications (SVE2 with at least 256-bit wide vectors) but still wanted to run regular SSE-enabled applications, they would be taking a performance hit due to a load/store pessimization (necessary in order for 256-bit loads/stores to work) However, we can add an alternate view into the xmm data that would allow those hosts to use the previous optimization, while still supporting AVX-capable hosts.
35 lines
1.5 KiB
C++
35 lines
1.5 KiB
C++
#pragma once
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#include <memory>
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namespace FEXCore::Utils {
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class IntrusivePooledAllocator;
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}
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namespace FEXCore::IR {
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class Pass;
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class RegisterAllocationPass;
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class RegisterAllocationData;
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std::unique_ptr<FEXCore::IR::Pass> CreateConstProp(bool InlineConstants, bool SupportsTSOImm9);
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std::unique_ptr<FEXCore::IR::Pass> CreateContextLoadStoreElimination(bool SupportsAVX);
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std::unique_ptr<FEXCore::IR::Pass> CreateSyscallOptimization();
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std::unique_ptr<FEXCore::IR::Pass> CreateDeadFlagCalculationEliminination();
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std::unique_ptr<FEXCore::IR::Pass> CreateDeadStoreElimination(bool SupportsAVX);
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std::unique_ptr<FEXCore::IR::Pass> CreatePassDeadCodeElimination();
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std::unique_ptr<FEXCore::IR::Pass> CreateIRCompaction(FEXCore::Utils::IntrusivePooledAllocator &Allocator);
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std::unique_ptr<FEXCore::IR::RegisterAllocationPass> CreateRegisterAllocationPass(FEXCore::IR::Pass* CompactionPass,
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bool OptimizeSRA,
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bool SupportsAVX);
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std::unique_ptr<FEXCore::IR::Pass> CreateStaticRegisterAllocationPass(bool SupportsAVX);
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std::unique_ptr<FEXCore::IR::Pass> CreateLongDivideEliminationPass();
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namespace Validation {
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std::unique_ptr<FEXCore::IR::Pass> CreateIRValidation();
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std::unique_ptr<FEXCore::IR::Pass> CreateRAValidation();
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std::unique_ptr<FEXCore::IR::Pass> CreatePhiValidation();
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std::unique_ptr<FEXCore::IR::Pass> CreateValueDominanceValidation();
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}
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}
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