mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-13 01:00:46 +02:00
Ryan Houdek
b1a3f82923
Requires the IR headerop to house the number of host instructions this code is translating for the stats. Fixes compiling with disassembly enabled, will be used with the instruction count CI.
336 lines
9.6 KiB
C++
336 lines
9.6 KiB
C++
/*
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$info$
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meta: ir|dumper ~ IR -> Text
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tags: ir|dumper
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$end_info$
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*/
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/IR/IntrusiveIRList.h>
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#include <FEXCore/IR/RegisterAllocationData.h>
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#include <FEXCore/fextl/sstream.h>
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#include <algorithm>
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#include <array>
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#include <ostream>
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#include <stdint.h>
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#include <string_view>
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#include <iomanip>
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namespace FEXCore::IR {
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#define IROP_GETNAME_IMPL
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#define IROP_GETRAARGS_IMPL
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#define IROP_REG_CLASSES_IMPL
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#define IROP_HASSIDEEFFECTS_IMPL
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#define IROP_SIZES_IMPL
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#define IROP_GETHASDEST_IMPL
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#include <FEXCore/IR/IRDefines.inc>
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static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, const SHA256Sum &Arg) {
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*out << "sha256:";
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for(auto byte: Arg.data)
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*out << std::hex << std::setfill('0') << std::setw(2) << (unsigned int)byte;
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}
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static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, uint64_t Arg) {
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*out << "#0x" << std::hex << Arg;
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}
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[[maybe_unused]]
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static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, const char* Arg) {
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*out << Arg;
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}
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static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, CondClassType Arg) {
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static constexpr std::array<std::string_view, 22> CondNames = {
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"EQ",
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"NEQ",
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"UGE",
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"ULT",
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"MI",
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"PL",
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"VS",
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"VC",
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"UGT",
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"ULE",
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"SGE",
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"SLT",
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"SGT",
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"SLE",
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"Invalid Cond",
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"Invalid Cond",
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"FLU",
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"FGE",
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"FLEU",
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"FGT",
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"FU",
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"FNU"
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};
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*out << CondNames[Arg];
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}
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static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, MemOffsetType Arg) {
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static constexpr std::array<std::string_view, 3> Names = {
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"SXTX",
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"UXTW",
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"SXTW",
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};
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*out << Names[Arg];
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}
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static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, RegisterClassType Arg) {
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if (Arg == GPRClass.Val)
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*out << "GPR";
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else if (Arg == GPRFixedClass.Val)
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*out << "GPRFixed";
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else if (Arg == FPRClass.Val)
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*out << "FPR";
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else if (Arg == FPRFixedClass.Val)
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*out << "FPRFixed";
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else if (Arg == GPRPairClass.Val)
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*out << "GPRPair";
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else
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*out << "Unknown Registerclass " << Arg;
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}
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static void PrintArg(fextl::stringstream *out, IRListView const* IR, OrderedNodeWrapper Arg, IR::RegisterAllocationData *RAData) {
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auto [CodeNode, IROp] = IR->at(Arg)();
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const auto ArgID = Arg.ID();
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if (ArgID.IsInvalid()) {
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*out << "%Invalid";
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} else {
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*out << "%" << std::dec << ArgID;
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if (RAData) {
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auto PhyReg = RAData->GetNodeRegister(ArgID);
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switch (PhyReg.Class) {
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case FEXCore::IR::GPRClass.Val: *out << "(GPR"; break;
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case FEXCore::IR::GPRFixedClass.Val: *out << "(GPRFixed"; break;
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case FEXCore::IR::FPRClass.Val: *out << "(FPR"; break;
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case FEXCore::IR::FPRFixedClass.Val: *out << "(FPRFixed"; break;
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case FEXCore::IR::GPRPairClass.Val: *out << "(GPRPair"; break;
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case FEXCore::IR::ComplexClass.Val: *out << "(Complex"; break;
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case FEXCore::IR::InvalidClass.Val: *out << "(Invalid"; break;
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default: *out << "(Unknown"; break;
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}
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if (PhyReg.Class != FEXCore::IR::InvalidClass.Val) {
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*out << std::dec << (uint32_t)PhyReg.Reg << ")";
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} else {
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*out << ")";
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}
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}
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}
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if (GetHasDest(IROp->Op)) {
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uint32_t ElementSize = IROp->ElementSize;
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uint32_t NumElements = IROp->Size;
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if (!IROp->ElementSize) {
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ElementSize = IROp->Size;
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}
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if (ElementSize) {
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NumElements /= ElementSize;
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}
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*out << " i" << std::dec << (ElementSize * 8);
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if (NumElements > 1) {
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*out << "v" << std::dec << NumElements;
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}
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}
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}
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static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::FenceType Arg) {
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if (Arg == IR::Fence_Load) {
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*out << "Loads";
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}
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else if (Arg == IR::Fence_Store) {
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*out << "Stores";
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}
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else if (Arg == IR::Fence_LoadStore) {
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*out << "LoadStores";
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}
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else {
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*out << "<Unknown Fence Type>";
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}
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}
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static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::RoundType Arg) {
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switch (Arg) {
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case FEXCore::IR::Round_Nearest: *out << "Nearest"; break;
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case FEXCore::IR::Round_Negative_Infinity: *out << "-Inf"; break;
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case FEXCore::IR::Round_Positive_Infinity: *out << "+Inf"; break;
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case FEXCore::IR::Round_Towards_Zero: *out << "Towards Zero"; break;
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case FEXCore::IR::Round_Host: *out << "Host"; break;
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default: *out << "<Unknown Round Type>"; break;
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}
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}
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static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::SyscallFlags Arg) {
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switch (Arg) {
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case FEXCore::IR::SyscallFlags::DEFAULT: *out << "Default"; break;
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case FEXCore::IR::SyscallFlags::OPTIMIZETHROUGH: *out << "Optimize Through"; break;
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case FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY: *out << "No Sync State on Entry"; break;
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case FEXCore::IR::SyscallFlags::NORETURN: *out << "No Return"; break;
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case FEXCore::IR::SyscallFlags::NOSIDEEFFECTS: *out << "No Side Effects"; break;
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default: *out << "<Unknown Round Type>"; break;
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}
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}
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static void PrintArg(fextl::stringstream *out, [[maybe_unused]] IRListView const* IR, FEXCore::IR::BreakDefinition Arg) {
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*out << "{" << Arg.ErrorRegister << ".";
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*out << static_cast<uint32_t>(Arg.Signal) << ".";
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*out << static_cast<uint32_t>(Arg.TrapNumber) << ".";
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*out << static_cast<uint32_t>(Arg.si_code) << "}";
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}
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void Dump(fextl::stringstream *out, IRListView const* IR, IR::RegisterAllocationData *RAData) {
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auto HeaderOp = IR->GetHeader();
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int8_t CurrentIndent = 0;
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auto AddIndent = [&out, &CurrentIndent]() {
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for (uint8_t i = 0; i < CurrentIndent; ++i) {
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*out << "\t";
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}
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};
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++CurrentIndent;
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AddIndent();
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*out << "(%0) " << "IRHeader ";
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*out << "%" << HeaderOp->Blocks.ID() << ", ";
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*out << "#" << std::dec << HeaderOp->OriginalRIP << ", ";
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*out << "#" << std::dec << HeaderOp->BlockCount << ", ";
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*out << "#" << std::dec << HeaderOp->NumHostInstructions << std::endl;
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for (auto [BlockNode, BlockHeader] : IR->GetBlocks()) {
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{
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auto BlockIROp = BlockHeader->C<FEXCore::IR::IROp_CodeBlock>();
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AddIndent();
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*out << "(%" << IR->GetID(BlockNode) << ") " << "CodeBlock ";
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*out << "%" << BlockIROp->Begin.ID() << ", ";
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*out << "%" << BlockIROp->Last.ID() << std::endl;
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}
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++CurrentIndent;
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for (auto [CodeNode, IROp] : IR->GetCode(BlockNode)) {
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const auto ID = IR->GetID(CodeNode);
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const auto Name = FEXCore::IR::GetName(IROp->Op);
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bool Skip{};
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switch (IROp->Op) {
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case IR::OP_PHIVALUE:
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Skip = true;
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break;
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default: break;
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}
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if (!Skip) {
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AddIndent();
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if (GetHasDest(IROp->Op)) {
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uint32_t ElementSize = IROp->ElementSize;
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uint32_t NumElements = IROp->Size;
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if (!IROp->ElementSize) {
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ElementSize = IROp->Size;
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}
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if (ElementSize) {
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NumElements /= ElementSize;
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}
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*out << "%" << std::dec << ID;
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if (RAData) {
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auto PhyReg = RAData->GetNodeRegister(ID);
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switch (PhyReg.Class) {
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case FEXCore::IR::GPRClass.Val: *out << "(GPR"; break;
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case FEXCore::IR::GPRFixedClass.Val: *out << "(GPRFixed"; break;
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case FEXCore::IR::FPRClass.Val: *out << "(FPR"; break;
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case FEXCore::IR::FPRFixedClass.Val: *out << "(FPRFixed"; break;
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case FEXCore::IR::GPRPairClass.Val: *out << "(GPRPair"; break;
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case FEXCore::IR::ComplexClass.Val: *out << "(Complex"; break;
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case FEXCore::IR::InvalidClass.Val: *out << "(Invalid"; break;
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default: *out << "(Unknown"; break;
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}
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if (PhyReg.Class != FEXCore::IR::InvalidClass.Val) {
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*out << std::dec << (uint32_t)PhyReg.Reg << ")";
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} else {
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*out << ")";
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}
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}
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*out << " i" << std::dec << (ElementSize * 8);
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if (NumElements > 1) {
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*out << "v" << std::dec << NumElements;
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}
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*out << " = ";
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}
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else {
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uint32_t ElementSize = IROp->ElementSize;
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if (!IROp->ElementSize) {
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ElementSize = IROp->Size;
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}
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uint32_t NumElements = 0;
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if (ElementSize) {
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NumElements = IROp->Size / ElementSize;
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}
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*out << "(%" << std::dec << ID << ' ';
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*out << 'i' << std::dec << (ElementSize * 8);
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if (NumElements > 1) {
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*out << 'v' << std::dec << NumElements;
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}
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*out << ") ";
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}
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*out << Name;
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#define IROP_ARGPRINTER_HELPER
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#include <FEXCore/IR/IRDefines.inc>
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case IR::OP_PHI: {
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auto Op = IROp->C<IR::IROp_Phi>();
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auto NodeBegin = IR->at(Op->PhiBegin);
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*out << " ";
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while (NodeBegin != NodeBegin.Invalid()) {
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auto [NodeNode, IROp] = NodeBegin();
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auto PhiOp = IROp->C<IR::IROp_PhiValue>();
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*out << "[ ";
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PrintArg(out, IR, PhiOp->Value, RAData);
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*out << ", ";
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PrintArg(out, IR, PhiOp->Block, RAData);
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*out << " ]";
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if (PhiOp->Next.ID().IsValid()) {
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*out << ", ";
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}
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NodeBegin = IR->at(PhiOp->Next);
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}
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break;
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}
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default: *out << "<Unknown Args>"; break;
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}
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//*out << " (" << std::dec << CodeNode->GetUses() << ")";
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*out << "\n";
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}
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}
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CurrentIndent = std::max(0, CurrentIndent - 1);
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}
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}
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}
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