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Didn't notice this in the previous PR, When DUMPIR=stderr without and selection of where to place it in PASSMANAGERDUMPIR it was supposed to put the dumper at the end of the passes. We need to make sure that it it placed at the end of the passes rather than current `it`.
126 lines
4.0 KiB
C++
126 lines
4.0 KiB
C++
/*
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$info$
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meta: ir|opts ~ IR to IR Optimization
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tags: ir|opts
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desc: Defines which passes are run, and runs them
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$end_info$
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*/
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#include "Interface/Context/Context.h"
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#include "Interface/IR/PassManager.h"
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#include "Interface/IR/Passes.h"
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#include "Interface/IR/Passes/RegisterAllocationPass.h"
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#include <FEXCore/Config/Config.h>
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#include <FEXCore/Utils/Profiler.h>
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namespace FEXCore::IR {
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class IREmitter;
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void PassManager::Finalize() {
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if (!PassManagerDumpIR()) {
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// Not configured to dump any IR, just return.
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return;
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}
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auto it = Passes.begin();
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// Walk the passes and add them where asked.
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if (PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::BEFOREOPT) {
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// Insert at the start.
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it = InsertAt(it, Debug::CreateIRDumper());
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++it; // Skip what we inserted.
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}
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if ((PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::BEFOREPASS) ||
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(PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::AFTERPASS)) {
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bool SkipFirstBefore = PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::BEFOREOPT;
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for (; it != Passes.end();) {
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if (PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::BEFOREPASS) {
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if (SkipFirstBefore) {
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// If we need to skip the first one, then continue.
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SkipFirstBefore = false;
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++it;
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continue;
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}
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// Insert before
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it = InsertAt(it, Debug::CreateIRDumper());
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++it; // Skip what we inserted.
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}
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++it; // Skip current pass.
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if (PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::AFTERPASS) {
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// Insert after
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it = InsertAt(it, Debug::CreateIRDumper());
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++it; // Skip what we inserted.
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}
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}
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}
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if (PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::AFTEROPT) {
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if (!(PassManagerDumpIR() & FEXCore::Config::PassManagerDumpIR::AFTERPASS)) {
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// Insert final IRDumper.
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InsertAt(Passes.end(), Debug::CreateIRDumper());
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}
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}
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}
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void PassManager::AddDefaultPasses(FEXCore::Context::ContextImpl *ctx, bool InlineConstants, bool StaticRegisterAllocation) {
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FEX_CONFIG_OPT(DisablePasses, O0);
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if (!DisablePasses()) {
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InsertPass(CreateContextLoadStoreElimination(ctx->HostFeatures.SupportsAVX));
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if (Is64BitMode()) {
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// This needs to run after RCLSE
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// This only matters for 64-bit code since these instructions don't exist in 32-bit
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InsertPass(CreateLongDivideEliminationPass());
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}
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InsertPass(CreateDeadStoreElimination(ctx->HostFeatures.SupportsAVX));
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InsertPass(CreatePassDeadCodeElimination());
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InsertPass(CreateConstProp(InlineConstants, ctx->HostFeatures.SupportsTSOImm9));
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////// InsertPass(CreateDeadFlagCalculationEliminination());
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InsertPass(CreateSyscallOptimization());
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InsertPass(CreatePassDeadCodeElimination());
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}
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// If the IR is compacted post-RA then the node indexing gets messed up and the backend isn't able to find the register assigned to a node
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// Compact before IR, don't worry about RA generating spills/fills
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InsertPass(CreateIRCompaction(ctx->OpDispatcherAllocator), "Compaction");
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}
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void PassManager::AddDefaultValidationPasses() {
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#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
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InsertValidationPass(Validation::CreatePhiValidation());
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InsertValidationPass(Validation::CreateIRValidation(), "IRValidation");
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InsertValidationPass(Validation::CreateRAValidation());
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InsertValidationPass(Validation::CreateValueDominanceValidation());
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#endif
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}
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void PassManager::InsertRegisterAllocationPass(bool OptimizeSRA, bool SupportsAVX) {
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InsertPass(IR::CreateRegisterAllocationPass(GetPass("Compaction"), OptimizeSRA, SupportsAVX), "RA");
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}
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bool PassManager::Run(IREmitter *IREmit) {
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FEXCORE_PROFILE_SCOPED("PassManager::Run");
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bool Changed = false;
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for (auto const &Pass : Passes) {
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Changed |= Pass->Run(IREmit);
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}
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#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
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for (auto const &Pass : ValidationPasses) {
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Changed |= Pass->Run(IREmit);
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}
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#endif
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return Changed;
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}
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}
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