mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-14 18:00:46 +02:00
Ryan Houdek
37983006f0
Sadly these things can't be split without breaking functionality so it turns in to a bit of a mess. SyscallHandler is very much something that is a Linux only construct and shouldn't be in FEXCore itself. Lets the frontend register a Syscallhandler with FEXCore. FEXCore itself is then aware of the current syscall ABI and handles the ABI in an optimal fashion. So it is not a 100% clean break otherwise we would lose performance. The SignalDelegator then needs to move to the frontend since the SyscallHandler requires it for signal based syscalls. The CPU backend signal handling still needs to happen in FEXCore because it is a very tight coupling with the CPU backend. Once we need to support more Signal handling we can give the backends cleaner support to select which specific OS handler to handle.
651 lines
20 KiB
C++
651 lines
20 KiB
C++
#include <filesystem>
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#include <unistd.h>
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#include <FEXCore/Utils/LogManager.h>
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#include "FEXCore/Core/CodeLoader.h"
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#include <FEXCore/Core/Context.h>
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#include "Tests/LinuxSyscalls/Syscalls.h"
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#include "Tests/LinuxSyscalls/FileManagement.h"
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#include "Tests/LinuxSyscalls/EmulatedFiles/EmulatedFiles.h"
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using string = std::string;
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namespace FEX::EmulatedFile {
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std::string GenerateCPUInfo(FEXCore::Context::Context *ctx, uint32_t CPUCores) {
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std::ostringstream cpu_stream{};
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auto res_0 = FEXCore::Context::RunCPUIDFunction(ctx, 0, 0);
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auto res_1 = FEXCore::Context::RunCPUIDFunction(ctx, 1, 0);
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auto res_6 = FEXCore::Context::RunCPUIDFunction(ctx, 6, 0);
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auto res_7 = FEXCore::Context::RunCPUIDFunction(ctx, 7, 0);
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auto res_10 = FEXCore::Context::RunCPUIDFunction(ctx, 0x10, 0);
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auto res_8000_0001 = FEXCore::Context::RunCPUIDFunction(ctx, 0x8000'0001, 0);
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auto res_8000_0002 = FEXCore::Context::RunCPUIDFunction(ctx, 0x8000'0002, 0);
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auto res_8000_0003 = FEXCore::Context::RunCPUIDFunction(ctx, 0x8000'0003, 0);
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auto res_8000_0004 = FEXCore::Context::RunCPUIDFunction(ctx, 0x8000'0004, 0);
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auto res_8000_0007 = FEXCore::Context::RunCPUIDFunction(ctx, 0x8000'0007, 0);
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auto res_8000_0008 = FEXCore::Context::RunCPUIDFunction(ctx, 0x8000'0008, 0);
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auto res_8000_000a = FEXCore::Context::RunCPUIDFunction(ctx, 0x8000'000a, 0);
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auto res_8000_001f = FEXCore::Context::RunCPUIDFunction(ctx, 0x8000'001f, 0);
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union VendorID {
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struct {
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uint32_t id;
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char Str[13];
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};
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struct {
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FEXCore::CPUID::FunctionResults cpuid;
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uint8_t null;
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};
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};
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union ModelName {
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struct {
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char Str[49];
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};
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struct {
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FEXCore::CPUID::FunctionResults cpuid_2;
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FEXCore::CPUID::FunctionResults cpuid_3;
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FEXCore::CPUID::FunctionResults cpuid_4;
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uint8_t null;
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};
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};
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union Info {
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FEXCore::CPUID::FunctionResults cpuid;
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struct {
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unsigned Stepping : 4;
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unsigned Model : 4;
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unsigned FamilyID : 4;
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unsigned Type : 4;
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unsigned ExModelID : 4;
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unsigned ExFamilyID : 8;
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unsigned : 4;
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};
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};
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VendorID vendorid {};
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vendorid.cpuid = {res_0.eax, res_0.ebx, res_0.edx, res_0.ecx};
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vendorid.null = 0;
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ModelName modelname {};
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modelname.cpuid_2 = res_8000_0002;
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modelname.cpuid_3 = res_8000_0003;
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modelname.cpuid_4 = res_8000_0004;
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modelname.null = 0;
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Info info {res_1};
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uint32_t Family = info.FamilyID + (info.FamilyID == 0xF ? info.ExFamilyID : 0);
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for (int i = 0; i < CPUCores; ++i) {
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cpu_stream << "processor : " << i << std::endl;
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cpu_stream << "vendor_id : " << vendorid.Str << std::endl;
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cpu_stream << "cpu family : " << Family << std::endl;
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cpu_stream << "model : " << (info.Model + (info.FamilyID >= 6 ? (info.ExModelID << 4) : 0)) << std::endl;
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cpu_stream << "model name : " << modelname.Str << std::endl;
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cpu_stream << "stepping : " << info.Stepping << std::endl;
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cpu_stream << "microcode : 0x0" << std::endl;
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cpu_stream << "cpu MHz : 3000" << std::endl;
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cpu_stream << "cache size : 512 KB" << std::endl;
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cpu_stream << "physical id : " << i << std::endl;
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cpu_stream << "siblings : " << CPUCores << std::endl;
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cpu_stream << "core id : " << i << std::endl;
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cpu_stream << "cpu cores : " << CPUCores << std::endl;
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cpu_stream << "apicid : " << i << std::endl;
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cpu_stream << "initial apicid : " << i << std::endl;
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cpu_stream << "fpu : " << (res_1.edx & (1 << 0) ? "yes" : "no") << std::endl;
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cpu_stream << "fpu_exception : " << (res_1.edx & (1 << 0) ? "yes" : "no") << std::endl;
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cpu_stream << "cpuid level : " << vendorid.id << std::endl;
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cpu_stream << "wp : yes" << std::endl;
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cpu_stream << "flags : ";
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#define FLAG(flag, name) if (flag) { cpu_stream << name << " "; }
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FLAG(res_1.edx & (1 << 0), "fpu")
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FLAG(res_1.edx & (1 << 1), "vme")
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FLAG(res_1.edx & (1 << 2), "de")
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FLAG(res_1.edx & (1 << 3), "pse")
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FLAG(res_1.edx & (1 << 4), "tsc")
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FLAG(res_1.edx & (1 << 5), "msr")
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FLAG(res_1.edx & (1 << 6), "pae")
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FLAG(res_1.edx & (1 << 7), "mce")
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FLAG(res_1.edx & (1 << 8), "cx8")
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FLAG(res_1.edx & (1 << 9), "apic")
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FLAG(res_1.edx & (1 << 11), "sep")
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FLAG(res_1.edx & (1 << 12), "mtrr")
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FLAG(res_1.edx & (1 << 13), "pge")
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FLAG(res_1.edx & (1 << 14), "mca")
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FLAG(res_1.edx & (1 << 15), "cmov")
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FLAG(res_1.edx & (1 << 16), "pat")
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FLAG(res_1.edx & (1 << 17), "pse36")
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FLAG(res_1.edx & (1 << 18), "pn")
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FLAG(res_1.edx & (1 << 19), "clflush")
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FLAG(res_1.edx & (1 << 21), "ds") // XXX
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FLAG(res_1.edx & (1 << 22), "acpi") // XXX
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FLAG(res_1.edx & (1 << 23), "mmx")
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FLAG(res_1.edx & (1 << 24), "fxsr")
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FLAG(res_1.edx & (1 << 25), "sse")
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FLAG(res_1.edx & (1 << 26), "sse2")
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FLAG(res_1.edx & (1 << 27), "ss")
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FLAG(res_1.edx & (1 << 28), "ht")
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FLAG(res_1.edx & (1 << 29), "tm")
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FLAG(res_1.edx & (1 << 30), "ia64")
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FLAG(res_1.edx & (1 << 31), "pbe")
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FLAG(res_8000_0001.edx & (1 << 11),
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"syscall")
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FLAG(res_8000_0001.edx & (1 << 19),
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"mp")
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FLAG(res_8000_0001.edx & (1 << 20),
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"nx")
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FLAG(res_8000_0001.edx & (1 << 22),
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"mmxext")
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FLAG(res_8000_0001.edx & (1 << 25),
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"fxsr_opt")
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FLAG(res_8000_0001.edx & (1 << 26),
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"pdpe1gb")
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FLAG(res_8000_0001.edx & (1 << 27),
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"rdtscp")
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FLAG(res_8000_0001.edx & (1 << 29),
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"lm")
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FLAG(res_8000_0001.edx & (1 << 31),
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"3dnow")
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FLAG(res_8000_0001.edx & (1 << 30),
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"3dnowext")
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FLAG(res_8000_0007.edx & (1 << 8),
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"constant_tsc")
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// We are not a uniprocessor running in SMP mode
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FLAG(false, "up")
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// Timer is always running
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FLAG(true, "art")
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// No Intel perfmon
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FLAG(false, "arch_perfmon")
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// No precise event based sampling
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FLAG(false, "pebs")
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// No branch trace store
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FLAG(false, "bts")
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FLAG(true, "rep_good")
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FLAG(res_8000_0007.edx & (1 << 12),
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"tm")
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// Always support long nop
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FLAG(true, "nopl")
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// Always expose topology information
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FLAG(true, "xtoplogy")
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// Atom/geode only?
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FLAG(false, "tsc_reliable")
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FLAG(res_8000_0007.edx & (1 << 8),
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"nonstop_tsc")
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// We always support CPUID
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FLAG(true, "cpuid")
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FLAG(Family > 0x16,
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"extd_apicid")
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FLAG(false, "amd_dcm") // Never claim to be a multi node processor
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FLAG(res_8000_0007.edx & (1 << 11),
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"aperfmperf")
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// Need to check ARM documentation if we can support this?
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FLAG(false, "nonstop_tsc_s3")
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// We can calculate this flag on AArch64
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FLAG(true, "tsc_known_freq")
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FLAG(res_1.ecx & (1 << 0),
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"pni")
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FLAG(res_1.ecx & (1 << 1),
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"pclmulqdq")
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FLAG(res_1.ecx & (1 << 2),
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"dtes64")
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FLAG(res_1.ecx & (1 << 3),
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"monitor")
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FLAG(res_1.ecx & (1 << 4),
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"ds_cpl")
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FLAG(res_1.ecx & (1 << 5),
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"vmx")
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FLAG(res_1.ecx & (1 << 6),
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"smx")
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FLAG(res_1.ecx & (1 << 7),
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"est")
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FLAG(res_1.ecx & (1 << 8),
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"tm2")
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FLAG(res_1.ecx & (1 << 9),
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"ssse3")
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FLAG(res_1.ecx & (1 << 11),
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"sdbg")
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FLAG(res_1.ecx & (1 << 12),
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"fma")
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FLAG(res_1.ecx & (1 << 13),
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"cx16")
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FLAG(res_1.ecx & (1 << 14),
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"xptr")
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FLAG(res_1.ecx & (1 << 15),
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"pdcm")
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FLAG(res_1.ecx & (1 << 17),
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"pcid")
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FLAG(res_1.ecx & (1 << 18),
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"dca")
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FLAG(res_1.ecx & (1 << 19),
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"sse4_1")
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FLAG(res_1.ecx & (1 << 20),
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"sse4_2")
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FLAG(res_1.ecx & (1 << 21),
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"x2apic")
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FLAG(res_1.ecx & (1 << 22),
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"movbe")
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FLAG(res_1.ecx & (1 << 23),
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"popcnt")
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FLAG(res_1.ecx & (1 << 24),
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"tsc_deadline_timer")
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FLAG(res_1.ecx & (1 << 25),
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"aes")
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FLAG(res_1.ecx & (1 << 26),
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"xsave")
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FLAG(res_1.ecx & (1 << 28),
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"avx")
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FLAG(res_1.ecx & (1 << 29),
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"f16c")
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FLAG(res_1.ecx & (1 << 30),
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"rdrand")
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FLAG(res_1.ecx & (1 << 31),
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"hypervisor")
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FLAG(res_8000_0001.ecx & (1 << 0),
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"lahf_lm")
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FLAG(res_8000_0001.ecx & (1 << 1),
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"cmp_legacy")
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FLAG(res_8000_0001.ecx & (1 << 2),
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"svm")
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FLAG(res_8000_0001.ecx & (1 << 3),
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"extapic")
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FLAG(res_8000_0001.ecx & (1 << 4),
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"cr8_legacy")
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FLAG(res_8000_0001.ecx & (1 << 5),
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"abm")
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FLAG(res_8000_0001.ecx & (1 << 6),
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"sse4a")
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FLAG(res_8000_0001.ecx & (1 << 7),
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"misalignsse")
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FLAG(res_8000_0001.ecx & (1 << 8),
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"3dnowprefetch")
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FLAG(res_8000_0001.ecx & (1 << 9),
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"osvw")
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FLAG(res_8000_0001.ecx & (1 << 10),
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"ibs")
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FLAG(res_8000_0001.ecx & (1 << 11),
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"xop")
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FLAG(res_8000_0001.ecx & (1 << 12),
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"skinit")
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FLAG(res_8000_0001.ecx & (1 << 13),
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"wdt")
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FLAG(res_8000_0001.ecx & (1 << 15),
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"lwp")
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FLAG(res_8000_0001.ecx & (1 << 16),
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"fma4")
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FLAG(res_8000_0001.ecx & (1 << 17),
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"tce")
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FLAG(res_8000_0001.ecx & (1 << 19),
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"nodeid_msr")
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FLAG(res_8000_0001.ecx & (1 << 21),
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"tbm")
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FLAG(res_8000_0001.ecx & (1 << 22),
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"topoext")
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FLAG(res_8000_0001.ecx & (1 << 23),
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"perfctr_core")
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FLAG(res_8000_0001.ecx & (1 << 24),
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"perfctr_nb")
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FLAG(res_8000_0001.ecx & (1 << 26),
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"bpext")
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FLAG(res_8000_0001.ecx & (1 << 27),
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"ptsc")
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FLAG(res_8000_0001.ecx & (1 << 28),
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"perfctr_llc")
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FLAG(res_8000_0001.ecx & (1 << 29),
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"mwaitx")
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// We don't support ring 3 supporting mwait
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FLAG(false, "ring3mwait")
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// We don't support Intel CPUID fault support
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FLAG(false, "cpuid_fault")
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FLAG(res_8000_0007.edx & (1 << 9),
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"cpb")
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FLAG(res_6.ecx & (1 << 3),
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"epb")
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FLAG(res_10.ebx & (1 << 1),
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"cat_l3")
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FLAG(res_10.ebx & (1 << 2),
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"cat_l2")
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FLAG(false, // Needs leaf support
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"cdp_l3")
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FLAG(false, "invpcid_single")
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FLAG(res_8000_0007.edx & (1 << 7),
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"hw_pstate")
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FLAG(res_8000_001f.eax & (1 << 0),
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"sme")
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// Kernel page table isolation.
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FLAG(false, "pti")
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// We don't support Intel's Protected Processor Inventory Number
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FLAG(false, "intel_ppin")
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FLAG(false, // Needs leaf support
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"cdp_l2")
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FLAG(res_8000_0008.ebx & (1 << 6),
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"mba")
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FLAG(res_8000_001f.eax & (1 << 1),
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"sev")
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{
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// Speculative bug workarounds
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// We don't claim to have these bugs, so we don't need to claim these flags
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FLAG(res_7.edx & (1 << 31),
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"ssbd")
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FLAG(false, "ibrs")
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FLAG(false, "ibpb")
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FLAG(res_7.edx & (1 << 27),
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"stibp")
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FLAG(false, "ibrs_enhanced")
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}
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// We don't support Intel's TPR Shadow feature
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FLAG(false, "tpr_shadow")
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// Intel virtual NMI
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FLAG(false, "vnmi")
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// Intel FlexPriority
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FLAG(false, "flexpriority")
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// Intel Extended page table
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FLAG(false, "ept")
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// Intel virtual processor ID
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FLAG(false, "vpid")
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// Prefer VMMCall to VMCall
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FLAG(false, "vmmcall")
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// Intel extended page table access dirty bit
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FLAG(false, "ept_ad")
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FLAG(res_7.ebx & (1 << 0),
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"fsgsbase")
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FLAG(res_7.ebx & (1 << 1),
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"tsc_adjust")
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FLAG(res_7.ebx & (1 << 3),
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"bmi1")
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FLAG(res_7.ebx & (1 << 4),
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"hle")
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FLAG(res_7.ebx & (1 << 5),
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"avx2")
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FLAG(res_7.ebx & (1 << 7),
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"smep")
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FLAG(res_7.ebx & (1 << 8),
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"bmi2")
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FLAG(res_7.ebx & (1 << 9),
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"erms")
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FLAG(res_7.ebx & (1 << 10),
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"invpcid")
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FLAG(res_7.ebx & (1 << 11),
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"rtm")
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FLAG(false, // Needs leaf support
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"cqm")
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FLAG(res_7.ebx & (1 << 14),
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"mpx")
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FLAG(false, // Needs leaf support
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"rdt_a")
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FLAG(res_7.ebx & (1 << 16),
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"avx512f")
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FLAG(res_7.ebx & (1 << 17),
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"avx512dq")
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FLAG(res_7.ebx & (1 << 18),
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"rdseed")
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FLAG(res_7.ebx & (1 << 19),
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"adx")
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FLAG(res_7.ebx & (1 << 20),
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"smap")
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FLAG(res_7.ebx & (1 << 21),
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"avx512ifma")
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FLAG(res_7.ebx & (1 << 23),
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"clflushopt")
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FLAG(res_7.ebx & (1 << 24),
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"clwb")
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FLAG(res_7.ebx & (1 << 25),
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"intel_pt")
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FLAG(res_7.ebx & (1 << 26),
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"avx512pf")
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FLAG(res_7.ebx & (1 << 27),
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"avx512er")
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FLAG(res_7.ebx & (1 << 28),
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"avx512cd")
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FLAG(res_7.ebx & (1 << 29),
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"sha_ni")
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FLAG(res_7.ebx & (1 << 30),
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"avx512bw")
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FLAG(res_7.ebx & (1 << 31),
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"avx512vl")
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FLAG(false, // Needs leaf support // res_d.eax & (1 << 0) // Leaf 1h
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"xsaveopt")
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FLAG(false, // Needs leaf support // res_d.eax & (1 << 1) // Leaf 1h
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"xsavec")
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FLAG(false, // Needs leaf support // res_d.eax & (1 << 2) // Leaf 1h
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"xgetbv1")
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FLAG(false, // Needs leaf support // res_d.eax & (1 << 3) // Leaf 1h
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"xsaves")
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FLAG(false, // Needs leaf support
|
|
"avx512_bf16")
|
|
FLAG(res_8000_0008.ebx & (1 << 0),
|
|
"clzero")
|
|
FLAG(res_8000_0008.ebx & (1 << 1),
|
|
"irperf")
|
|
FLAG(res_8000_0008.ebx & (1 << 2),
|
|
"xsaveerptr")
|
|
|
|
// Intel digital thermal sensor
|
|
FLAG(false, "dtherm")
|
|
// Intel turbo boost
|
|
FLAG(false, "ida")
|
|
FLAG(res_6.eax & (1 << 2),
|
|
"arat")
|
|
// Power limit notification controls
|
|
FLAG(false, "pln")
|
|
// Intel package thermal status
|
|
FLAG(false, "pts")
|
|
|
|
// Intel Hardware P-state features
|
|
FLAG(false, "hwp")
|
|
FLAG(false, "hwp_notify")
|
|
FLAG(false, "hwp_act_window")
|
|
FLAG(false, "hwp_epp")
|
|
FLAG(false, "hwp_pkg_req")
|
|
|
|
FLAG(res_8000_000a.ebx & (1 << 0),
|
|
"npt")
|
|
FLAG(res_8000_000a.ebx & (1 << 1),
|
|
"lbrv")
|
|
FLAG(res_8000_000a.ebx & (1 << 2),
|
|
"svm_lock")
|
|
FLAG(res_8000_000a.ebx & (1 << 3),
|
|
"nrip_save")
|
|
FLAG(res_8000_000a.ebx & (1 << 4),
|
|
"tsc_scale")
|
|
FLAG(res_8000_000a.ebx & (1 << 5),
|
|
"vmcb_clean")
|
|
FLAG(res_8000_000a.ebx & (1 << 6),
|
|
"flushbyasid")
|
|
FLAG(res_8000_000a.ebx & (1 << 7),
|
|
"decodeassists")
|
|
FLAG(res_8000_000a.ebx & (1 << 10),
|
|
"pausefilter")
|
|
FLAG(res_8000_000a.ebx & (1 << 12),
|
|
"pfthreshold")
|
|
FLAG(res_8000_000a.ebx & (1 << 13),
|
|
"avic")
|
|
FLAG(res_8000_000a.ebx & (1 << 15),
|
|
"v_vmsave_vmload")
|
|
FLAG(res_8000_000a.ebx & (1 << 16),
|
|
"vgif")
|
|
|
|
FLAG(res_7.ecx & (1 << 1),
|
|
"avx512vbmi")
|
|
FLAG(res_7.ecx & (1 << 2),
|
|
"umip")
|
|
FLAG(res_7.ecx & (1 << 3),
|
|
"pku")
|
|
FLAG(res_7.ecx & (1 << 4),
|
|
"ospke")
|
|
FLAG(res_7.ecx & (1 << 5),
|
|
"waitpkg")
|
|
FLAG(res_7.ecx & (1 << 6),
|
|
"avx512_vbmi2")
|
|
FLAG(res_7.ecx & (1 << 8),
|
|
"gfni")
|
|
FLAG(res_7.ecx & (1 << 9),
|
|
"vaes")
|
|
FLAG(res_7.ecx & (1 << 10),
|
|
"vpclmulqdq")
|
|
FLAG(res_7.ecx & (1 << 11),
|
|
"avx512_vnni")
|
|
FLAG(res_7.ecx & (1 << 12),
|
|
"avx512_bitalg")
|
|
FLAG(res_7.ecx & (1 << 13),
|
|
"tme")
|
|
FLAG(res_7.ecx & (1 << 14),
|
|
"avx512_vpopcntdq")
|
|
FLAG(res_7.ecx & (1 << 16),
|
|
"la57")
|
|
FLAG(res_7.ecx & (1 << 22),
|
|
"rdpid")
|
|
FLAG(res_7.ecx & (1 << 25),
|
|
"cldemote")
|
|
FLAG(res_7.ecx & (1 << 27),
|
|
"movdiri")
|
|
FLAG(res_7.ecx & (1 << 28),
|
|
"movdir64b")
|
|
|
|
FLAG(res_8000_0007.ebx & (1 << 0),
|
|
"overflow_recov")
|
|
FLAG(res_8000_0007.ebx & (1 << 1),
|
|
"succor")
|
|
FLAG(res_8000_0007.ebx & (1 << 3),
|
|
"smca")
|
|
|
|
FLAG(res_7.edx & (1 << 2),
|
|
"avx512_4vnniw")
|
|
FLAG(res_7.edx & (1 << 3),
|
|
"avx512_4fmaps")
|
|
FLAG(res_7.edx & (1 << 4),
|
|
"fsrm")
|
|
FLAG(res_7.edx & (1 << 8),
|
|
"avx512_vp2intersect")
|
|
FLAG(res_7.edx & (1 << 10),
|
|
"md_clear")
|
|
FLAG(res_7.edx & (1 << 14),
|
|
"serialize")
|
|
FLAG(res_7.edx & (1 << 18),
|
|
"pconfig")
|
|
FLAG(res_7.edx & (1 << 19),
|
|
"arch_lbr")
|
|
FLAG(res_7.edx & (1 << 28),
|
|
"flush_l1d")
|
|
FLAG(res_7.edx & (1 << 29),
|
|
"arch_capabilities")
|
|
|
|
cpu_stream << std::endl;
|
|
|
|
// We don't have any bugs, don't question it
|
|
cpu_stream << "bugs : " << std::endl;
|
|
cpu_stream << "bogomips : 8000.0" << std::endl;
|
|
// These next four aren't necessarily correct
|
|
cpu_stream << "TLB size : 2560 4K pages" << std::endl;
|
|
cpu_stream << "clflush size : 64" << std::endl;
|
|
cpu_stream << "cache_alignment : 64" << std::endl;
|
|
|
|
// Cortex-A is 40 or 44 bits physical, and 48/52 virtual
|
|
// Choose the lesser configuration
|
|
cpu_stream << "address sizes : 40 bits physical, 48 bits virtual" << std::endl;
|
|
|
|
cpu_stream << std::endl;
|
|
}
|
|
|
|
return cpu_stream.str();
|
|
}
|
|
|
|
EmulatedFDManager::EmulatedFDManager(FEXCore::Context::Context *ctx)
|
|
: CTX {ctx} {
|
|
EmulatedMap.emplace("/proc/cpuinfo");
|
|
EmulatedMap.emplace("/sys/devices/system/cpu/online");
|
|
|
|
FDReadCreators["/proc/cpuinfo"] = [&](FEXCore::Context::Context *ctx, int32_t fd, const char *pathname, int32_t flags, mode_t mode) -> int32_t {
|
|
FILE *fp = tmpfile();
|
|
fwrite((void*)&cpu_info.at(0), sizeof(uint8_t), cpu_info.size(), fp);
|
|
fseek(fp, 0, SEEK_SET);
|
|
int32_t f = fileno(fp);
|
|
return f;
|
|
};
|
|
auto NumCPUCores = [&](FEXCore::Context::Context *ctx, int32_t fd, const char *pathname, int32_t flags, mode_t mode) -> int32_t {
|
|
FILE *fp = tmpfile();
|
|
fwrite((void*)&cpus_online.at(0), sizeof(uint8_t), cpus_online.size(), fp);
|
|
fseek(fp, 0, SEEK_SET);
|
|
int32_t f = fileno(fp);
|
|
return f;
|
|
};
|
|
|
|
FDReadCreators["/sys/devices/system/cpu/online"] = NumCPUCores;
|
|
FDReadCreators["/sys/devices/system/cpu/present"] = NumCPUCores;
|
|
|
|
string procAuxv = string("/proc/") + std::to_string(getpid()) + string("/auxv");
|
|
EmulatedMap.emplace(procAuxv);
|
|
EmulatedMap.emplace("/proc/self/auxv");
|
|
|
|
FDReadCreators[procAuxv] = &EmulatedFDManager::ProcAuxv;
|
|
FDReadCreators["/proc/self/auxv"] = &EmulatedFDManager::ProcAuxv;
|
|
|
|
cpus_online = "0";
|
|
uint64_t CPUCores = ThreadsConfig();
|
|
if (CPUCores > 1) {
|
|
cpus_online += "-" + std::to_string(CPUCores - 1);
|
|
}
|
|
|
|
cpu_info = GenerateCPUInfo(ctx, CPUCores);
|
|
}
|
|
|
|
EmulatedFDManager::~EmulatedFDManager() {
|
|
}
|
|
|
|
int32_t EmulatedFDManager::OpenAt(int dirfs, const char *pathname, int flags, uint32_t mode) {
|
|
std::error_code ec;
|
|
bool exists = std::filesystem::exists(pathname, ec);
|
|
if (ec) {
|
|
return -1;
|
|
}
|
|
string cpath = exists ? std::filesystem::canonical(pathname)
|
|
: std::filesystem::path(pathname).lexically_normal(); // *Note: this doesn't transform to absolute
|
|
|
|
if (EmulatedMap.find(cpath) == EmulatedMap.end()) {
|
|
return -1;
|
|
}
|
|
|
|
return FDReadCreators[cpath](CTX, dirfs, pathname, flags, mode);
|
|
}
|
|
|
|
int32_t EmulatedFDManager::ProcAuxv(FEXCore::Context::Context* ctx, int32_t fd, const char* pathname, int32_t flags, mode_t mode)
|
|
{
|
|
uint64_t auxvBase=0, auxvSize=0;
|
|
FEX::HLE::_SyscallHandler->GetCodeLoader()->GetAuxv(auxvBase, auxvSize);
|
|
if (!auxvBase) {
|
|
LogMan::Msg::D("Failed to get Auxv stack address");
|
|
return -1;
|
|
}
|
|
|
|
FILE* fp = tmpfile();
|
|
fwrite((void*)auxvBase, 1, auxvSize, fp);
|
|
fseek(fp, 0, SEEK_SET);
|
|
int32_t f = fileno(fp);
|
|
return f;
|
|
}
|
|
}
|
|
|