Ryan Houdek f277025c9a AVX128: Fixes wide shifts ...

During refactoring this was missed and rerunning unittests locally
caught it. 256-bit operations get their shift only from the lower half
of the vector register.

2024-06-26 14:16:39 -07:00

..

Config

Config: Change default TSO options

2024-05-21 18:08:58 -07:00

Context

FEXCore: Implement support for fetching/setting YMM registers

2024-06-21 17:13:56 -04:00

Core

AVX128: Fixes wide shifts

2024-06-26 14:16:39 -07:00

GDBJIT

Whole-tree reformat

2024-04-12 16:26:02 +02:00

HLE/Thunks

IR: specify registers, not offsets for SRA

2024-05-08 14:01:42 -04:00

IR

Merge pull request #3766 from alyssarosenzweig/opt/f16c-round

2024-06-26 14:03:24 -07:00