mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-08 21:00:19 +02:00
Ryan Houdek
9c8438f264
PR #3980 is adding a feature to merge loadstores in to paired loadstores, but it was using the incorrect atomic check to determine if it can safely merge them or not. It was using the GPR atomic check instead of the vector atomic check. While this would improve performance on Apple Silicon with its hardware TSO implementation, it would have had zero impact on Cortex and Oryon. Instead split out the three config options to live as a boolean check in the ContextImpl similar to how we disable "AtomicTSOEmulation". Removing the various configs in the JIT and CPUID so that it queries from the same context. This makes it clearer that if you are wanting the current active configuration for memcpy, vector, or general atomic TSO emulation, you should query one of those three getters. This also fixes a weird edge case bug in the arm64 JIT where you could have TSO emulation disable, but still have vector TSO enabled partially. Just because half a config wasn't checked in {Load,Store}MemTSO for vectors. If the global "TSOEnabled" option is disabled then TSO should always be disabled. Alyssa will be able to pull this in to #3980 once merged and get the performance uplift on Cortex and Oryon, since our default configuration is to have vector and memcpy TSO emulation disabled.
516 lines
19 KiB
C++
516 lines
19 KiB
C++
// SPDX-License-Identifier: MIT
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#pragma once
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#include <FEXCore/Core/CPUID.h>
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#include <FEXCore/Config/Config.h>
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#include <FEXCore/fextl/vector.h>
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#include <cstdint>
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#include <unordered_map>
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#include <utility>
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namespace FEXCore {
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namespace Context {
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class ContextImpl;
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}
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uint32_t GetCycleCounterFrequency();
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// Debugging define to switch what family of CPU we execute as.
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// Might be useful if an application makes an assumption about a CPU.
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// #define CPUID_AMD
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class CPUIDEmu final {
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private:
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constexpr static uint32_t CPUID_VENDOR_INTEL1 = 0x756E6547; // "Genu"
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constexpr static uint32_t CPUID_VENDOR_INTEL2 = 0x49656E69; // "ineI"
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constexpr static uint32_t CPUID_VENDOR_INTEL3 = 0x6C65746E; // "ntel"
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constexpr static uint32_t CPUID_VENDOR_AMD1 = 0x68747541; // "Auth"
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constexpr static uint32_t CPUID_VENDOR_AMD2 = 0x69746E65; // "enti"
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constexpr static uint32_t CPUID_VENDOR_AMD3 = 0x444D4163; // "cAMD"
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public:
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CPUIDEmu(const FEXCore::Context::ContextImpl* ctx);
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// X86 cacheline size effectively has to be hardcoded to 64
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// if we report anything differently then applications are likely to break
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constexpr static uint64_t CACHELINE_SIZE = 64;
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FEXCore::CPUID::FunctionResults RunFunction(uint32_t Function, uint32_t Leaf) const {
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if (Function < Primary.size()) {
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const auto Handler = Primary[Function];
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return (this->*Handler)(Leaf);
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}
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constexpr uint32_t HypervisorBase = 0x4000'0000;
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if (Function >= HypervisorBase && Function < (HypervisorBase + Hypervisor.size())) {
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const auto Handler = Hypervisor[Function - HypervisorBase];
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return (this->*Handler)(Leaf);
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}
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constexpr uint32_t ExtendedBase = 0x8000'0000;
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if (Function >= ExtendedBase && Function < (ExtendedBase + Extended.size())) {
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const auto Handler = Extended[Function - ExtendedBase];
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return (this->*Handler)(Leaf);
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}
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return Function_Reserved(Leaf);
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}
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FEXCore::CPUID::FunctionResults RunFunctionName(uint32_t Function, uint32_t Leaf, uint32_t CPU) const {
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if (Function == 0x8000'0002U) {
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return Function_8000_0002h(Leaf, CPU % PerCPUData.size());
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} else if (Function == 0x8000'0003U) {
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return Function_8000_0003h(Leaf, CPU % PerCPUData.size());
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} else {
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return Function_8000_0004h(Leaf, CPU % PerCPUData.size());
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}
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}
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FEXCore::CPUID::XCRResults RunXCRFunction(uint32_t Function) const {
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if (Function >= 1) {
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// XCR function 1 is not yet supported.
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return {};
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}
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return XCRFunction_0h();
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}
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bool DoesXCRFunctionReportConstantData(uint32_t Function) const {
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// Every function currently returns constant data.
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return true;
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}
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enum class SupportsConstant {
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CONSTANT,
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NONCONSTANT,
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};
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enum class NeedsLeafConstant {
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NEEDSLEAFCONSTANT,
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NOLEAFCONSTANT,
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};
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struct FunctionConstant {
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SupportsConstant SupportsConstantFunction;
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NeedsLeafConstant NeedsLeaf;
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};
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static constexpr FunctionConstant DoesFunctionReportConstantData(uint32_t Function) {
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if (Function < Primary.size()) {
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return Primary_Constant[Function];
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}
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constexpr uint32_t HypervisorBase = 0x4000'0000;
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if (Function >= HypervisorBase && Function < (HypervisorBase + Hypervisor.size())) {
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return Hypervisor_Constant[Function - HypervisorBase];
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}
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constexpr uint32_t ExtendedBase = 0x8000'0000;
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if (Function >= ExtendedBase && Function < (ExtendedBase + Extended.size())) {
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return Extended_Constant[Function - ExtendedBase];
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}
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// Anything unsupported is known constant return of reserved data.
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return {SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT};
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}
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private:
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const FEXCore::Context::ContextImpl* CTX;
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bool Hybrid {};
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uint32_t Cores {};
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FEX_CONFIG_OPT(HideHypervisorBit, HIDEHYPERVISORBIT);
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FEX_CONFIG_OPT(SmallTSCScale, SMALLTSCSCALE);
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// XFEATURE_ENABLED_MASK
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// Mask that configures what features are enabled on the CPU.
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// Affects XSAVE and XRSTOR when modified.
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// Bit layout is as follows.
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// [0] - x87 enabled
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// [1] - SSE enabled
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// [2] - YMM enabled (256-bit SSE)
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// [8:3] - Reserved. MBZ.
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// [9] - MPK
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// [10] - Reserved. MBZ.
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// [11] - CET_U
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// [12] - CET_S
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// [61:13] - Reserved. MBZ.
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// [62] - LWP (Lightweight profiling)
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// [63] - Reserved for XCR bit vector expansion. MBZ.
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// Always enable x87 and SSE by default.
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constexpr static uint64_t XCR0_X87 = 1ULL << 0;
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constexpr static uint64_t XCR0_SSE = 1ULL << 1;
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constexpr static uint64_t XCR0_AVX = 1ULL << 2;
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struct FeaturesConfig {
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uint64_t SHA : 1;
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uint64_t _pad : 63;
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};
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FeaturesConfig Features {
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.SHA = 1,
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};
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uint64_t XCR0 {XCR0_X87 | XCR0_SSE};
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uint32_t SupportsAVX() const {
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return (XCR0 & XCR0_AVX) ? 1 : 0;
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}
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using FunctionHandler = FEXCore::CPUID::FunctionResults (CPUIDEmu::*)(uint32_t Leaf) const;
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struct CPUData {
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const char* ProductName {};
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#ifdef _M_ARM_64
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uint32_t MIDR {};
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#endif
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bool IsBig {};
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};
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fextl::vector<CPUData> PerCPUData {};
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// Functions
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FEXCore::CPUID::FunctionResults Function_0h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_01h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_02h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_04h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_06h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_07h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_0Dh(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_15h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_1Ah(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_4000_0000h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_4000_0001h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_8000_0000h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_8000_0001h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_8000_0002h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_8000_0003h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_8000_0004h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_8000_0002h(uint32_t Leaf, uint32_t CPU) const;
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FEXCore::CPUID::FunctionResults Function_8000_0003h(uint32_t Leaf, uint32_t CPU) const;
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FEXCore::CPUID::FunctionResults Function_8000_0004h(uint32_t Leaf, uint32_t CPU) const;
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FEXCore::CPUID::FunctionResults Function_8000_0005h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_8000_0006h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_8000_0007h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_8000_0008h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_8000_0019h(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_8000_001Dh(uint32_t Leaf) const;
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FEXCore::CPUID::FunctionResults Function_Reserved(uint32_t Leaf) const;
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FEXCore::CPUID::XCRResults XCRFunction_0h() const;
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void SetupHostHybridFlag();
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void SetupFeatures();
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static constexpr size_t PRIMARY_FUNCTION_COUNT = 27;
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static constexpr size_t HYPERVISOR_FUNCTION_COUNT = 2;
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static constexpr size_t EXTENDED_FUNCTION_COUNT = 32;
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static constexpr std::array<FunctionHandler, PRIMARY_FUNCTION_COUNT> Primary = {
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// 0: Highest function parameter and ID
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&CPUIDEmu::Function_0h,
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// 1: Processor info
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&CPUIDEmu::Function_01h,
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// 2: Cache and TLB info
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&CPUIDEmu::Function_02h,
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// 3: Serial Number(previously), now reserved
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&CPUIDEmu::Function_Reserved,
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#ifndef CPUID_AMD
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// 4: Deterministic cache parameters for each level
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&CPUIDEmu::Function_04h,
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#else
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&CPUIDEmu::Function_Reserved,
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#endif
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// 5: Monitor/mwait
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&CPUIDEmu::Function_Reserved,
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// 6: Thermal and power management
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&CPUIDEmu::Function_06h,
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// 7: Extended feature flags
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&CPUIDEmu::Function_07h,
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// 0x08: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 9: Direct Cache Access information
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&CPUIDEmu::Function_Reserved,
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// 0x0A: Architectural performance monitoring
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&CPUIDEmu::Function_Reserved,
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// 0x0B: Extended topology enumeration
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&CPUIDEmu::Function_Reserved,
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// 0x0C: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x0D: Processor extended state enumeration
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&CPUIDEmu::Function_0Dh,
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// 0x0E: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x0F: Intel RDT monitoring
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&CPUIDEmu::Function_Reserved,
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// 0x10: Intel RDT allocation enumeration
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&CPUIDEmu::Function_Reserved,
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// 0x12: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x12: Intel SGX capability enumeration
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&CPUIDEmu::Function_Reserved,
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// 0x13: Reserved
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&CPUIDEmu::Function_Reserved,
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// 0x14: Intel Processor trace
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&CPUIDEmu::Function_Reserved,
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#ifndef CPUID_AMD
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// Timestamp counter information
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// Doesn't exist on AMD hardware
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&CPUIDEmu::Function_15h,
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#else
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&CPUIDEmu::Function_Reserved,
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#endif
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// 0x16: Processor frequency information
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&CPUIDEmu::Function_Reserved,
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// 0x17: SoC vendor attribute enumeration
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&CPUIDEmu::Function_Reserved,
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// 0x18: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x19: Reserved?
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&CPUIDEmu::Function_Reserved,
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#ifndef CPUID_AMD
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// 0x1A: Hybrid Information Sub-leaf
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&CPUIDEmu::Function_1Ah,
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#else
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&CPUIDEmu::Function_Reserved,
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#endif
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};
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static constexpr std::array<FunctionConstant, PRIMARY_FUNCTION_COUNT> Primary_Constant = {{
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// 0: Highest function parameter and ID
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 1: Processor info
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 2: Cache and TLB info
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 3: Serial Number(previously), now reserved
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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#ifndef CPUID_AMD
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// 4: Deterministic cache parameters for each level
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT},
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#else
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// 4: Reserved
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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#endif
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// 5: Monitor/mwait
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 6: Thermal and power management
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 7: Extended feature flags
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT},
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// 0x08: Reserved?
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 9: Direct Cache Access information
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x0A: Architectural performance monitoring
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x0B: Extended topology enumeration
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x0C: Reserved?
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x0D: Processor extended state enumeration
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT},
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// 0x0E: Reserved?
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x0F: Intel RDT monitoring
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x10: Intel RDT allocation enumeration
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x12: Reserved?
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x12: Intel SGX capability enumeration
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x13: Reserved
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x14: Intel Processor trace
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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#ifndef CPUID_AMD
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// 0x15: Timestamp counter information
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// Doesn't exist on AMD hardware
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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#else
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// 0x15: Reserved
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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#endif
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// 0x16: Processor frequency information
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x17: SoC vendor attribute enumeration
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x18: Reserved?
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// 0x19: Reserved?
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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#ifndef CPUID_AMD
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// 0x1A: Hybrid Information Sub-leaf
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{SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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#else
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// 0x1A: Reserved
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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#endif
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}};
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static constexpr std::array<FunctionHandler, HYPERVISOR_FUNCTION_COUNT> Hypervisor = {
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// Hypervisor CPUID information leaf
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&CPUIDEmu::Function_4000_0000h,
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// FEX-Emu specific leaf
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&CPUIDEmu::Function_4000_0001h,
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};
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static constexpr std::array<FunctionConstant, HYPERVISOR_FUNCTION_COUNT> Hypervisor_Constant = {{
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// Hypervisor CPUID information leaf
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
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// FEX-Emu specific leaf
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{SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT},
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}};
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static constexpr std::array<FunctionHandler, EXTENDED_FUNCTION_COUNT> Extended = {
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// Largest extended function number
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&CPUIDEmu::Function_8000_0000h,
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// Processor vendor
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&CPUIDEmu::Function_8000_0001h,
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// Processor brand string
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&CPUIDEmu::Function_8000_0002h,
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// Processor brand string continued
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&CPUIDEmu::Function_8000_0003h,
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// Processor brand string continued
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&CPUIDEmu::Function_8000_0004h,
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#ifdef CPUID_AMD
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// 0x8000'0005: L1 Cache and TLB identifiers
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&CPUIDEmu::Function_8000_0005h,
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#else
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&CPUIDEmu::Function_Reserved,
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#endif
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// 0x8000'0006: L2 Cache identifiers
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&CPUIDEmu::Function_8000_0006h,
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// 0x8000'0007: Advanced power management information
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&CPUIDEmu::Function_8000_0007h,
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// 0x8000'0008: Virtual and physical address sizes
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&CPUIDEmu::Function_8000_0008h,
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// 0x8000'0009: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'000A: SVM Revision
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&CPUIDEmu::Function_Reserved,
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// 0x8000'000B: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'000C: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'000D: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'000E: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'000F: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'0010: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'0011: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'0012: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'0013: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'0014: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'0015: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'0016: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'0017: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'0018: Reserved?
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&CPUIDEmu::Function_Reserved,
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// 0x8000'0019: TLB 1GB page identifiers
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&CPUIDEmu::Function_8000_0019h,
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// 0x8000'001A: Performance optimization identifiers
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&CPUIDEmu::Function_Reserved,
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// 0x8000'001B: Instruction based sampling identifiers
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&CPUIDEmu::Function_Reserved,
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// 0x8000'001C: Lightweight profiling capabilities
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&CPUIDEmu::Function_Reserved,
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#ifdef CPUID_AMD
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// 0x8000'001D: Cache properties
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&CPUIDEmu::Function_8000_001Dh,
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#else
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&CPUIDEmu::Function_Reserved,
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#endif
|
|
// 0x8000'001E: Extended APIC ID
|
|
&CPUIDEmu::Function_Reserved,
|
|
// 0x8000'001F: AMD Secure Encryption
|
|
&CPUIDEmu::Function_Reserved,
|
|
};
|
|
|
|
static constexpr std::array<FunctionConstant, EXTENDED_FUNCTION_COUNT> Extended_Constant = {{
|
|
// Largest extended function number
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|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// Processor vendor
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// Processor brand string
|
|
{SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// Processor brand string continued
|
|
{SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// Processor brand string continued
|
|
{SupportsConstant::NONCONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
#ifdef CPUID_AMD
|
|
// 0x8000'0005: L1 Cache and TLB identifiers
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
#else
|
|
// 0x8000'0005: Reserved
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
#endif
|
|
// 0x8000'0006: L2 Cache identifiers
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0007: Advanced power management information
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0008: Virtual and physical address sizes
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0009: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'000A: SVM Revision
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'000B: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'000C: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'000D: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'000E: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'000F: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0010: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0011: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0012: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0013: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0014: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0015: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0016: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0017: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0018: Reserved?
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'0019: TLB 1GB page identifiers
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'001A: Performance optimization identifiers
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'001B: Instruction based sampling identifiers
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'001C: Lightweight profiling capabilities
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
#ifdef CPUID_AMD
|
|
// 0x8000'001D: Cache properties
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NEEDSLEAFCONSTANT},
|
|
#else
|
|
// 0x8000'001D: Reserved
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
#endif
|
|
// 0x8000'001E: Extended APIC ID
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
// 0x8000'001F: AMD Secure Encryption
|
|
{SupportsConstant::CONSTANT, NeedsLeafConstant::NOLEAFCONSTANT},
|
|
}};
|
|
};
|
|
} // namespace FEXCore
|