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Ryan Houdek
9c8438f264
PR #3980 is adding a feature to merge loadstores in to paired loadstores, but it was using the incorrect atomic check to determine if it can safely merge them or not. It was using the GPR atomic check instead of the vector atomic check. While this would improve performance on Apple Silicon with its hardware TSO implementation, it would have had zero impact on Cortex and Oryon. Instead split out the three config options to live as a boolean check in the ContextImpl similar to how we disable "AtomicTSOEmulation". Removing the various configs in the JIT and CPUID so that it queries from the same context. This makes it clearer that if you are wanting the current active configuration for memcpy, vector, or general atomic TSO emulation, you should query one of those three getters. This also fixes a weird edge case bug in the arm64 JIT where you could have TSO emulation disable, but still have vector TSO enabled partially. Just because half a config wasn't checked in {Load,Store}MemTSO for vectors. If the global "TSOEnabled" option is disabled then TSO should always be disabled. Alyssa will be able to pull this in to #3980 once merged and get the performance uplift on Cortex and Oryon, since our default configuration is to have vector and memcpy TSO emulation disabled.