mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 12:00:17 +02:00
1624 lines
41 KiB
JSON
1624 lines
41 KiB
JSON
{
|
|
"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [],
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|
"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"AFP",
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"FCMA",
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"FLAGM",
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"FLAGM2"
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|
]
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},
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|
"Instructions": {
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"movupd xmm0, xmm0": {
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"ExpectedInstructionCount": 0,
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|
"Comment": "0x66 0x0f 0x10",
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"ExpectedArm64ASM": []
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|
},
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|
"movupd xmm0, xmm1": {
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|
"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x10",
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|
"ExpectedArm64ASM": [
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|
"mov v16.16b, v17.16b"
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|
]
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},
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|
"movupd xmm0, [rax]": {
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|
"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x10",
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"ExpectedArm64ASM": [
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|
"ldr q16, [x4]"
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|
]
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|
},
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|
"movupd [rax], xmm0": {
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"ExpectedInstructionCount": 1,
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"Comment": "0x66 0x0f 0x11",
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"ExpectedArm64ASM": [
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|
"str q16, [x4]"
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]
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},
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|
"movlpd xmm0, [rax]": {
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"ExpectedInstructionCount": 1,
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"Comment": "0x66 0x0f 0x12",
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"ExpectedArm64ASM": [
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|
"ld1 {v16.d}[0], [x4]"
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]
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|
},
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|
"movlpd [rax], xmm0": {
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|
"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x13",
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"ExpectedArm64ASM": [
|
|
"str d16, [x4]"
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|
]
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|
},
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|
"unpcklpd xmm0, xmm1": {
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|
"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x14",
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|
"ExpectedArm64ASM": [
|
|
"zip1 v16.2d, v16.2d, v17.2d"
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|
]
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|
},
|
|
"unpckhpd xmm0, xmm1": {
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|
"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x15",
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|
"ExpectedArm64ASM": [
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|
"zip2 v16.2d, v16.2d, v17.2d"
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|
]
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},
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|
"movhpd xmm0, [rax]": {
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|
"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x16",
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"ExpectedArm64ASM": [
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|
"ld1 {v16.d}[1], [x4]"
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]
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|
},
|
|
"movhpd [rax], xmm0": {
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"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x17",
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|
"ExpectedArm64ASM": [
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|
"st1 {v16.d}[1], [x4]"
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]
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},
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|
"movapd xmm0, xmm0": {
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"ExpectedInstructionCount": 0,
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|
"Comment": "0x66 0x0f 0x28",
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"ExpectedArm64ASM": []
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|
},
|
|
"movapd xmm0, xmm1": {
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|
"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x28",
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"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b"
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]
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},
|
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"movapd xmm0, [rax]": {
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"ExpectedInstructionCount": 1,
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"Comment": "0x66 0x0f 0x28",
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"ExpectedArm64ASM": [
|
|
"ldr q16, [x4]"
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|
]
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|
},
|
|
"movapd [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x29",
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|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
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|
]
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|
},
|
|
"cvtpi2pd xmm0, mm0": {
|
|
"ExpectedInstructionCount": 3,
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|
"Comment": "0x66 0x0f 0x2a",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #1040]",
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|
"sxtl v2.2d, v2.2s",
|
|
"scvtf v16.2d, v2.2d"
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|
]
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},
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|
"movntpd [rax], xmm0": {
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"ExpectedInstructionCount": 1,
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"Comment": "0x66 0x0f 0x2b",
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|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
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|
]
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|
},
|
|
"cvttpd2pi mm0, xmm0": {
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|
"ExpectedInstructionCount": 11,
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|
"Comment": "0x66 0x0f 0x2c",
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|
"ExpectedArm64ASM": [
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|
"ldr d2, [x28, #2880]",
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|
"ldr q3, [x28, #2832]",
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|
"frintz v4.2d, v16.2d",
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|
"fcvtn v4.2s, v4.2d",
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|
"fcvtzs v4.2s, v4.2s",
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"fcmgt v3.2d, v3.2d, v16.2d",
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|
"shrn v3.2s, v3.2d, #32",
|
|
"bit v2.8b, v4.8b, v3.8b",
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"str d2, [x28, #1040]",
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"mov w20, #0xffff",
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"strh w20, [x28, #1048]"
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]
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},
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"cvtpd2pi mm0, xmm0": {
|
|
"ExpectedInstructionCount": 12,
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|
"Comment": "0x66 0x0f 0x2d",
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"ExpectedArm64ASM": [
|
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"frinti v2.2d, v16.2d",
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|
"ldr d3, [x28, #2880]",
|
|
"ldr q4, [x28, #2832]",
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"frintz v5.2d, v2.2d",
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"fcvtn v5.2s, v5.2d",
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"fcvtzs v5.2s, v5.2s",
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"fcmgt v2.2d, v4.2d, v2.2d",
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"shrn v2.2s, v2.2d, #32",
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"bsl v2.8b, v5.8b, v3.8b",
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"str d2, [x28, #1040]",
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"mov w20, #0xffff",
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"strh w20, [x28, #1048]"
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]
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},
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"ucomisd xmm0, xmm1": {
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"ExpectedInstructionCount": 5,
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"Comment": "0x66 0x0f 0x2e",
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"ExpectedArm64ASM": [
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"fcmp d16, d17",
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"mov w27, #0x0",
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"cset w26, vc",
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"csetm x0, eq",
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"ccmn x26, x0, #nzCv, le"
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]
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},
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"comisd xmm0, xmm1": {
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"ExpectedInstructionCount": 5,
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"Comment": "0x66 0x0f 0x2f",
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"ExpectedArm64ASM": [
|
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"fcmp d16, d17",
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"mov w27, #0x0",
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"cset w26, vc",
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"csetm x0, eq",
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"ccmn x26, x0, #nzCv, le"
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]
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},
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"movmskpd eax, xmm0": {
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"ExpectedInstructionCount": 4,
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"Comment": "0x66 0x0f 0x50",
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"ExpectedArm64ASM": [
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"uzp2 v2.4s, v16.4s, v16.4s",
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"mov x20, v2.d[0]",
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|
"bfi x20, x20, #31, #32",
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|
"lsr x4, x20, #62"
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]
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},
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"sqrtpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x51",
|
|
"ExpectedArm64ASM": [
|
|
"fsqrt v16.2d, v17.2d"
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|
]
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},
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|
"addpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x58",
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|
"ExpectedArm64ASM": [
|
|
"fadd v16.2d, v16.2d, v17.2d"
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|
]
|
|
},
|
|
"mulpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x59",
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|
"ExpectedArm64ASM": [
|
|
"fmul v16.2d, v16.2d, v17.2d"
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|
]
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|
},
|
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"cvtpd2ps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
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|
"Comment": "0x66 0x0f 0x5a",
|
|
"ExpectedArm64ASM": [
|
|
"fcvtn v16.2s, v17.2d"
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|
]
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|
},
|
|
"cvtpd2ps xmm0, [rax]": {
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"ExpectedInstructionCount": 2,
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|
"Comment": "0xf2 0x0f 0x5a",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"fcvtn v16.2s, v2.2d"
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|
]
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},
|
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"cvtps2dq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 7,
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|
"Comment": "0x66 0x0f 0x5b",
|
|
"ExpectedArm64ASM": [
|
|
"frinti v2.4s, v17.4s",
|
|
"ldr q3, [x28, #2880]",
|
|
"ldr q4, [x28, #2784]",
|
|
"fcvtzs v5.4s, v2.4s",
|
|
"fcmgt v2.4s, v4.4s, v2.4s",
|
|
"mov v16.16b, v2.16b",
|
|
"bsl v16.16b, v5.16b, v3.16b"
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|
]
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},
|
|
"cvtps2dq xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0xf2 0x0f 0x5b",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"frinti v2.4s, v2.4s",
|
|
"ldr q3, [x28, #2880]",
|
|
"ldr q4, [x28, #2784]",
|
|
"fcvtzs v5.4s, v2.4s",
|
|
"fcmgt v2.4s, v4.4s, v2.4s",
|
|
"mov v16.16b, v2.16b",
|
|
"bsl v16.16b, v5.16b, v3.16b"
|
|
]
|
|
},
|
|
"subpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x5c",
|
|
"ExpectedArm64ASM": [
|
|
"fsub v16.2d, v16.2d, v17.2d"
|
|
]
|
|
},
|
|
"minpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0x5d",
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v0.2d, v17.2d, v16.2d",
|
|
"bif v16.16b, v17.16b, v0.16b"
|
|
]
|
|
},
|
|
"divpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x5e",
|
|
"ExpectedArm64ASM": [
|
|
"fdiv v16.2d, v16.2d, v17.2d"
|
|
]
|
|
},
|
|
"maxpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0x5f",
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v0.2d, v17.2d, v16.2d",
|
|
"bit v16.16b, v17.16b, v0.16b"
|
|
]
|
|
},
|
|
"punpcklbw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x60",
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"punpcklbw xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0x60",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"zip1 v16.16b, v16.16b, v2.16b"
|
|
]
|
|
},
|
|
"punpcklwd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x61",
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"punpcklwd xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0x61",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"zip1 v16.8h, v16.8h, v2.8h"
|
|
]
|
|
},
|
|
"punpckldq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x62",
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.4s, v16.4s, v17.4s"
|
|
]
|
|
},
|
|
"punpckldq xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0x62",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"zip1 v16.4s, v16.4s, v2.4s"
|
|
]
|
|
},
|
|
"packsswb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0x63",
|
|
"ExpectedArm64ASM": [
|
|
"sqxtn v16.8b, v16.8h",
|
|
"sqxtn2 v16.16b, v17.8h"
|
|
]
|
|
},
|
|
"packsswb xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x66 0x0f 0x63",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"sqxtn v16.8b, v16.8h",
|
|
"sqxtn2 v16.16b, v2.8h"
|
|
]
|
|
},
|
|
"packsswb xmm0, xmm0": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x66 0x0f 0x63",
|
|
"ExpectedArm64ASM": [
|
|
"mov v0.16b, v16.16b",
|
|
"sqxtn v16.8b, v16.8h",
|
|
"sqxtn2 v16.16b, v0.8h"
|
|
]
|
|
},
|
|
"pcmpgtb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x64",
|
|
"ExpectedArm64ASM": [
|
|
"cmgt v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"pcmpgtw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x65",
|
|
"ExpectedArm64ASM": [
|
|
"cmgt v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pcmpgtd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x66",
|
|
"ExpectedArm64ASM": [
|
|
"cmgt v16.4s, v16.4s, v17.4s"
|
|
]
|
|
},
|
|
"punpckhbw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x68",
|
|
"ExpectedArm64ASM": [
|
|
"zip2 v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"punpckhbw xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0x68",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"zip2 v16.16b, v16.16b, v2.16b"
|
|
]
|
|
},
|
|
"punpckhwd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x69",
|
|
"ExpectedArm64ASM": [
|
|
"zip2 v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"punpckhwd xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0x69",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"zip2 v16.8h, v16.8h, v2.8h"
|
|
]
|
|
},
|
|
"punpckhdq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x6a",
|
|
"ExpectedArm64ASM": [
|
|
"zip2 v16.4s, v16.4s, v17.4s"
|
|
]
|
|
},
|
|
"punpckhdq xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0x6a",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"zip2 v16.4s, v16.4s, v2.4s"
|
|
]
|
|
},
|
|
"packssdw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0x6b",
|
|
"ExpectedArm64ASM": [
|
|
"sqxtn v16.4h, v16.4s",
|
|
"sqxtn2 v16.8h, v17.4s"
|
|
]
|
|
},
|
|
"punpcklqdq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x6c",
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.2d, v16.2d, v17.2d"
|
|
]
|
|
},
|
|
"punpckhqdq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x6d",
|
|
"ExpectedArm64ASM": [
|
|
"zip2 v16.2d, v16.2d, v17.2d"
|
|
]
|
|
},
|
|
"movd xmm0, dword [rax]": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x6e",
|
|
"ExpectedArm64ASM": [
|
|
"ldr s16, [x4]"
|
|
]
|
|
},
|
|
"movd xmm0, eax": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x6e",
|
|
"ExpectedArm64ASM": [
|
|
"fmov s16, w4"
|
|
]
|
|
},
|
|
"movq xmm0, qword [rax]": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x6e",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d16, [x4]"
|
|
]
|
|
},
|
|
"movq xmm0, rax": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x6e",
|
|
"ExpectedArm64ASM": [
|
|
"fmov d16, x4"
|
|
]
|
|
},
|
|
"movdqa xmm0, xmm0": {
|
|
"ExpectedInstructionCount": 0,
|
|
"Comment": "0x66 0x0f 0x6f",
|
|
"ExpectedArm64ASM": []
|
|
},
|
|
"movdqa xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x6f",
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"movdqa xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x6f",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q16, [x4]"
|
|
]
|
|
},
|
|
"pshufd xmm0, xmm1, 0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Broadcast element 0",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"dup v16.4s, v17.s[0]"
|
|
]
|
|
},
|
|
"pshufd xmm0, xmm1, 11100100b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Identity copy",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"pshufd xmm0, xmm1, 01010000b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Zip with self",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.4s, v17.4s, v17.4s"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 0": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Broadcast element 0 from memory",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"dup v16.4s, v2.s[0]"
|
|
]
|
|
},
|
|
"pshufd xmm0, xmm1, 1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Broadcast element 0",
|
|
"Element 0 becomes element 1",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr x0, [x28, #2064]",
|
|
"ldr q2, [x0, #16]",
|
|
"tbl v16.16b, {v17.16b}, v2.16b"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Broadcast element 0 from Memory",
|
|
"Element 0 becomes element 1",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"ldr x0, [x28, #2064]",
|
|
"ldr q3, [x0, #16]",
|
|
"tbl v16.16b, {v2.16b}, v3.16b"
|
|
]
|
|
},
|
|
"pshufd xmm0, xmm1, 0xff": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": [
|
|
"Broadcast element 3",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"dup v16.4s, v17.s[3]"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 0xff": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Broadcast element 3 from memory",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"dup v16.4s, v2.s[3]"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 00_00_11_10b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Inverse elements",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"dup v3.4s, v2.s[0]",
|
|
"ext v16.16b, v2.16b, v3.16b, #8"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 00_01_00_01b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Weird reversed low elements and broadcast",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"rev64 v2.4s, v2.4s",
|
|
"zip1 v16.2d, v2.2d, v2.2d"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 00_01_10_11b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Inverse elements",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"rev64 v2.4s, v2.4s",
|
|
"ext v16.16b, v2.16b, v2.16b, #8"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 00_10_00_10b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Weird reversed even elements and broadcast",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"uzp1 v2.4s, v2.4s, v2.4s",
|
|
"ext v16.16b, v2.16b, v2.16b, #4"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 00_11_00_11b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Weird Low plus high element reversed and broadcast",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"ext v2.16b, v2.16b, v2.16b, #4",
|
|
"zip2 v16.2d, v2.2d, v2.2d"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 00_11_10_01b": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Vector rotate - One element",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"ext v16.16b, v2.16b, v2.16b, #4"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 01_00_01_00b": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Duplicate bottom 64-bits",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"dup v16.2d, v2.d[0]"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 01_00_11_10b": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Vector rotate - Two elements",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"ext v16.16b, v2.16b, v2.16b, #8"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 10_00_10_00b": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Even elements broadcast",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"uzp1 v16.4s, v2.4s, v2.4s"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 10_01_10_11b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Vector rotate - Three elements",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"ldr x0, [x28, #2064]",
|
|
"ldr q3, [x0, #2480]",
|
|
"tbl v16.16b, {v2.16b}, v3.16b"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 01_10_01_10b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Weird middle elements swizzle plus broadcast",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"ext v2.16b, v2.16b, v2.16b, #4",
|
|
"rev64 v2.4s, v2.4s",
|
|
"zip1 v16.2d, v2.2d, v2.2d"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 01_11_01_11b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Weird reversed upper elements and broadcast",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"uzp2 v2.4s, v2.4s, v2.4s",
|
|
"ext v16.16b, v2.16b, v2.16b, #4"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 10_01_10_01b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Middle two elements broadcast",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"ext v2.16b, v2.16b, v2.16b, #4",
|
|
"zip1 v16.2d, v2.2d, v2.2d"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 10_11_00_01b": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Inverse elements",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"rev64 v16.4s, v2.4s"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 10_11_10_11b": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": [
|
|
"Weird top two elements reverse and broadcast",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"zip2 v2.2d, v2.2d, v2.2d",
|
|
"ext v16.16b, v2.16b, v2.16b, #4"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 11_00_11_00b": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": [
|
|
"Weird low plus high element broadcast",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"ext v2.16b, v2.16b, v2.16b, #4",
|
|
"zip2 v2.2d, v2.2d, v2.2d",
|
|
"ext v16.16b, v2.16b, v2.16b, #4"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 11_01_11_01b": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Odd elements broadcast",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"uzp2 v16.4s, v2.4s, v2.4s"
|
|
]
|
|
},
|
|
"pshufd xmm0, [rax], 11_10_11_10b": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": [
|
|
"Duplicate Top 64-bits",
|
|
"0x66 0x0f 0x70"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"dup v16.2d, v2.d[1]"
|
|
]
|
|
},
|
|
"pcmpeqb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x74",
|
|
"ExpectedArm64ASM": [
|
|
"cmeq v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"pcmpeqw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x75",
|
|
"ExpectedArm64ASM": [
|
|
"cmeq v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pcmpeqd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x76",
|
|
"ExpectedArm64ASM": [
|
|
"cmeq v16.4s, v16.4s, v17.4s"
|
|
]
|
|
},
|
|
"extrq xmm0, 64, 0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"SSE4a",
|
|
"0x66 0x0f 0x78"
|
|
]
|
|
},
|
|
"extrq xmm0, 32, 32": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"SSE4a",
|
|
"0x66 0x0f 0x78"
|
|
]
|
|
},
|
|
"extrq xmm0, 0, 0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"SSE4a",
|
|
"0x66 0x0f 0x78"
|
|
]
|
|
},
|
|
"extrq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"SSE4a",
|
|
"0x66 0x0f 0x79"
|
|
]
|
|
},
|
|
"haddpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x7c",
|
|
"ExpectedArm64ASM": [
|
|
"faddp v16.2d, v16.2d, v17.2d"
|
|
]
|
|
},
|
|
"hsubpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x66 0x0f 0x7c",
|
|
"ExpectedArm64ASM": [
|
|
"uzp1 v2.2d, v16.2d, v17.2d",
|
|
"uzp2 v3.2d, v16.2d, v17.2d",
|
|
"fsub v16.2d, v2.2d, v3.2d"
|
|
]
|
|
},
|
|
"movd eax, xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x7e",
|
|
"ExpectedArm64ASM": [
|
|
"mov w4, v16.s[0]"
|
|
]
|
|
},
|
|
"movq rax, xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x7e",
|
|
"ExpectedArm64ASM": [
|
|
"mov x4, v16.d[0]"
|
|
]
|
|
},
|
|
"movd dword [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x7e",
|
|
"ExpectedArm64ASM": [
|
|
"str s16, [x4]"
|
|
]
|
|
},
|
|
"movq qword [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x7e",
|
|
"ExpectedArm64ASM": [
|
|
"str d16, [x4]"
|
|
]
|
|
},
|
|
"movdqa [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0x7f",
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
|
|
]
|
|
},
|
|
"cmppd xmm0, xmm1, 0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc2",
|
|
"ExpectedArm64ASM": [
|
|
"fcmeq v16.2d, v16.2d, v17.2d"
|
|
]
|
|
},
|
|
"cmppd xmm0, xmm1, 1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc2",
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v16.2d, v17.2d, v16.2d"
|
|
]
|
|
},
|
|
"cmppd xmm0, xmm1, 2": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc2",
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v16.2d, v17.2d, v16.2d"
|
|
]
|
|
},
|
|
"cmppd xmm0, xmm1, 3": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x66 0x0f 0xc2",
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v0.2d, v16.2d, v17.2d",
|
|
"fcmgt v1.2d, v17.2d, v16.2d",
|
|
"orr v16.16b, v0.16b, v1.16b",
|
|
"mvn v16.16b, v16.16b"
|
|
]
|
|
},
|
|
"cmppd xmm0, xmm1, 4": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0xc2",
|
|
"ExpectedArm64ASM": [
|
|
"fcmeq v16.2d, v16.2d, v17.2d",
|
|
"mvn v16.16b, v16.16b"
|
|
]
|
|
},
|
|
"cmppd xmm0, xmm1, 5": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0xc2",
|
|
"ExpectedArm64ASM": [
|
|
"fcmgt v2.2d, v17.2d, v16.2d",
|
|
"mvn v16.16b, v2.16b"
|
|
]
|
|
},
|
|
"cmppd xmm0, xmm1, 6": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x66 0x0f 0xc2",
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v2.2d, v17.2d, v16.2d",
|
|
"mvn v16.16b, v2.16b"
|
|
]
|
|
},
|
|
"cmppd xmm0, xmm1, 7": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x66 0x0f 0xc2",
|
|
"ExpectedArm64ASM": [
|
|
"fcmge v0.2d, v16.2d, v17.2d",
|
|
"fcmgt v1.2d, v17.2d, v16.2d",
|
|
"orr v16.16b, v0.16b, v1.16b"
|
|
]
|
|
},
|
|
"pinsrw xmm0, eax, 000b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.h[0], w4"
|
|
]
|
|
},
|
|
"pinsrw xmm0, eax, 001b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.h[1], w4"
|
|
]
|
|
},
|
|
"pinsrw xmm0, eax, 010b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.h[2], w4"
|
|
]
|
|
},
|
|
"pinsrw xmm0, eax, 011b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.h[3], w4"
|
|
]
|
|
},
|
|
"pinsrw xmm0, eax, 100b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.h[4], w4"
|
|
]
|
|
},
|
|
"pinsrw xmm0, eax, 101b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.h[5], w4"
|
|
]
|
|
},
|
|
"pinsrw xmm0, eax, 110b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.h[6], w4"
|
|
]
|
|
},
|
|
"pinsrw xmm0, eax, 111b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.h[7], w4"
|
|
]
|
|
},
|
|
"pinsrw xmm0, [rax], 000b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"ld1 {v16.h}[0], [x4]"
|
|
]
|
|
},
|
|
"pinsrw xmm0, [rax], 001b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"ld1 {v16.h}[1], [x4]"
|
|
]
|
|
},
|
|
"pinsrw xmm0, [rax], 010b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"ld1 {v16.h}[2], [x4]"
|
|
]
|
|
},
|
|
"pinsrw xmm0, [rax], 011b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"ld1 {v16.h}[3], [x4]"
|
|
]
|
|
},
|
|
"pinsrw xmm0, [rax], 100b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"ld1 {v16.h}[4], [x4]"
|
|
]
|
|
},
|
|
"pinsrw xmm0, [rax], 101b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"ld1 {v16.h}[5], [x4]"
|
|
]
|
|
},
|
|
"pinsrw xmm0, [rax], 110b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"ld1 {v16.h}[6], [x4]"
|
|
]
|
|
},
|
|
"pinsrw xmm0, [rax], 111b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc4",
|
|
"ExpectedArm64ASM": [
|
|
"ld1 {v16.h}[7], [x4]"
|
|
]
|
|
},
|
|
"pextrw eax, xmm0, 000b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"umov w4, v16.h[0]"
|
|
]
|
|
},
|
|
"pextrw eax, xmm0, 001b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"umov w4, v16.h[1]"
|
|
]
|
|
},
|
|
"pextrw eax, xmm0, 010b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"umov w4, v16.h[2]"
|
|
]
|
|
},
|
|
"pextrw eax, xmm0, 011b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"umov w4, v16.h[3]"
|
|
]
|
|
},
|
|
"pextrw eax, xmm0, 100b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"umov w4, v16.h[4]"
|
|
]
|
|
},
|
|
"pextrw eax, xmm0, 101b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"umov w4, v16.h[5]"
|
|
]
|
|
},
|
|
"pextrw eax, xmm0, 110b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"umov w4, v16.h[6]"
|
|
]
|
|
},
|
|
"pextrw eax, xmm0, 111b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"umov w4, v16.h[7]"
|
|
]
|
|
},
|
|
"pextrw [rax], xmm0, 000b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.h}[0], [x4]"
|
|
]
|
|
},
|
|
"pextrw [rax], xmm0, 001b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.h}[1], [x4]"
|
|
]
|
|
},
|
|
"pextrw [rax], xmm0, 010b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.h}[2], [x4]"
|
|
]
|
|
},
|
|
"pextrw [rax], xmm0, 011b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.h}[3], [x4]"
|
|
]
|
|
},
|
|
"pextrw [rax], xmm0, 100b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.h}[4], [x4]"
|
|
]
|
|
},
|
|
"pextrw [rax], xmm0, 101b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.h}[5], [x4]"
|
|
]
|
|
},
|
|
"pextrw [rax], xmm0, 110b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.h}[6], [x4]"
|
|
]
|
|
},
|
|
"pextrw [rax], xmm0, 111b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc5",
|
|
"ExpectedArm64ASM": [
|
|
"st1 {v16.h}[7], [x4]"
|
|
]
|
|
},
|
|
"shufpd xmm0, xmm1, 00b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc6",
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v16.2d, v16.2d, v17.2d"
|
|
]
|
|
},
|
|
"shufpd xmm0, xmm1, 01b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc6",
|
|
"ExpectedArm64ASM": [
|
|
"ext v16.16b, v16.16b, v17.16b, #8"
|
|
]
|
|
},
|
|
"shufpd xmm0, xmm1, 10b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc6",
|
|
"ExpectedArm64ASM": [
|
|
"mov v16.d[1], v17.d[1]"
|
|
]
|
|
},
|
|
"shufpd xmm0, xmm1, 11b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc6",
|
|
"ExpectedArm64ASM": [
|
|
"zip2 v16.2d, v16.2d, v17.2d"
|
|
]
|
|
},
|
|
"shufpd xmm1, xmm0, 00b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc6",
|
|
"ExpectedArm64ASM": [
|
|
"zip1 v17.2d, v17.2d, v16.2d"
|
|
]
|
|
},
|
|
"shufpd xmm1, xmm0, 01b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc6",
|
|
"ExpectedArm64ASM": [
|
|
"ext v17.16b, v17.16b, v16.16b, #8"
|
|
]
|
|
},
|
|
"shufpd xmm1, xmm0, 10b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc6",
|
|
"ExpectedArm64ASM": [
|
|
"mov v17.d[1], v16.d[1]"
|
|
]
|
|
},
|
|
"shufpd xmm1, xmm0, 11b": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xc6",
|
|
"ExpectedArm64ASM": [
|
|
"zip2 v17.2d, v17.2d, v16.2d"
|
|
]
|
|
},
|
|
"addsubpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x66 0x0f 0xd0",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #2432]",
|
|
"eor v2.16b, v17.16b, v2.16b",
|
|
"fadd v16.2d, v16.2d, v2.2d"
|
|
]
|
|
},
|
|
"psrlw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x66 0x0f 0xd1",
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d17, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"neg v0.8h, v0.8h",
|
|
"ushl v16.8h, v16.8h, v0.8h"
|
|
]
|
|
},
|
|
"psrld xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x66 0x0f 0xd2",
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d17, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"neg v0.4s, v0.4s",
|
|
"ushl v16.4s, v16.4s, v0.4s"
|
|
]
|
|
},
|
|
"psrlq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x66 0x0f 0xd3",
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d17, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.2d, v0.d[0]",
|
|
"neg v0.2d, v0.2d",
|
|
"ushl v16.2d, v16.2d, v0.2d"
|
|
]
|
|
},
|
|
"paddq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xd4",
|
|
"ExpectedArm64ASM": [
|
|
"add v16.2d, v16.2d, v17.2d"
|
|
]
|
|
},
|
|
"pmullw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xd3",
|
|
"ExpectedArm64ASM": [
|
|
"mul v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pmovmskb eax, xmm0": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x66 0x0f 0xd7",
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x28, #2656]",
|
|
"cmlt v3.16b, v16.16b, #0",
|
|
"and v2.16b, v3.16b, v2.16b",
|
|
"addp v2.16b, v2.16b, v2.16b",
|
|
"addp v2.8b, v2.8b, v2.8b",
|
|
"addp v2.8b, v2.8b, v2.8b",
|
|
"umov w4, v2.h[0]"
|
|
]
|
|
},
|
|
"psubusb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xd8",
|
|
"ExpectedArm64ASM": [
|
|
"uqsub v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"psubusw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xd9",
|
|
"ExpectedArm64ASM": [
|
|
"uqsub v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pminub xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xda",
|
|
"ExpectedArm64ASM": [
|
|
"umin v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"pand xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xdb",
|
|
"ExpectedArm64ASM": [
|
|
"and v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"paddusb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xdc",
|
|
"ExpectedArm64ASM": [
|
|
"uqadd v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"paddusw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xdd",
|
|
"ExpectedArm64ASM": [
|
|
"uqadd v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pmaxub xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xde",
|
|
"ExpectedArm64ASM": [
|
|
"umax v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"pandn xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xdf",
|
|
"ExpectedArm64ASM": [
|
|
"bic v16.16b, v17.16b, v16.16b"
|
|
]
|
|
},
|
|
"pavgb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xe0",
|
|
"ExpectedArm64ASM": [
|
|
"urhadd v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"psraw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x66 0x0f 0xe1",
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d17, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"neg v0.8h, v0.8h",
|
|
"sshl v16.8h, v16.8h, v0.8h"
|
|
]
|
|
},
|
|
"psrad xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x66 0x0f 0xe2",
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d17, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"neg v0.4s, v0.4s",
|
|
"sshl v16.4s, v16.4s, v0.4s"
|
|
]
|
|
},
|
|
"pavgw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xe3",
|
|
"ExpectedArm64ASM": [
|
|
"urhadd v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pmulhuw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x66 0x0f 0xe4",
|
|
"ExpectedArm64ASM": [
|
|
"umull2 v0.4s, v16.8h, v17.8h",
|
|
"umull v16.4s, v16.4h, v17.4h",
|
|
"uzp2 v16.8h, v16.8h, v0.8h"
|
|
]
|
|
},
|
|
"pmulhw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x66 0x0f 0xe5",
|
|
"ExpectedArm64ASM": [
|
|
"smull2 v0.4s, v16.8h, v17.8h",
|
|
"smull v16.4s, v16.4h, v17.4h",
|
|
"uzp2 v16.8h, v16.8h, v0.8h"
|
|
]
|
|
},
|
|
"cvttpd2dq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x66 0x0f 0xe6",
|
|
"ExpectedArm64ASM": [
|
|
"ldr d2, [x28, #2880]",
|
|
"ldr q3, [x28, #2832]",
|
|
"frintz v4.2d, v17.2d",
|
|
"fcvtn v4.2s, v4.2d",
|
|
"fcvtzs v4.2s, v4.2s",
|
|
"fcmgt v3.2d, v3.2d, v17.2d",
|
|
"shrn v3.2s, v3.2d, #32",
|
|
"mov v16.16b, v3.16b",
|
|
"bsl v16.16b, v4.16b, v2.16b"
|
|
]
|
|
},
|
|
"movntdq [rax], xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xe7",
|
|
"ExpectedArm64ASM": [
|
|
"str q16, [x4]"
|
|
]
|
|
},
|
|
"psubsb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xe8",
|
|
"ExpectedArm64ASM": [
|
|
"sqsub v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"psubsw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xe9",
|
|
"ExpectedArm64ASM": [
|
|
"sqsub v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pminsw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xea",
|
|
"ExpectedArm64ASM": [
|
|
"smin v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"por xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xeb",
|
|
"ExpectedArm64ASM": [
|
|
"orr v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"paddsb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xec",
|
|
"ExpectedArm64ASM": [
|
|
"sqadd v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"paddsw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xed",
|
|
"ExpectedArm64ASM": [
|
|
"sqadd v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pmaxsw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xee",
|
|
"ExpectedArm64ASM": [
|
|
"smax v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"pxor xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xef",
|
|
"ExpectedArm64ASM": [
|
|
"eor v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"pxor xmm0, xmm0": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xef",
|
|
"ExpectedArm64ASM": [
|
|
"movi v16.2d, #0x0"
|
|
]
|
|
},
|
|
"psllw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x66 0x0f 0xf1",
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d17, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.8h, v0.h[0]",
|
|
"ushl v16.8h, v16.8h, v0.8h"
|
|
]
|
|
},
|
|
"pslld xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x66 0x0f 0xf2",
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d17, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.4s, v0.s[0]",
|
|
"ushl v16.4s, v16.4s, v0.4s"
|
|
]
|
|
},
|
|
"psllq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x66 0x0f 0xf3",
|
|
"ExpectedArm64ASM": [
|
|
"uqshl d0, d17, #57",
|
|
"ushr d0, d0, #57",
|
|
"dup v0.2d, v0.d[0]",
|
|
"ushl v16.2d, v16.2d, v0.2d"
|
|
]
|
|
},
|
|
"pmuludq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x66 0x0f 0xf4",
|
|
"ExpectedArm64ASM": [
|
|
"uzp1 v2.4s, v16.4s, v16.4s",
|
|
"uzp1 v3.4s, v17.4s, v17.4s",
|
|
"umull v16.2d, v2.2s, v3.2s"
|
|
]
|
|
},
|
|
"pmaddwd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x66 0x0f 0xf5",
|
|
"ExpectedArm64ASM": [
|
|
"smull v2.4s, v16.4h, v17.4h",
|
|
"smull2 v3.4s, v16.8h, v17.8h",
|
|
"addp v16.4s, v2.4s, v3.4s"
|
|
]
|
|
},
|
|
"psadbw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x66 0x0f 0xf6",
|
|
"ExpectedArm64ASM": [
|
|
"uabdl v2.8h, v16.8b, v17.8b",
|
|
"uabdl2 v3.8h, v16.16b, v17.16b",
|
|
"addv h2, v2.8h",
|
|
"addv h3, v3.8h",
|
|
"zip1 v16.2d, v2.2d, v3.2d"
|
|
]
|
|
},
|
|
"maskmovdqu xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x66 0x0f 0xf7",
|
|
"ExpectedArm64ASM": [
|
|
"cmlt v2.16b, v17.16b, #0",
|
|
"ldr q3, [x11]",
|
|
"bsl v2.16b, v16.16b, v3.16b",
|
|
"str q2, [x11]"
|
|
]
|
|
},
|
|
"psubb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xf8",
|
|
"ExpectedArm64ASM": [
|
|
"sub v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"psubw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xf9",
|
|
"ExpectedArm64ASM": [
|
|
"sub v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"psubd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xfa",
|
|
"ExpectedArm64ASM": [
|
|
"sub v16.4s, v16.4s, v17.4s"
|
|
]
|
|
},
|
|
"psubq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xfb",
|
|
"ExpectedArm64ASM": [
|
|
"sub v16.2d, v16.2d, v17.2d"
|
|
]
|
|
},
|
|
"paddb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xfc",
|
|
"ExpectedArm64ASM": [
|
|
"add v16.16b, v16.16b, v17.16b"
|
|
]
|
|
},
|
|
"paddw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xfd",
|
|
"ExpectedArm64ASM": [
|
|
"add v16.8h, v16.8h, v17.8h"
|
|
]
|
|
},
|
|
"paddd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x66 0x0f 0xfe",
|
|
"ExpectedArm64ASM": [
|
|
"add v16.4s, v16.4s, v17.4s"
|
|
]
|
|
}
|
|
}
|
|
}
|