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Ryan Houdek
f2f90eeb82
We can support a few combinations of guest and host vector sizes Host: 128-bit or 256-bit Guest: 128-bit or 256-bit The typical case is Host = 128-bit and Guest = 256-bit now that AVX is implemented. On 32-bit this changes to Host=128-bit and Guest=128-bit because we disable AVX. In the vixl simulator 32-bit turns in to Host=256-bit and Guest=128-bit. And then in the vixl sim 64-bit turns in to Host=256-bit and Guest=256-bit. We cover all four combinations of guest and host vector register sizes! Fixes a few assumptions that SVE256 = AVX256 basically.