mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-08 01:00:15 +02:00
Ryan Houdek
e84848b16b
This moves the CPU feature querying to the frontend. The primary purpose here is for the wow64 frontend to not require linux-isms for querying these features. This is required since non-Linux environments don't have the "CPUID" feature for reading EL1 MSRs in EL0. Wiring up the remaining wow64 registry querying is left for a future exercise. This also technically removes an xbyak requirement from FEXCore for when building the x86 Test harness runner, but that doesn't really matter for regular use cases.
309 lines
13 KiB
C++
309 lines
13 KiB
C++
// SPDX-License-Identifier: MIT
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#include <FEXCore/Config/Config.h>
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#include <FEXCore/Core/HostFeatures.h>
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#include "aarch64/cpu-aarch64.h"
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#ifdef _M_X86_64
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#define XBYAK64
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#define XBYAK_NO_EXCEPTION
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#include <FEXCore/fextl/list.h>
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#include <FEXCore/fextl/unordered_map.h>
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#include <FEXCore/fextl/unordered_set.h>
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#include <xbyak/xbyak.h>
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#include <xbyak/xbyak_util.h>
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#endif
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namespace FEX {
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// Data Zero Prohibited flag
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// 0b0 = ZVA/GVA/GZVA permitted
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// 0b1 = ZVA/GVA/GZVA prohibited
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[[maybe_unused]] constexpr uint32_t DCZID_DZP_MASK = 0b1'0000;
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// Log2 of the blocksize in 32-bit words
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[[maybe_unused]] constexpr uint32_t DCZID_BS_MASK = 0b0'1111;
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#ifdef _M_ARM_64
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[[maybe_unused]]
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static uint32_t GetDCZID() {
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uint64_t Result {};
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__asm("mrs %[Res], DCZID_EL0" : [Res] "=r"(Result));
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return Result;
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}
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static uint32_t GetFPCR() {
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uint64_t Result {};
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__asm("mrs %[Res], FPCR" : [Res] "=r"(Result));
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return Result;
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}
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static void SetFPCR(uint64_t Value) {
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__asm("msr FPCR, %[Value]" ::[Value] "r"(Value));
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}
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static uint32_t GetMIDR() {
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uint64_t Result {};
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__asm("mrs %[Res], MIDR_EL1" : [Res] "=r"(Result));
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return Result;
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}
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__attribute__((naked)) static uint64_t ReadSVEVectorLengthInBits() {
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///< Can't use rdvl instruction directly because compilers will complain that sve/sme is required.
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__asm(R"(
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.word 0x04bf5100 // rdvl x0, #8
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ret;
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)");
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}
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#else
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[[maybe_unused]]
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static uint32_t GetDCZID() {
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// Return unsupported
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return DCZID_DZP_MASK;
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}
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static int ReadSVEVectorLengthInBits() {
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// Return unsupported
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return 0;
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}
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#endif
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static void OverrideFeatures(FEXCore::HostFeatures* Features, uint64_t ForceSVEWidth) {
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// Override features if the user has specifically called for it.
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FEX_CONFIG_OPT(HostFeatures, HOSTFEATURES);
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if (!HostFeatures()) {
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// Early exit if no features are overriden.
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return;
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}
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#define ENABLE_DISABLE_OPTION(FeatureName, name, enum_name) \
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do { \
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const bool Disable##name = (HostFeatures() & FEXCore::Config::HostFeatures::DISABLE##enum_name) != 0; \
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const bool Enable##name = (HostFeatures() & FEXCore::Config::HostFeatures::ENABLE##enum_name) != 0; \
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LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive"); \
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const bool AlreadyEnabled = Features->FeatureName; \
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const bool Result = (AlreadyEnabled | Enable##name) & !Disable##name; \
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Features->FeatureName = Result; \
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} while (0)
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#define GET_SINGLE_OPTION(name, enum_name) \
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const bool Disable##name = (HostFeatures() & FEXCore::Config::HostFeatures::DISABLE##enum_name) != 0; \
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const bool Enable##name = (HostFeatures() & FEXCore::Config::HostFeatures::ENABLE##enum_name) != 0; \
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LogMan::Throw::AFmt(!(Disable##name && Enable##name), "Disabling and Enabling CPU feature (" #name ") is mutually exclusive");
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ENABLE_DISABLE_OPTION(SupportsAVX, AVX, AVX);
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ENABLE_DISABLE_OPTION(SupportsSVE128, SVE, SVE);
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ENABLE_DISABLE_OPTION(SupportsAFP, AFP, AFP);
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ENABLE_DISABLE_OPTION(SupportsRCPC, LRCPC, LRCPC);
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ENABLE_DISABLE_OPTION(SupportsTSOImm9, LRCPC2, LRCPC2);
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ENABLE_DISABLE_OPTION(SupportsCSSC, CSSC, CSSC);
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ENABLE_DISABLE_OPTION(SupportsPMULL_128Bit, PMULL128, PMULL128);
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ENABLE_DISABLE_OPTION(SupportsRAND, RNG, RNG);
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ENABLE_DISABLE_OPTION(SupportsCLZERO, CLZERO, CLZERO);
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ENABLE_DISABLE_OPTION(SupportsAtomics, Atomics, ATOMICS);
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ENABLE_DISABLE_OPTION(SupportsFCMA, FCMA, FCMA);
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ENABLE_DISABLE_OPTION(SupportsFlagM, FlagM, FLAGM);
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ENABLE_DISABLE_OPTION(SupportsFlagM2, FlagM2, FLAGM2);
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ENABLE_DISABLE_OPTION(SupportsRPRES, RPRES, RPRES);
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ENABLE_DISABLE_OPTION(SupportsSVEBitPerm, SVEBITPERM, SVEBITPERM);
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ENABLE_DISABLE_OPTION(SupportsPreserveAllABI, PRESERVEALLABI, PRESERVEALLABI);
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GET_SINGLE_OPTION(Crypto, CRYPTO);
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#undef ENABLE_DISABLE_OPTION
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#undef GET_SINGLE_OPTION
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if (EnableCrypto) {
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Features->SupportsAES = true;
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Features->SupportsCRC = true;
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Features->SupportsSHA = true;
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Features->SupportsPMULL_128Bit = true;
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Features->SupportsAES256 = true;
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} else if (DisableCrypto) {
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Features->SupportsAES = false;
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Features->SupportsCRC = false;
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Features->SupportsSHA = false;
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Features->SupportsPMULL_128Bit = false;
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Features->SupportsAES256 = false;
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}
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///< Only force enable SVE256 if SVE is already enabled and ForceSVEWidth is set to >= 256.
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Features->SupportsSVE256 = ForceSVEWidth && ForceSVEWidth >= 256;
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}
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FEXCore::HostFeatures FetchHostFeatures() {
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FEXCore::HostFeatures HostFeatures;
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#ifdef VIXL_SIMULATOR
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auto Features = vixl::CPUFeatures::All();
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// Vixl simulator doesn't support AFP.
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Features.Remove(vixl::CPUFeatures::Feature::kAFP);
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// Vixl simulator doesn't support RPRES.
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Features.Remove(vixl::CPUFeatures::Feature::kRPRES);
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#elif !defined(_WIN32)
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auto Features = vixl::CPUFeatures::InferFromOS();
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#else
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// Need to use ID registers in WINE.
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auto Features = vixl::CPUFeatures::InferFromIDRegisters();
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#endif
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FEX_CONFIG_OPT(ForceSVEWidth, FORCESVEWIDTH);
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FEX_CONFIG_OPT(Is64BitMode, IS64BIT_MODE);
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HostFeatures.SupportsAES = Features.Has(vixl::CPUFeatures::Feature::kAES);
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HostFeatures.SupportsCRC = Features.Has(vixl::CPUFeatures::Feature::kCRC32);
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HostFeatures.SupportsSHA = Features.Has(vixl::CPUFeatures::Feature::kSHA1) && Features.Has(vixl::CPUFeatures::Feature::kSHA2);
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HostFeatures.SupportsAtomics = Features.Has(vixl::CPUFeatures::Feature::kAtomics);
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HostFeatures.SupportsRAND = Features.Has(vixl::CPUFeatures::Feature::kRNG);
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// Only supported when FEAT_AFP is supported
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HostFeatures.SupportsAFP = Features.Has(vixl::CPUFeatures::Feature::kAFP);
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HostFeatures.SupportsRCPC = Features.Has(vixl::CPUFeatures::Feature::kRCpc);
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HostFeatures.SupportsTSOImm9 = Features.Has(vixl::CPUFeatures::Feature::kRCpcImm);
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HostFeatures.SupportsPMULL_128Bit = Features.Has(vixl::CPUFeatures::Feature::kPmull1Q);
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HostFeatures.SupportsCSSC = Features.Has(vixl::CPUFeatures::Feature::kCSSC);
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HostFeatures.SupportsFCMA = Features.Has(vixl::CPUFeatures::Feature::kFcma);
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HostFeatures.SupportsFlagM = Features.Has(vixl::CPUFeatures::Feature::kFlagM);
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HostFeatures.SupportsFlagM2 = Features.Has(vixl::CPUFeatures::Feature::kAXFlag);
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HostFeatures.SupportsRPRES = Features.Has(vixl::CPUFeatures::Feature::kRPRES);
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HostFeatures.SupportsSVEBitPerm = Features.Has(vixl::CPUFeatures::Feature::kSVEBitPerm);
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HostFeatures.Supports3DNow = true;
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HostFeatures.SupportsSSE4A = true;
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#ifdef VIXL_SIMULATOR
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// Hardcode enable SVE with 256-bit wide registers.
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HostFeatures.SupportsSVE128 = ForceSVEWidth() ? ForceSVEWidth() >= 128 : true;
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HostFeatures.SupportsSVE256 = ForceSVEWidth() ? ForceSVEWidth() >= 256 : true;
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#else
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HostFeatures.SupportsSVE128 = Features.Has(vixl::CPUFeatures::Feature::kSVE2);
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HostFeatures.SupportsSVE256 = Features.Has(vixl::CPUFeatures::Feature::kSVE2) && ReadSVEVectorLengthInBits() >= 256;
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#endif
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HostFeatures.SupportsAVX = true;
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HostFeatures.SupportsAES256 = HostFeatures.SupportsAVX && HostFeatures.SupportsAES;
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HostFeatures.SupportsBMI1 = true;
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HostFeatures.SupportsBMI2 = true;
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HostFeatures.SupportsCLWB = true;
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if (!HostFeatures.SupportsAtomics) {
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WARN_ONCE_FMT("Host CPU doesn't support atomics. Expect bad performance");
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}
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#ifdef _M_ARM_64
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// We need to get the CPU's cache line size
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// We expect sane targets that have correct cacheline sizes across clusters
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uint64_t CTR;
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__asm volatile("mrs %[ctr], ctr_el0" : [ctr] "=r"(CTR));
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HostFeatures.DCacheLineSize = 4 << ((CTR >> 16) & 0xF);
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HostFeatures.ICacheLineSize = 4 << (CTR & 0xF);
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// Test if this CPU supports float exception trapping by attempting to enable
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// On unsupported these bits are architecturally defined as RAZ/WI
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constexpr uint32_t ExceptionEnableTraps = (1U << 8) | // Invalid Operation float exception trap enable
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(1U << 9) | // Divide by zero float exception trap enable
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(1U << 10) | // Overflow float exception trap enable
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(1U << 11) | // Underflow float exception trap enable
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(1U << 12) | // Inexact float exception trap enable
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(1U << 15); // Input Denormal float exception trap enable
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uint32_t OriginalFPCR = GetFPCR();
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uint32_t FPCR = OriginalFPCR | ExceptionEnableTraps;
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SetFPCR(FPCR);
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FPCR = GetFPCR();
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HostFeatures.SupportsFloatExceptions = (FPCR & ExceptionEnableTraps) == ExceptionEnableTraps;
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// Set FPCR back to original just in case anything changed
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SetFPCR(OriginalFPCR);
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if (HostFeatures.SupportsRAND) {
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const auto MIDR = GetMIDR();
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constexpr uint32_t Implementer_QCOM = 0x51;
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constexpr uint32_t PartNum_Oryon1 = 0x001;
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const uint32_t MIDR_Implementer = (MIDR >> 24) & 0xFF;
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const uint32_t MIDR_PartNum = (MIDR >> 4) & 0xFFF;
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if (MIDR_Implementer == Implementer_QCOM && MIDR_PartNum == PartNum_Oryon1) {
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// Work around an errata in Qualcomm's Oryon.
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// While this CPU implements the RAND extension:
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// - The RNDR register works.
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// - The RNDRRS register will never read a random number. (Always return failure)
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// This is contrary to x86 RNG behaviour where it allows spurious failure with RDSEED, but guarantees eventual success.
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// This manifested itself on Linux when an x86 processor failed to guarantee forward progress and boot of services would infinite
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// loop. Just disable this extension if this CPU is detected.
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HostFeatures.SupportsRAND = false;
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}
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}
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#endif
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#ifdef VIXL_SIMULATOR
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// simulator doesn't support dc(ZVA)
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HostFeatures.SupportsCLZERO = false;
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// Simulator doesn't support SHA
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HostFeatures.SupportsSHA = false;
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#else
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// Check if we can support cacheline clears
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uint32_t DCZID = GetDCZID();
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if ((DCZID & DCZID_DZP_MASK) == 0) {
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uint32_t DCZID_Log2 = DCZID & DCZID_BS_MASK;
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uint32_t DCZID_Bytes = (1 << DCZID_Log2) * sizeof(uint32_t);
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// If the DC ZVA size matches the emulated cache line size
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// This means we can use the instruction
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constexpr static uint64_t CACHELINE_SIZE = 64;
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HostFeatures.SupportsCLZERO = DCZID_Bytes == CACHELINE_SIZE;
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}
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#endif
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#if defined(_M_X86_64)
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// Hardcoded cacheline size.
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HostFeatures.DCacheLineSize = 64U;
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HostFeatures.ICacheLineSize = 64U;
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#if !defined(VIXL_SIMULATOR)
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Xbyak::util::Cpu X86Features {};
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HostFeatures.SupportsAES = X86Features.has(Xbyak::util::Cpu::tAESNI);
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HostFeatures.SupportsCRC = X86Features.has(Xbyak::util::Cpu::tSSE42);
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HostFeatures.SupportsRAND = X86Features.has(Xbyak::util::Cpu::tRDRAND) && X86Features.has(Xbyak::util::Cpu::tRDSEED);
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HostFeatures.SupportsRCPC = true;
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HostFeatures.SupportsTSOImm9 = true;
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HostFeatures.Supports3DNow = X86Features.has(Xbyak::util::Cpu::t3DN) && X86Features.has(Xbyak::util::Cpu::tE3DN);
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HostFeatures.SupportsSSE4A = X86Features.has(Xbyak::util::Cpu::tSSE4a);
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HostFeatures.SupportsAVX = true;
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HostFeatures.SupportsSHA = X86Features.has(Xbyak::util::Cpu::tSHA);
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HostFeatures.SupportsBMI1 = X86Features.has(Xbyak::util::Cpu::tBMI1);
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HostFeatures.SupportsBMI2 = X86Features.has(Xbyak::util::Cpu::tBMI2);
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HostFeatures.SupportsCLWB = X86Features.has(Xbyak::util::Cpu::tCLWB);
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HostFeatures.SupportsPMULL_128Bit = X86Features.has(Xbyak::util::Cpu::tPCLMULQDQ);
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HostFeatures.SupportsAES256 = HostFeatures.SupportsAES && X86Features.has(Xbyak::util::Cpu::tVAES);
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// xbyak doesn't know how to check for CLZero
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// First ensure we support a new enough extended CPUID function range
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uint32_t data[4];
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Xbyak::util::Cpu::getCpuid(0x8000'0000, data);
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if (data[0] >= 0x8000'0008U) {
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// CLZero defined in 8000_00008_EBX[bit 0]
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Xbyak::util::Cpu::getCpuid(0x8000'0008, data);
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HostFeatures.SupportsCLZERO = data[1] & 1;
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}
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HostFeatures.SupportsAFP = true;
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HostFeatures.SupportsFloatExceptions = true;
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#endif
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#endif
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HostFeatures.SupportsPreserveAllABI = FEX_HAS_PRESERVE_ALL_ATTR;
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if (!Is64BitMode()) {
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///< Always disable AVX and AVX2 in 32-bit mode.
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// When AVX256 is enabled, signal frames start using significantly more stack space.
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// - 16bytes * 16 registers = 256 bytes for XMM registers.
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// - 32bytes * 16 registers = 512 bytes for YMM registers.
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// There are known game failures on real x86 hardware where a 32-bit game is running up against the wall on stack space on non-AVX
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// hardware and then explodes when run on AVX hardware. This is to guard against that.
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HostFeatures.SupportsAVX = false;
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}
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OverrideFeatures(&HostFeatures, ForceSVEWidth());
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return HostFeatures;
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}
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} // namespace FEX
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