Alyssa Rosenzweig e5cb583cc0 OpcodeDispatcher: optimize 8-bit rol ...

rotate right by less than 8:

  ror(________________7654321076543120, ...)

rotate left by less than 8:

  rol(76543210________________76543210, ...)

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2024-08-19 10:40:53 -04:00

..

Config

HostFeatures: Check for SVE bit permute extension

2024-07-10 21:45:07 -07:00

Context

FEXCore: Pass HostFeatures in to CreateNewContext directly

2024-08-08 21:02:41 -07:00

Core

OpcodeDispatcher: optimize 8-bit rol

2024-08-19 10:40:53 -04:00

GDBJIT

Whole-tree reformat

2024-04-12 16:26:02 +02:00

HLE/Thunks

VDSO: Stop using a vector for a static

2024-07-11 23:53:57 -07:00

IR

OpcodeDispatcher: optimize rotate flags

2024-08-19 10:40:53 -04:00