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e455996dbd2e4f59741719ba7436be1a40e60432
FEX-Emu--FEX/FEXCore/Source/Interface
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Alyssa Rosenzweig e455996dbd OpcodeDispatcher: Remove silly shift branching 
The flag generation code does this internally and more efficiently.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-10-23 10:16:38 -04:00
..
Config
FEXCore: Implements support for RPRES
2023-10-07 23:13:47 -07:00
Context
InstCountCI: Support multiple instructions in the tests
2023-10-09 21:49:53 -07:00
Core
OpcodeDispatcher: Remove silly shift branching
2023-10-23 10:16:38 -04:00
GDBJIT
FEXCore/Interface/GDBJIT: Adds SPDX identifier
2023-09-19 17:33:15 -07:00
HLE/Thunks
FEXCore/Interface/Thunks: Adds SPDX identifier
2023-09-19 17:33:14 -07:00
IR
IR: Adds scalar vector insert operations
2023-10-10 03:17:19 -07:00