Alyssa Rosenzweig 64bac687b5 IR: Add TEST opcode ...

Maps to arm64 tst, except properly SSA. This will need some RA support
to avoid redundant mrs/msr sequences.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2023-08-02 12:38:00 -04:00

..

Passes

IR: Add TEST opcode

2023-08-02 12:38:00 -04:00

AOTIR.cpp

AOTIR: std::move function instances where applicable

2023-07-27 18:35:30 -04:00

AOTIR.h

AOTIR: std::move function instances where applicable

2023-07-27 18:35:30 -04:00

IR.json

IR: Add TEST opcode

2023-08-02 12:38:00 -04:00

IRDumper.cpp

IR: Print SSA values as %123 instead of %ssa123

2023-07-13 11:52:36 -04:00

IREmitter.cpp

Convert the rest of vector to fextl

2023-03-16 03:03:08 -07:00

IRParser.cpp

IR: Print SSA values as %123 instead of %ssa123

2023-07-13 11:52:36 -04:00

Passes.h

Convert a ton of things over to fextl

2023-03-30 16:28:33 -07:00

PassManager.cpp

FEXCore: Removes C wrapper interface

2023-02-19 11:59:11 -08:00

PassManager.h

Convert a ton of things over to fextl

2023-03-30 16:28:33 -07:00