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FEX-Emu--FEX/unittests/InstructionCountCI/x87.json
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Ryan Houdek d06e98ed84 InstcountCI: Update
2026-09-15 16:40:55 -07:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"CSSC",
"AFP",
"FLAGM",
"FLAGM2"
],
"BinaryCacheVersion": 24
},
"Instructions": {
"fadd dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xd8 !11b /0"
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str x30, [sp, #-16]!",
"fmov s0, s2",
"ldr x0, [x28, #1640]",
"ldr x3, [x28, #1648]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xd8 !11b /1"
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str x30, [sp, #-16]!",
"fmov s0, s2",
"ldr x0, [x28, #1640]",
"ldr x3, [x28, #1648]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fcom dword [rax]": {
"ExpectedInstructionCount": 31,
"Comment": [
"0xd8 !11b /2"
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str x30, [sp, #-16]!",
"fmov s0, s2",
"ldr x0, [x28, #1640]",
"ldr x3, [x28, #1648]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fcomp dword [rax]": {
"ExpectedInstructionCount": 39,
"Comment": [
"0xd8 !11b /3"
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str x30, [sp, #-16]!",
"fmov s0, s2",
"ldr x0, [x28, #1640]",
"ldr x3, [x28, #1648]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsub dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xd8 !11b /4"
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str x30, [sp, #-16]!",
"fmov s0, s2",
"ldr x0, [x28, #1640]",
"ldr x3, [x28, #1648]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsubr dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xd8 !11b /5"
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str x30, [sp, #-16]!",
"fmov s0, s2",
"ldr x0, [x28, #1640]",
"ldr x3, [x28, #1648]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xd8 !11b /6"
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str x30, [sp, #-16]!",
"fmov s0, s2",
"ldr x0, [x28, #1640]",
"ldr x3, [x28, #1648]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdivr dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xd8 !11b /7"
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str x30, [sp, #-16]!",
"fmov s0, s2",
"ldr x0, [x28, #1640]",
"ldr x3, [x28, #1648]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st0, st0": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd8 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st0, st1": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st0, st2": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st0, st3": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st0, st4": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st0, st5": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st0, st6": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st0, st7": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st0, st0": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd8 11b 0xc8 /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st0, st1": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xc9 /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st0, st2": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xca /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st0, st3": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xcb /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st0, st4": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xcc /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st0, st5": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xcd /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st0, st6": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xce /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st0, st7": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xcf /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fcom st0, st0": {
"ExpectedInstructionCount": 23,
"Comment": [
"0xd8 11b 0xd0 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fcom st0, st1": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xd8 11b 0xd1 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fcom st0, st2": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xd8 11b 0xd2 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fcom st0, st3": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xd8 11b 0xd3 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fcom st0, st4": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xd8 11b 0xd4 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fcom st0, st5": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xd8 11b 0xd5 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fcom st0, st6": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xd8 11b 0xd6 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fcom st0, st7": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xd8 11b 0xd7 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fcomp st0, st0": {
"ExpectedInstructionCount": 31,
"Comment": [
"0xd8 11b 0xd8 /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomp st0, st1": {
"ExpectedInstructionCount": 33,
"Comment": [
"0xd8 11b 0xd9 /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x22, x0",
"ubfx x23, x22, #1, #1",
"ubfx x24, x22, #0, #1",
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"strb w23, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w22, [x28, #1050]",
"strb w24, [x28, #1054]",
"ldrb w23, [x28, #1040]",
"orr w22, w23, w22",
"strb w22, [x28, #1040]",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomp st0, st2": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xd8 11b 0xda /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomp st0, st3": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xd8 11b 0xdb /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomp st0, st4": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xd8 11b 0xdc /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomp st0, st5": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xd8 11b 0xdd /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomp st0, st6": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xd8 11b 0xde /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomp st0, st7": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xd8 11b 0xdf /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsub st0, st0": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd8 11b 0xe0 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st0, st1": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xe1 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st0, st2": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xe2 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st0, st3": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xe3 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st0, st4": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xe4 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st0, st5": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xe5 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st0, st6": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xe6 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st0, st7": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xe7 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsubr st0, st0": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd8 11b 0xe8 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsubr st0, st1": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xe9 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st0, st2": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xea /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st0, st3": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xeb /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st0, st4": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xec /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st0, st5": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xed /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st0, st6": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xee /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st0, st7": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xef /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdiv st0, st0": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd8 11b 0xf0 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st0, st1": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xf1 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st0, st2": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xf2 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st0, st3": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xf3 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st0, st4": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xf4 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st0, st5": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xf5 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st0, st6": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xf6 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st0, st7": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xf7 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdivr st0, st0": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd8 11b 0xf8 /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdivr st0, st1": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xf9 /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st0, st2": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xfa /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st0, st3": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xfb /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st0, st4": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xfc /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st0, st5": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xfd /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st0, st6": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xfe /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st0, st7": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd8 11b 0xff /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fld dword [rax]": {
"ExpectedInstructionCount": 19,
"Comment": [
"0xd9 !11b /0"
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str x30, [sp, #-16]!",
"fmov s0, s2",
"ldr x0, [x28, #1640]",
"ldr x3, [x28, #1648]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst dword [rax]": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xd9 !11b /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1672]",
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x4]"
]
},
"fstp dword [rax]": {
"ExpectedInstructionCount": 19,
"Comment": [
"0xd9 !11b /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1672]",
"ldr x3, [x28, #1680]",
"blr x0",
"ldr x30, [sp], #16",
"fmov s2, s0",
"str s2, [x4]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fldenv [rax]": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xd9 !11b /4"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1200]",
"add x20, x4, #0x4 (4)",
"ldr w20, [x20]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1051]",
"ubfx w21, w20, #8, #1",
"ubfx w22, w20, #9, #1",
"ubfx w23, w20, #10, #1",
"ubfx w24, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w21, [x28, #1048]",
"strb w22, [x28, #1049]",
"strb w23, [x28, #1050]",
"strb w24, [x28, #1054]",
"strb w20, [x28, #1040]",
"add x20, x4, #0x8 (8)",
"ldr w20, [x20]",
"and w20, w20, w20, lsr #1",
"mov w21, #0x55555555",
"bic w20, w21, w20",
"orr w20, w20, w20, lsr #1",
"and w20, w20, #0x33333333",
"orr w20, w20, w20, lsr #2",
"and w20, w20, #0xf0f0f0f",
"orr w20, w20, w20, lsr #4",
"strb w20, [x28, #1202]"
]
},
"fldcw [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"0xd9 !11b /5"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1200]"
]
},
"fnstenv [rax]": {
"ExpectedInstructionCount": 29,
"Comment": [
"0xd9 !11b /6"
],
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1200]",
"str w20, [x4]",
"ldrb w20, [x28, #1051]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1048]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1049]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1050]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1054]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #1040]",
"orr x20, x20, x21",
"str w20, [x4, #4]",
"ldrb w20, [x28, #1202]",
"orr w20, w20, w20, lsl #4",
"and w20, w20, #0xf0f0f0f",
"orr w20, w20, w20, lsl #2",
"and w20, w20, #0x33333333",
"orr w20, w20, w20, lsl #1",
"and w20, w20, #0x55555555",
"orr w20, w20, w20, lsl #1",
"eor w20, w20, #0xffff",
"str w20, [x4, #8]",
"str wzr, [x4, #12]",
"str wzr, [x4, #16]",
"str wzr, [x4, #20]",
"str wzr, [x4, #24]"
]
},
"fnstcw [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"0xd9 !11b /7"
],
"ExpectedArm64ASM": [
"ldrh w20, [x28, #1200]",
"strh w20, [x4]"
]
},
"fld st0": {
"ExpectedInstructionCount": 13,
"Comment": [
"0xd9 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fld st1": {
"ExpectedInstructionCount": 15,
"Comment": [
"0xd9 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fld st2": {
"ExpectedInstructionCount": 15,
"Comment": [
"0xd9 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fld st3": {
"ExpectedInstructionCount": 15,
"Comment": [
"0xd9 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fld st4": {
"ExpectedInstructionCount": 15,
"Comment": [
"0xd9 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fld st5": {
"ExpectedInstructionCount": 15,
"Comment": [
"0xd9 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fld st6": {
"ExpectedInstructionCount": 15,
"Comment": [
"0xd9 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fld st7": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd9 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"strb w20, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st0": {
"ExpectedInstructionCount": 1,
"Comment": [
"0xd9 11b 0xc8 /1"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1049]"
]
},
"fxch st0, st1": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xc9 /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x303",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st2": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xca /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w22, w20, #0x2 (2)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x505",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st3": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcb /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w22, w20, #0x3 (3)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x909",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st4": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcc /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w22, w20, #0x4 (4)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x1111",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st5": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcd /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w22, w20, #0x5 (5)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x2121",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st6": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xce /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w22, w20, #0x6 (6)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x4141",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxch st0, st7": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xcf /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w22, w20, #0x7 (7)",
"and w22, w22, #0x7",
"add x22, x28, x22, lsl #4",
"ldr q3, [x22, #1056]",
"strb wzr, [x28, #1049]",
"str q3, [x21, #1056]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x8181",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fnop": {
"ExpectedInstructionCount": 0,
"Comment": [
"0xd9 11b 0xd0 /2"
],
"ExpectedArm64ASM": []
},
"fchs": {
"ExpectedInstructionCount": 6,
"Comment": [
"0xd9 11b 0xe0 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"ldr q3, [x28, #3696]",
"eor v2.16b, v2.16b, v3.16b",
"str q2, [x20, #1056]"
]
},
"fabs": {
"ExpectedInstructionCount": 6,
"Comment": [
"0xd9 11b 0xe1 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"ldr q3, [x28, #3696]",
"bic v2.16b, v2.16b, v3.16b",
"str q2, [x20, #1056]"
]
},
"ftst": {
"ExpectedInstructionCount": 25,
"Comment": [
"0xd9 11b 0xe4 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"mov w20, #0x0",
"fmov d3, x20",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fxam": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd9 11b 0xe5 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"mov x21, v2.d[1]",
"ubfx x21, x21, #15, #1",
"strb w21, [x28, #1049]",
"ldrb w21, [x28, #1202]",
"lsr w20, w21, w20",
"and w20, w20, #0x1",
"mrs x21, nzcv",
"cmp w20, #0x1 (1)",
"cset x22, ne",
"strb w22, [x28, #1048]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"msr nzcv, x21"
]
},
"fld1": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd9 11b 0xe8 /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3472]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fldl2t": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd9 11b 0xe9 /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3488]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fldl2e": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd9 11b 0xea /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3504]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fldpi": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd9 11b 0xeb /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3520]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fldlg2": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd9 11b 0xec /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3536]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fldln2": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd9 11b 0xed /5"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3552]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fldz": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd9 11b 0xee /5"
],
"ExpectedArm64ASM": [
"movi v2.2d, #0x0",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"f2xm1": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xd9 11b 0xf0 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1864]",
"ldr x3, [x28, #1872]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fyl2x": {
"ExpectedInstructionCount": 22,
"Comment": [
"0xd9 11b 0xf1 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q2, [x22, #1056]",
"add x23, x28, x20, lsl #4",
"ldr q3, [x23, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2088]",
"ldr x3, [x28, #2096]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb w21, [x28, #1051]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fptan": {
"ExpectedInstructionCount": 23,
"Comment": [
"0xd9 11b 0xf2 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1880]",
"ldr x3, [x28, #1888]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldr q3, [x28, #3472]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb wzr, [x28, #1050]",
"strb w20, [x28, #1051]",
"add x22, x28, x20, lsl #4",
"str q3, [x22, #1056]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fpatan": {
"ExpectedInstructionCount": 22,
"Comment": [
"0xd9 11b 0xf3 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2120]",
"ldr x3, [x28, #2128]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb w21, [x28, #1051]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fxtract": {
"ExpectedInstructionCount": 30,
"Comment": [
"0xd9 11b 0xf4 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1960]",
"ldr x3, [x28, #1968]",
"blr x0",
"ldr x30, [sp], #16",
"mov v3.16b, v0.16b",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1976]",
"ldr x3, [x28, #1984]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x22, x28, x20, lsl #4",
"str q2, [x22, #1056]",
"str q3, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0x303",
"lsr w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fprem1": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xf5 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2136]",
"ldr x3, [x28, #2144]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb wzr, [x28, #1050]",
"str q2, [x20, #1056]"
]
},
"fdecstp": {
"ExpectedInstructionCount": 5,
"Comment": [
"0xd9 11b 0xf6 /6"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1049]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]"
]
},
"fincstp": {
"ExpectedInstructionCount": 5,
"Comment": [
"0xd9 11b 0xf7 /6"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1049]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]"
]
},
"fprem": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xd9 11b 0xf8 /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2152]",
"ldr x3, [x28, #2160]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb wzr, [x28, #1050]",
"str q2, [x20, #1056]"
]
},
"fyl2xp1": {
"ExpectedInstructionCount": 22,
"Comment": [
"0xd9 11b 0xf9 /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q2, [x22, #1056]",
"add x23, x28, x20, lsl #4",
"ldr q3, [x23, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2104]",
"ldr x3, [x28, #2112]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb w21, [x28, #1051]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsqrt": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xd9 11b 0xfa /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1896]",
"ldr x3, [x28, #1904]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsincos": {
"ExpectedInstructionCount": 23,
"Comment": [
"0xd9 11b 0xfb /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1944]",
"ldr x3, [x28, #1952]",
"blr x0",
"ldr x30, [sp], #16",
"mov v3.16b, v0.16b",
"mov v4.16b, v1.16b",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb wzr, [x28, #1050]",
"strb w20, [x28, #1051]",
"add x22, x28, x20, lsl #4",
"str q4, [x22, #1056]",
"str q3, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"frndint": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xd9 11b 0xfc /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1848]",
"ldr x3, [x28, #1856]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fscale": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xd9 11b 0xfd /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2168]",
"ldr x3, [x28, #2176]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsin": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd9 11b 0xfe /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1912]",
"ldr x3, [x28, #1920]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb wzr, [x28, #1050]",
"str q2, [x20, #1056]"
]
},
"fcos": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xd9 11b 0xff /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1928]",
"ldr x3, [x28, #1936]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb wzr, [x28, #1050]",
"str q2, [x20, #1056]"
]
},
"fiadd dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xda !11b /0"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"str x30, [sp, #-16]!",
"mov w1, w20",
"ldr x0, [x28, #1832]",
"ldr x3, [x28, #1840]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fimul dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xda !11b /1"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"str x30, [sp, #-16]!",
"mov w1, w20",
"ldr x0, [x28, #1832]",
"ldr x3, [x28, #1840]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"ficom dword [rax]": {
"ExpectedInstructionCount": 31,
"Comment": [
"0xda !11b /2"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"str x30, [sp, #-16]!",
"mov w1, w20",
"ldr x0, [x28, #1832]",
"ldr x3, [x28, #1840]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"ficomp dword [rax]": {
"ExpectedInstructionCount": 39,
"Comment": [
"0xda !11b /3"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"str x30, [sp, #-16]!",
"mov w1, w20",
"ldr x0, [x28, #1832]",
"ldr x3, [x28, #1840]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fisub dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xda !11b /4"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"str x30, [sp, #-16]!",
"mov w1, w20",
"ldr x0, [x28, #1832]",
"ldr x3, [x28, #1840]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fisubr dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xda !11b /5"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"str x30, [sp, #-16]!",
"mov w1, w20",
"ldr x0, [x28, #1832]",
"ldr x3, [x28, #1840]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fidiv dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xda !11b /6"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"str x30, [sp, #-16]!",
"mov w1, w20",
"ldr x0, [x28, #1832]",
"ldr x3, [x28, #1840]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fidivr dword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xda !11b /7"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"str x30, [sp, #-16]!",
"mov w1, w20",
"ldr x0, [x28, #1832]",
"ldr x3, [x28, #1840]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fcmovb st0, st0": {
"ExpectedInstructionCount": 7,
"Comment": [
"0xda 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"bsl v2.16b, v3.16b, v3.16b",
"str q2, [x20, #1056]"
]
},
"fcmovb st0, st1": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovb st0, st2": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovb st0, st3": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovb st0, st4": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovb st0, st5": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovb st0, st6": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovb st0, st7": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"csetm x20, lo",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmove st0, st0": {
"ExpectedInstructionCount": 7,
"Comment": [
"0xda 11b 0xc8 /1"
],
"ExpectedArm64ASM": [
"csetm x20, eq",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"bsl v2.16b, v3.16b, v3.16b",
"str q2, [x20, #1056]"
]
},
"fcmove st0, st1": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xc9 /1"
],
"ExpectedArm64ASM": [
"csetm x20, eq",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmove st0, st2": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xca /1"
],
"ExpectedArm64ASM": [
"csetm x20, eq",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmove st0, st3": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xcb /1"
],
"ExpectedArm64ASM": [
"csetm x20, eq",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmove st0, st4": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xcc /1"
],
"ExpectedArm64ASM": [
"csetm x20, eq",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmove st0, st5": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xcd /1"
],
"ExpectedArm64ASM": [
"csetm x20, eq",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmove st0, st6": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xce /1"
],
"ExpectedArm64ASM": [
"csetm x20, eq",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmove st0, st7": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xcf /1"
],
"ExpectedArm64ASM": [
"csetm x20, eq",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovbe st0, st0": {
"ExpectedInstructionCount": 7,
"Comment": [
"0xda 11b 0xd0 /0"
],
"ExpectedArm64ASM": [
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"bsl v2.16b, v3.16b, v3.16b",
"str q2, [x20, #1056]"
]
},
"fcmovbe st0, st1": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xd1 /0"
],
"ExpectedArm64ASM": [
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovbe st0, st2": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xd2 /0"
],
"ExpectedArm64ASM": [
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovbe st0, st3": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xd3 /0"
],
"ExpectedArm64ASM": [
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovbe st0, st4": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xd4 /0"
],
"ExpectedArm64ASM": [
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovbe st0, st5": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xd5 /0"
],
"ExpectedArm64ASM": [
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovbe st0, st6": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xd6 /0"
],
"ExpectedArm64ASM": [
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovbe st0, st7": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xda 11b 0xd7 /0"
],
"ExpectedArm64ASM": [
"csetm x20, ls",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovu st0, st0": {
"ExpectedInstructionCount": 10,
"Comment": [
"0xda 11b 0xd8 /1"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"bsl v2.16b, v3.16b, v3.16b",
"str q2, [x20, #1056]"
]
},
"fcmovu st0, st1": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xda 11b 0xd9 /1"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovu st0, st2": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xda 11b 0xda /1"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovu st0, st3": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xda 11b 0xdb /1"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovu st0, st4": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xda 11b 0xdc /1"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovu st0, st5": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xda 11b 0xdd /1"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovu st0, st6": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xda 11b 0xde /1"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovu st0, st7": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xda 11b 0xdf /1"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eon w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fucompp": {
"ExpectedInstructionCount": 37,
"Comment": [
"0xda 11b 0xe9 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0xc0c0",
"lsr w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fild dword [rax]": {
"ExpectedInstructionCount": 33,
"Comment": [
"0xdf !11b /5"
],
"ExpectedArm64ASM": [
"ldr w20, [x4]",
"sxtw x20, w20",
"mrs x21, nzcv",
"mov w22, #0x0",
"cmp x20, #0x0 (0)",
"mov w23, #0x8000",
"csel x23, x23, x22, lt",
"cneg x20, x20, mi",
"mov w24, #0x3f",
"mov x0, #0x3f",
"clz x30, x20",
"sub x30, x0, x30",
"sub x24, x24, x30",
"lsl x30, x20, x24",
"mov w18, #0x403e",
"sub x24, x18, x24",
"cmp x20, #0x0 (0)",
"csel x20, x22, x24, eq",
"orr x20, x23, x20",
"fmov d2, x30",
"fmov v2.D[1], x20",
"msr nzcv, x21",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fisttp dword [rax]": {
"ExpectedInstructionCount": 19,
"Comment": [
"0xdb !11b /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1768]",
"ldr x3, [x28, #1776]",
"blr x0",
"ldr x30, [sp], #16",
"mov w21, w0",
"str w21, [x4]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fist dword [rax]": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb !11b /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1720]",
"ldr x3, [x28, #1728]",
"blr x0",
"ldr x30, [sp], #16",
"mov w20, w0",
"str w20, [x4]"
]
},
"fistp dword [rax]": {
"ExpectedInstructionCount": 19,
"Comment": [
"0xdf !11b /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1720]",
"ldr x3, [x28, #1728]",
"blr x0",
"ldr x30, [sp], #16",
"mov w21, w0",
"str w21, [x4]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fld tword [rax]": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xdb !11b /5"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"add x20, x4, #0x8 (8)",
"ld1 {v2.h}[4], [x20]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fstp tword [rax]": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xdb !11b /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str d2, [x4]",
"mov x21, v2.d[1]",
"strh w21, [x4, #8]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcmovnb st0, st0": {
"ExpectedInstructionCount": 7,
"Comment": [
"0xdb 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"bsl v2.16b, v3.16b, v3.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnb st0, st1": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnb st0, st2": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnb st0, st3": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnb st0, st4": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnb st0, st5": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnb st0, st6": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnb st0, st7": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"csetm x20, hs",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovne st0, st0": {
"ExpectedInstructionCount": 7,
"Comment": [
"0xdb 11b 0xc8 /1"
],
"ExpectedArm64ASM": [
"csetm x20, ne",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"bsl v2.16b, v3.16b, v3.16b",
"str q2, [x20, #1056]"
]
},
"fcmovne st0, st1": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xc9 /1"
],
"ExpectedArm64ASM": [
"csetm x20, ne",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovne st0, st2": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xca /1"
],
"ExpectedArm64ASM": [
"csetm x20, ne",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovne st0, st3": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xcb /1"
],
"ExpectedArm64ASM": [
"csetm x20, ne",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovne st0, st4": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xcc /1"
],
"ExpectedArm64ASM": [
"csetm x20, ne",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovne st0, st5": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xcd /1"
],
"ExpectedArm64ASM": [
"csetm x20, ne",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovne st0, st6": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xce /1"
],
"ExpectedArm64ASM": [
"csetm x20, ne",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovne st0, st7": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xcf /1"
],
"ExpectedArm64ASM": [
"csetm x20, ne",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnbe st0, st0": {
"ExpectedInstructionCount": 7,
"Comment": [
"0xdb 11b 0xd0 /2"
],
"ExpectedArm64ASM": [
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"bsl v2.16b, v3.16b, v3.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnbe st0, st1": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xd1 /2"
],
"ExpectedArm64ASM": [
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnbe st0, st2": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xd2 /2"
],
"ExpectedArm64ASM": [
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnbe st0, st3": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xd3 /2"
],
"ExpectedArm64ASM": [
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnbe st0, st4": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xd4 /2"
],
"ExpectedArm64ASM": [
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnbe st0, st5": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xd5 /2"
],
"ExpectedArm64ASM": [
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnbe st0, st6": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xd6 /2"
],
"ExpectedArm64ASM": [
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnbe st0, st7": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdb 11b 0xd7 /2"
],
"ExpectedArm64ASM": [
"csetm x20, hi",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnu st0, st0": {
"ExpectedInstructionCount": 10,
"Comment": [
"0xdb 11b 0xd8 /3"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"bsl v2.16b, v3.16b, v3.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnu st0, st1": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xdb 11b 0xd9 /3"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnu st0, st2": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xdb 11b 0xda /3"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnu st0, st3": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xdb 11b 0xdb /3"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnu st0, st4": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xdb 11b 0xdc /3"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnu st0, st5": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xdb 11b 0xdd /3"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnu st0, st6": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xdb 11b 0xde /3"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fcmovnu st0, st7": {
"ExpectedInstructionCount": 14,
"Comment": [
"0xdb 11b 0xdf /3"
],
"ExpectedArm64ASM": [
"eor w0, w26, w26, lsr #4",
"eor w0, w0, w0, lsr #2",
"eor w20, w0, w0, lsr #1",
"sbfx x20, x20, #0, #1",
"dup v2.2d, x20",
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q4, [x20, #1056]",
"bsl v2.16b, v3.16b, v4.16b",
"str q2, [x20, #1056]"
]
},
"fnclex": {
"ExpectedInstructionCount": 1,
"Comment": [
"0xdb 11b 0xe2 /4"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1040]"
]
},
"fninit": {
"ExpectedInstructionCount": 9,
"Comment": [
"0xdb 11b 0xe3 /4"
],
"ExpectedArm64ASM": [
"mov w20, #0x37f",
"strh w20, [x28, #1200]",
"strb wzr, [x28, #1051]",
"strb wzr, [x28, #1202]",
"strb wzr, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb wzr, [x28, #1050]",
"strb wzr, [x28, #1054]",
"strb wzr, [x28, #1040]"
]
},
"fucomi st0, st0": {
"ExpectedInstructionCount": 28,
"Comment": [
"0xdb 11b 0xe8 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fucomi st0, st1": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xe9 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fucomi st0, st2": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xea /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fucomi st0, st3": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xeb /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fucomi st0, st4": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xec /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fucomi st0, st5": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xed /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fucomi st0, st6": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xee /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fucomi st0, st7": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xef /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fcomi st0, st0": {
"ExpectedInstructionCount": 28,
"Comment": [
"0xdb 11b 0xf0 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fcomi st0, st1": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xf1 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fcomi st0, st2": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xf2 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fcomi st0, st3": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xf3 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fcomi st0, st4": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xf4 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fcomi st0, st5": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xf5 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fcomi st0, st6": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xf6 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fcomi st0, st7": {
"ExpectedInstructionCount": 32,
"Comment": [
"0xdb 11b 0xf7 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"eor x21, x21, #0x1",
"mrs x23, nzcv",
"bfi w23, w21, #29, #1",
"bfi w23, w22, #30, #1",
"eor w26, w20, #0x1",
"mov w27, #0x0",
"bfi w23, w27, #28, #1",
"bfi w23, w27, #31, #1",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"msr nzcv, x23"
]
},
"fadd qword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xdc !11b /0"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul qword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xdc !11b /1"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fcom qword [rax]": {
"ExpectedInstructionCount": 31,
"Comment": [
"0xdc !11b /2"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fcomp qword [rax]": {
"ExpectedInstructionCount": 39,
"Comment": [
"0xdc !11b /3"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsub qword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xdc !11b /4"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsubr qword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xdc !11b /5"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv qword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xdc !11b /6"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdivr qword [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xdc !11b /7"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"db 0xdc, 0xc0": {
"ExpectedInstructionCount": 12,
"Comment": [
"fadd st0, st0",
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
"0xdc 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st1, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st2, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st3, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st4, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st5, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st6, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fadd st7, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"db 0xdc, 0xc8": {
"ExpectedInstructionCount": 12,
"Comment": [
"fmul st0, st0",
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
"0xdc 11b 0xc8 /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st1, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xc9 /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st2, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xca /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st3, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xcb /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st4, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xcc /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st5, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xcd /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st6, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xce /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fmul st7, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xcf /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"db 0xdc, 0xe0": {
"ExpectedInstructionCount": 12,
"Comment": [
"fsubr st0, st0",
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
"0xdc 11b 0xe0 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsubr st1, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xe1 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st2, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xe2 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st3, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xe3 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st4, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xe4 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st5, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xe5 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st6, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xe6 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fsubr st7, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xe7 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"db 0xdc, 0xe8": {
"ExpectedInstructionCount": 12,
"Comment": [
"fsub st0, st0",
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
"0xdc 11b 0xe8 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st1, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xe9 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st2, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xea /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st3, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xeb /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st4, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xec /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st5, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xed /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st6, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xee /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fsub st7, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xef /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"db 0xdc, 0xf0": {
"ExpectedInstructionCount": 12,
"Comment": [
"fdivr st0, st0",
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
"0xdc 11b 0xf0 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdivr st1, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xf1 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st2, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xf2 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st3, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xf3 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st4, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xf4 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st5, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xf5 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st6, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xf6 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"fdivr st7, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xf7 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x21, #1056]"
]
},
"db 0xdc, 0xf8": {
"ExpectedInstructionCount": 12,
"Comment": [
"fdiv st0, st0",
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
"0xdc 11b 0xf8 /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st1, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xf9 /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st2, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xfa /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st3, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xfb /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st4, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xfc /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st5, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xfd /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st6, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xfe /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fdiv st7, st0": {
"ExpectedInstructionCount": 16,
"Comment": [
"0xdc 11b 0xff /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fld qword [rax]": {
"ExpectedInstructionCount": 19,
"Comment": [
"0xdd !11b /0"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str x30, [sp, #-16]!",
"fmov d0, d2",
"ldr x0, [x28, #1656]",
"ldr x3, [x28, #1664]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fisttp qword [rax]": {
"ExpectedInstructionCount": 19,
"Comment": [
"0xdd !11b /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1784]",
"ldr x3, [x28, #1792]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"str x21, [x4]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst qword [rax]": {
"ExpectedInstructionCount": 11,
"Comment": [
"0xdd !11b /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d2, d0",
"str d2, [x4]"
]
},
"fstp qword [rax]": {
"ExpectedInstructionCount": 19,
"Comment": [
"0xdd !11b /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1688]",
"ldr x3, [x28, #1696]",
"blr x0",
"ldr x30, [sp], #16",
"fmov d2, d0",
"str d2, [x4]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"frstor [rax]": {
"ExpectedInstructionCount": 76,
"Comment": [
"0xdd !11b /4"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"strh w20, [x28, #1200]",
"ldr w20, [x4, #4]",
"ubfx w21, w20, #11, #3",
"strb w21, [x28, #1051]",
"ubfx w22, w20, #8, #1",
"ubfx w23, w20, #9, #1",
"ubfx w24, w20, #10, #1",
"ubfx w30, w20, #14, #1",
"ubfx w20, w20, #0, #1",
"strb w22, [x28, #1048]",
"strb w23, [x28, #1049]",
"strb w24, [x28, #1050]",
"strb w30, [x28, #1054]",
"strb w20, [x28, #1040]",
"ldr w20, [x4, #8]",
"and w20, w20, w20, lsr #1",
"mov w22, #0x55555555",
"bic w20, w22, w20",
"orr w20, w20, w20, lsr #1",
"and w20, w20, #0x33333333",
"orr w20, w20, w20, lsr #2",
"and w20, w20, #0xf0f0f0f",
"orr w20, w20, w20, lsr #4",
"strb w20, [x28, #1202]",
"mov x20, #0xffffffffffffffff",
"mov w22, #0xffff",
"fmov d2, x20",
"fmov v2.D[1], x22",
"ldur q3, [x4, #28]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x21, lsl #4",
"str q3, [x0, #1056]",
"add w20, w21, #0x1 (1)",
"and w20, w20, #0x7",
"ldur q3, [x4, #38]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldr q3, [x4, #48]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldur q3, [x4, #58]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldur q3, [x4, #68]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldur q3, [x4, #78]",
"and v3.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q3, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldur q3, [x4, #88]",
"and v2.16b, v3.16b, v2.16b",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"ldur d2, [x4, #98]",
"ldr h3, [x4, #106]",
"mov v2.h[4], v3.h[0]",
"add x0, x28, x20, lsl #4",
"str q2, [x0, #1056]"
]
},
"fnsave [rax]": {
"ExpectedInstructionCount": 79,
"Comment": [
"0xdd !11b /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"ldrh w21, [x28, #1200]",
"str w21, [x4]",
"ldrb w21, [x28, #1051]",
"lsl x21, x21, #11",
"ldrb w22, [x28, #1048]",
"orr x21, x21, x22, lsl #8",
"ldrb w22, [x28, #1049]",
"orr x21, x21, x22, lsl #9",
"ldrb w22, [x28, #1050]",
"orr x21, x21, x22, lsl #10",
"ldrb w22, [x28, #1054]",
"orr x21, x21, x22, lsl #14",
"ldrb w22, [x28, #1040]",
"orr x21, x21, x22",
"str w21, [x4, #4]",
"ldrb w21, [x28, #1202]",
"orr w21, w21, w21, lsl #4",
"and w21, w21, #0xf0f0f0f",
"orr w21, w21, w21, lsl #2",
"and w21, w21, #0x33333333",
"orr w21, w21, w21, lsl #1",
"and w21, w21, #0x55555555",
"orr w21, w21, w21, lsl #1",
"eor w21, w21, #0xffff",
"str w21, [x4, #8]",
"str wzr, [x4, #12]",
"str wzr, [x4, #16]",
"str wzr, [x4, #20]",
"str wzr, [x4, #24]",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"stur q2, [x4, #28]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"stur q2, [x4, #38]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"str q2, [x4, #48]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"stur q2, [x4, #58]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"stur q2, [x4, #68]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"stur q2, [x4, #78]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"stur q2, [x4, #88]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x0, x28, x20, lsl #4",
"ldr q2, [x0, #1056]",
"stur d2, [x4, #98]",
"dup v2.8h, v2.h[4]",
"str h2, [x4, #106]",
"mov w20, #0x37f",
"strh w20, [x28, #1200]",
"strb wzr, [x28, #1051]",
"strb wzr, [x28, #1202]",
"strb wzr, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb wzr, [x28, #1050]",
"strb wzr, [x28, #1054]",
"strb wzr, [x28, #1040]"
]
},
"fnstsw [rax]": {
"ExpectedInstructionCount": 13,
"Comment": [
"0xdd !11b /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1048]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1049]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1050]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1054]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #1040]",
"orr x20, x20, x21",
"strh w20, [x4]"
]
},
"ffree st0": {
"ExpectedInstructionCount": 6,
"Comment": [
"0xdd 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"ffree st1": {
"ExpectedInstructionCount": 8,
"Comment": [
"0xdd 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"ffree st2": {
"ExpectedInstructionCount": 8,
"Comment": [
"0xdd 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"ffree st3": {
"ExpectedInstructionCount": 8,
"Comment": [
"0xdd 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"ffree st4": {
"ExpectedInstructionCount": 8,
"Comment": [
"0xdd 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"ffree st5": {
"ExpectedInstructionCount": 8,
"Comment": [
"0xdd 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"ffree st6": {
"ExpectedInstructionCount": 8,
"Comment": [
"0xdd 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"ffree st7": {
"ExpectedInstructionCount": 8,
"Comment": [
"0xdd 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst st0": {
"ExpectedInstructionCount": 9,
"Comment": [
"0xdd 11b 0xd0 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst st1": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xdd 11b 0xd1 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst st2": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xdd 11b 0xd2 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst st3": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xdd 11b 0xd3 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst st4": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xdd 11b 0xd4 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst st5": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xdd 11b 0xd5 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst st6": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xdd 11b 0xd6 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fst st7": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xdd 11b 0xd7 /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fstp st0": {
"ExpectedInstructionCount": 12,
"Comment": [
"0xdd 11b 0xd8 /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fstp st1": {
"ExpectedInstructionCount": 15,
"Comment": [
"0xdd 11b 0xd9 /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"add x22, x28, x21, lsl #4",
"str q2, [x22, #1056]",
"ldrb w22, [x28, #1202]",
"mov w23, #0x1",
"lsl w21, w23, w21",
"orr w21, w22, w21",
"lsl w20, w23, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fstp st2": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xdd 11b 0xda /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"add w21, w21, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"str q2, [x22, #1056]",
"ldrb w22, [x28, #1202]",
"mov w23, #0x1",
"lsl w21, w23, w21",
"orr w21, w22, w21",
"lsl w20, w23, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fstp st3": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xdd 11b 0xdb /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"add w21, w21, #0x2 (2)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"str q2, [x22, #1056]",
"ldrb w22, [x28, #1202]",
"mov w23, #0x1",
"lsl w21, w23, w21",
"orr w21, w22, w21",
"lsl w20, w23, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fstp st4": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xdd 11b 0xdc /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"add w21, w21, #0x3 (3)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"str q2, [x22, #1056]",
"ldrb w22, [x28, #1202]",
"mov w23, #0x1",
"lsl w21, w23, w21",
"orr w21, w22, w21",
"lsl w20, w23, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fstp st5": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xdd 11b 0xdd /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"add w21, w21, #0x4 (4)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"str q2, [x22, #1056]",
"ldrb w22, [x28, #1202]",
"mov w23, #0x1",
"lsl w21, w23, w21",
"orr w21, w22, w21",
"lsl w20, w23, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fstp st6": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xdd 11b 0xde /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"add w21, w21, #0x5 (5)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"str q2, [x22, #1056]",
"ldrb w22, [x28, #1202]",
"mov w23, #0x1",
"lsl w21, w23, w21",
"orr w21, w22, w21",
"lsl w20, w23, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fstp st7": {
"ExpectedInstructionCount": 17,
"Comment": [
"0xdd 11b 0xdf /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"add w21, w21, #0x6 (6)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"str q2, [x22, #1056]",
"ldrb w22, [x28, #1202]",
"mov w23, #0x1",
"lsl w21, w23, w21",
"orr w21, w22, w21",
"lsl w20, w23, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucom st0": {
"ExpectedInstructionCount": 23,
"Comment": [
"0xdd 11b 0xe0 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fucom st1": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xdd 11b 0xe1 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fucom st2": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xdd 11b 0xe2 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x2 (2)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fucom st3": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xdd 11b 0xe3 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x3 (3)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fucom st4": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xdd 11b 0xe4 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x4 (4)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fucom st5": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xdd 11b 0xe5 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x5 (5)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fucom st6": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xdd 11b 0xe6 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x6 (6)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fucom st7": {
"ExpectedInstructionCount": 27,
"Comment": [
"0xdd 11b 0xe7 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"fucomp st0": {
"ExpectedInstructionCount": 31,
"Comment": [
"0xdd 11b 0xe8 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomp st1": {
"ExpectedInstructionCount": 33,
"Comment": [
"0xdd 11b 0xe9 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x22, x0",
"ubfx x23, x22, #1, #1",
"ubfx x24, x22, #0, #1",
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"strb w23, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w22, [x28, #1050]",
"strb w24, [x28, #1054]",
"ldrb w23, [x28, #1040]",
"orr w22, w23, w22",
"strb w22, [x28, #1040]",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomp st2": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xdd 11b 0xea /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomp st3": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xdd 11b 0xeb /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomp st4": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xdd 11b 0xec /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomp st5": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xdd 11b 0xed /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomp st6": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xdd 11b 0xee /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomp st7": {
"ExpectedInstructionCount": 35,
"Comment": [
"0xdd 11b 0xef /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fiadd word [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xde !11b /0"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"str x30, [sp, #-16]!",
"sxth w1, w20",
"ldr x0, [x28, #1816]",
"ldr x3, [x28, #1824]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fimul word [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xde !11b /1"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"str x30, [sp, #-16]!",
"sxth w1, w20",
"ldr x0, [x28, #1816]",
"ldr x3, [x28, #1824]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"ficom word [rax]": {
"ExpectedInstructionCount": 31,
"Comment": [
"0xde !11b /2"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"str x30, [sp, #-16]!",
"sxth w1, w20",
"ldr x0, [x28, #1816]",
"ldr x3, [x28, #1824]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x20, x0",
"ubfx x21, x20, #1, #1",
"ubfx x22, x20, #0, #1",
"ubfx x20, x20, #2, #1",
"orr w21, w21, w20",
"orr w22, w22, w20",
"strb w21, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w20, [x28, #1050]",
"strb w22, [x28, #1054]",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]"
]
},
"ficomp word [rax]": {
"ExpectedInstructionCount": 39,
"Comment": [
"0xde !11b /3"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"str x30, [sp, #-16]!",
"sxth w1, w20",
"ldr x0, [x28, #1816]",
"ldr x3, [x28, #1824]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fisub word [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xde !11b /4"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"str x30, [sp, #-16]!",
"sxth w1, w20",
"ldr x0, [x28, #1816]",
"ldr x3, [x28, #1824]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fisubr word [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xde !11b /5"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"str x30, [sp, #-16]!",
"sxth w1, w20",
"ldr x0, [x28, #1816]",
"ldr x3, [x28, #1824]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fidiv word [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xde !11b /6"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"str x30, [sp, #-16]!",
"sxth w1, w20",
"ldr x0, [x28, #1816]",
"ldr x3, [x28, #1824]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"fidivr word [rax]": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xde !11b /7"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"str x30, [sp, #-16]!",
"sxth w1, w20",
"ldr x0, [x28, #1816]",
"ldr x3, [x28, #1824]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q3, [x20, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str q2, [x20, #1056]"
]
},
"faddp st0": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xd8 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"faddp st1": {
"ExpectedInstructionCount": 22,
"Comment": [
"0xde 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb w21, [x28, #1051]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"faddp st2": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"faddp st3": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"faddp st4": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"faddp st5": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"faddp st6": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"faddp st7": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2024]",
"ldr x3, [x28, #2032]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fmulp st0": {
"ExpectedInstructionCount": 20,
"Comment": [
"0xde 11b 0xc8 /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fmulp st1": {
"ExpectedInstructionCount": 22,
"Comment": [
"0xde 11b 0xc9 /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb w21, [x28, #1051]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fmulp st2": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xca /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fmulp st3": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xcb /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fmulp st4": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xcc /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fmulp st5": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xcd /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fmulp st6": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xce /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fmulp st7": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xcf /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2056]",
"ldr x3, [x28, #2064]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcompp": {
"ExpectedInstructionCount": 37,
"Comment": [
"0xde 11b 0xd9 /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"add x21, x28, x20, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"strb w22, [x28, #1048]",
"strb wzr, [x28, #1049]",
"strb w21, [x28, #1050]",
"strb w23, [x28, #1054]",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x8",
"sub w20, w22, w20",
"mov w22, #0xc0c0",
"lsr w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"db 0xde, 0xe0": {
"ExpectedInstructionCount": 20,
"Comment": [
"fsubrp st0, st0",
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
"0xde 11b 0xe0 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubrp st1, st0": {
"ExpectedInstructionCount": 22,
"Comment": [
"0xde 11b 0xe1 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q2, [x22, #1056]",
"add x23, x28, x20, lsl #4",
"ldr q3, [x23, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb w21, [x28, #1051]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubrp st2, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xe2 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubrp st3, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xe3 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubrp st4, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xe4 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubrp st5, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xe5 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubrp st6, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xe6 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubrp st7, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xe7 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"db 0xde, 0xe8": {
"ExpectedInstructionCount": 20,
"Comment": [
"fsubp st0, st0",
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
"0xde 11b 0xe8 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubp st1, st0": {
"ExpectedInstructionCount": 22,
"Comment": [
"0xde 11b 0xe9 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb w21, [x28, #1051]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubp st2, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xea /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubp st3, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xeb /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubp st4, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xec /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubp st5, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xed /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubp st6, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xee /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fsubp st7, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xef /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2040]",
"ldr x3, [x28, #2048]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"db 0xde, 0xf0": {
"ExpectedInstructionCount": 20,
"Comment": [
"fdivrp st0, st0",
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
"0xde 11b 0xf0 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivrp st1, st0": {
"ExpectedInstructionCount": 22,
"Comment": [
"0xde 11b 0xf1 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q2, [x22, #1056]",
"add x23, x28, x20, lsl #4",
"ldr q3, [x23, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb w21, [x28, #1051]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivrp st2, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xf2 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivrp st3, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xf3 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivrp st4, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xf4 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivrp st5, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xf5 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivrp st6, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xf6 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivrp st7, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xf7 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q2, [x21, #1056]",
"add x22, x28, x20, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"db 0xde, 0xf8": {
"ExpectedInstructionCount": 20,
"Comment": [
"fdivp st0, st0",
"Needs manual encoding since otherwise nasm will emit the 0xd8 variant.",
"0xde 11b 0xf8 /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivp st1, st0": {
"ExpectedInstructionCount": 22,
"Comment": [
"0xde 11b 0xf9 /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"strb w21, [x28, #1051]",
"str q2, [x22, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivp st2, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xfa /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivp st3, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xfb /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivp st4, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xfc /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivp st5, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xfd /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivp st6, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xfe /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fdivp st7, st0": {
"ExpectedInstructionCount": 24,
"Comment": [
"0xde 11b 0xff /7"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v3.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #2072]",
"ldr x3, [x28, #2080]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"add w22, w20, #0x1 (1)",
"and w22, w22, #0x7",
"strb w22, [x28, #1051]",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fild word [rax]": {
"ExpectedInstructionCount": 33,
"Comment": [
"0xdf !11b /0"
],
"ExpectedArm64ASM": [
"ldrh w20, [x4]",
"sxth x20, w20",
"mrs x21, nzcv",
"mov w22, #0x0",
"cmp x20, #0x0 (0)",
"mov w23, #0x8000",
"csel x23, x23, x22, lt",
"cneg x20, x20, mi",
"mov w24, #0x3f",
"mov x0, #0x3f",
"clz x30, x20",
"sub x30, x0, x30",
"sub x24, x24, x30",
"lsl x30, x20, x24",
"mov w18, #0x403e",
"sub x24, x18, x24",
"cmp x20, #0x0 (0)",
"csel x20, x22, x24, eq",
"orr x20, x23, x20",
"fmov d2, x30",
"fmov v2.D[1], x20",
"msr nzcv, x21",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fisttp word [rax]": {
"ExpectedInstructionCount": 33,
"Comment": [
"0xdf !11b /1"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"mov x21, v2.d[1]",
"mov w22, #0x7fff",
"and x21, x21, #0x7fff",
"mrs x23, nzcv",
"cmp x21, x22",
"cset x22, eq",
"mov w24, #0x400e",
"cmp x21, x24",
"cset x21, hs",
"orr x21, x22, x21",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1752]",
"ldr x3, [x28, #1760]",
"blr x0",
"ldr x30, [sp], #16",
"mov w21, w0",
"strh w21, [x4]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x23",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fist word [rax]": {
"ExpectedInstructionCount": 25,
"Comment": [
"0xdf !11b /2"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x20, x28, x20, lsl #4",
"ldr q2, [x20, #1056]",
"mov x20, v2.d[1]",
"mov w21, #0x7fff",
"and x20, x20, #0x7fff",
"mrs x22, nzcv",
"cmp x20, x21",
"cset x21, eq",
"mov w23, #0x400e",
"cmp x20, x23",
"cset x20, hs",
"orr x20, x21, x20",
"ldrb w21, [x28, #1040]",
"orr w20, w21, w20",
"strb w20, [x28, #1040]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1704]",
"ldr x3, [x28, #1712]",
"blr x0",
"ldr x30, [sp], #16",
"mov w20, w0",
"strh w20, [x4]",
"msr nzcv, x22"
]
},
"fistp word [rax]": {
"ExpectedInstructionCount": 33,
"Comment": [
"0xdf !11b /3"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"mov x21, v2.d[1]",
"mov w22, #0x7fff",
"and x21, x21, #0x7fff",
"mrs x23, nzcv",
"cmp x21, x22",
"cset x22, eq",
"mov w24, #0x400e",
"cmp x21, x24",
"cset x21, hs",
"orr x21, x22, x21",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1704]",
"ldr x3, [x28, #1712]",
"blr x0",
"ldr x30, [sp], #16",
"mov w21, w0",
"strh w21, [x4]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x23",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fbld tword [rax]": {
"ExpectedInstructionCount": 21,
"Comment": [
"0xdf !11b /4"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"add x20, x4, #0x8 (8)",
"ld1 {v2.h}[4], [x20]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #2008]",
"ldr x3, [x28, #2016]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"str q2, [x21, #1056]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"orr w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fbstp tword [rax]": {
"ExpectedInstructionCount": 21,
"Comment": [
"0xdf !11b /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"ldr x0, [x28, #1992]",
"ldr x3, [x28, #2000]",
"blr x0",
"ldr x30, [sp], #16",
"mov v2.16b, v0.16b",
"str d2, [x4]",
"mov x21, v2.d[1]",
"strh w21, [x4, #8]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"ffreep st0": {
"ExpectedInstructionCount": 5,
"Comment": [
"0xdf 11b 0xc0 /0"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1049]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]"
]
},
"ffreep st1": {
"ExpectedInstructionCount": 5,
"Comment": [
"0xdf 11b 0xc1 /0"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1049]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]"
]
},
"ffreep st2": {
"ExpectedInstructionCount": 5,
"Comment": [
"0xdf 11b 0xc2 /0"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1049]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]"
]
},
"ffreep st3": {
"ExpectedInstructionCount": 5,
"Comment": [
"0xdf 11b 0xc3 /0"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1049]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]"
]
},
"ffreep st4": {
"ExpectedInstructionCount": 5,
"Comment": [
"0xdf 11b 0xc4 /0"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1049]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]"
]
},
"ffreep st5": {
"ExpectedInstructionCount": 5,
"Comment": [
"0xdf 11b 0xc5 /0"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1049]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]"
]
},
"ffreep st6": {
"ExpectedInstructionCount": 5,
"Comment": [
"0xdf 11b 0xc6 /0"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1049]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]"
]
},
"ffreep st7": {
"ExpectedInstructionCount": 5,
"Comment": [
"0xdf 11b 0xc7 /0"
],
"ExpectedArm64ASM": [
"strb wzr, [x28, #1049]",
"ldrb w20, [x28, #1051]",
"add w20, w20, #0x1 (1)",
"and w20, w20, #0x7",
"strb w20, [x28, #1051]"
]
},
"fnstsw ax": {
"ExpectedInstructionCount": 13,
"Comment": [
"0xdf 11b 0xe0 /4"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"lsl x20, x20, #11",
"ldrb w21, [x28, #1048]",
"orr x20, x20, x21, lsl #8",
"ldrb w21, [x28, #1049]",
"orr x20, x20, x21, lsl #9",
"ldrb w21, [x28, #1050]",
"orr x20, x20, x21, lsl #10",
"ldrb w21, [x28, #1054]",
"orr x20, x20, x21, lsl #14",
"ldrb w21, [x28, #1040]",
"orr x20, x20, x21",
"bfxil x4, x20, #0, #16"
]
},
"fucomip st0": {
"ExpectedInstructionCount": 36,
"Comment": [
"0xdf 11b 0xe8 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomip st1": {
"ExpectedInstructionCount": 38,
"Comment": [
"0xdf 11b 0xe9 /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x22, x0",
"ubfx x23, x22, #1, #1",
"ubfx x24, x22, #0, #1",
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"eor x23, x23, #0x1",
"mrs x30, nzcv",
"bfi w30, w23, #29, #1",
"bfi w30, w24, #30, #1",
"eor w26, w22, #0x1",
"mov w27, #0x0",
"bfi w30, w27, #28, #1",
"bfi w30, w27, #31, #1",
"ldrb w23, [x28, #1040]",
"orr w22, w23, w22",
"strb w22, [x28, #1040]",
"msr nzcv, x30",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomip st2": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xea /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomip st3": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xeb /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomip st4": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xec /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomip st5": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xed /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomip st6": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xee /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fucomip st7": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xef /5"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomip st0": {
"ExpectedInstructionCount": 36,
"Comment": [
"0xdf 11b 0xf0 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v2.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomip st1": {
"ExpectedInstructionCount": 38,
"Comment": [
"0xdf 11b 0xf1 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"add x22, x28, x21, lsl #4",
"ldr q3, [x22, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x22, x0",
"ubfx x23, x22, #1, #1",
"ubfx x24, x22, #0, #1",
"ubfx x22, x22, #2, #1",
"orr w23, w23, w22",
"orr w24, w24, w22",
"eor x23, x23, #0x1",
"mrs x30, nzcv",
"bfi w30, w23, #29, #1",
"bfi w30, w24, #30, #1",
"eor w26, w22, #0x1",
"mov w27, #0x0",
"bfi w30, w27, #28, #1",
"bfi w30, w27, #31, #1",
"ldrb w23, [x28, #1040]",
"orr w22, w23, w22",
"strb w22, [x28, #1040]",
"msr nzcv, x30",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomip st2": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xf2 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x2 (2)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomip st3": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xf3 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x3 (3)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomip st4": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xf4 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x4 (4)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomip st5": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xf5 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x5 (5)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomip st6": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xf6 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x6 (6)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"fcomip st7": {
"ExpectedInstructionCount": 40,
"Comment": [
"0xdf 11b 0xf7 /6"
],
"ExpectedArm64ASM": [
"ldrb w20, [x28, #1051]",
"add x21, x28, x20, lsl #4",
"ldr q2, [x21, #1056]",
"add w21, w20, #0x7 (7)",
"and w21, w21, #0x7",
"add x21, x28, x21, lsl #4",
"ldr q3, [x21, #1056]",
"str x30, [sp, #-16]!",
"mov v0.16b, v2.16b",
"mov v1.16b, v3.16b",
"ldr x0, [x28, #1800]",
"ldr x3, [x28, #1808]",
"blr x0",
"ldr x30, [sp], #16",
"mov x21, x0",
"ubfx x22, x21, #1, #1",
"ubfx x23, x21, #0, #1",
"ubfx x21, x21, #2, #1",
"orr w22, w22, w21",
"orr w23, w23, w21",
"eor x22, x22, #0x1",
"mrs x24, nzcv",
"bfi w24, w22, #29, #1",
"bfi w24, w23, #30, #1",
"eor w26, w21, #0x1",
"mov w27, #0x0",
"bfi w24, w27, #28, #1",
"bfi w24, w27, #31, #1",
"ldrb w22, [x28, #1040]",
"orr w21, w22, w21",
"strb w21, [x28, #1040]",
"add w21, w20, #0x1 (1)",
"and w21, w21, #0x7",
"msr nzcv, x24",
"strb w21, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"memcpy4_32": {
"x86InstructionCount": 8,
"ExpectedInstructionCount": 16,
"x86Insts": [
"fld dword [rax]",
"fstp dword [rdx]",
"fld dword [rax + 4]",
"fstp dword [rdx + 4]",
"fld dword [rax + 8]",
"fstp dword [rdx + 8]",
"fld dword [rax + 12]",
"fstp dword [rdx + 12]"
],
"ExpectedArm64ASM": [
"ldr s2, [x4]",
"str s2, [x5]",
"ldr s2, [x4, #4]",
"str s2, [x5, #4]",
"ldr s2, [x4, #8]",
"str s2, [x5, #8]",
"ldr s2, [x4, #12]",
"str s2, [x5, #12]",
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"memcpy4_64": {
"x86InstructionCount": 8,
"ExpectedInstructionCount": 16,
"x86Insts": [
"fld qword [rax]",
"fstp qword [rdx]",
"fld qword [rax + 8]",
"fstp qword [rdx + 8]",
"fld qword [rax + 16]",
"fstp qword [rdx + 16]",
"fld qword [rax + 32]",
"fstp qword [rdx + 32]"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"str d2, [x5]",
"ldr d2, [x4, #8]",
"str d2, [x5, #8]",
"ldr d2, [x4, #16]",
"str d2, [x5, #16]",
"ldr d2, [x4, #32]",
"str d2, [x5, #32]",
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"Multiple fld/fst": {
"x86InstructionCount": 4,
"ExpectedInstructionCount": 22,
"x86Insts": [
"fld qword [ebp+16380]",
"fstp qword [eax-0x4]",
"fld qword [ebp-0x8]",
"fstp qword [eax+16370]"
],
"ExpectedArm64ASM": [
"mov w20, #0x3ffc",
"add x20, x9, x20",
"mov w20, w20",
"ldr d2, [x20]",
"sub x20, x4, #0x4 (4)",
"mov w20, w20",
"str d2, [x20]",
"sub x20, x9, #0x8 (8)",
"mov w20, w20",
"ldr d2, [x20]",
"mov w20, #0x3ff2",
"add x20, x4, x20",
"mov w20, w20",
"str d2, [x20]",
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
},
"memcpy4_80": {
"x86InstructionCount": 8,
"ExpectedInstructionCount": 38,
"x86Insts": [
"fld tword [rax]",
"fstp tword [rdx]",
"fld tword [rax + 10]",
"fstp tword [rdx + 10]",
"fld tword [rax + 20]",
"fstp tword [rdx + 20]",
"fld tword [rax + 30]",
"fstp tword [rdx + 30]"
],
"ExpectedArm64ASM": [
"ldr d2, [x4]",
"add x20, x4, #0x8 (8)",
"ld1 {v2.h}[4], [x20]",
"str d2, [x5]",
"mov x20, v2.d[1]",
"strh w20, [x5, #8]",
"add x20, x4, #0xa (10)",
"ldr d2, [x20]",
"add x20, x20, #0x8 (8)",
"ld1 {v2.h}[4], [x20]",
"stur d2, [x5, #10]",
"mov x20, v2.d[1]",
"add x21, x5, #0xa (10)",
"strh w20, [x21, #8]",
"add x20, x4, #0x14 (20)",
"ldr d2, [x20]",
"add x20, x20, #0x8 (8)",
"ld1 {v2.h}[4], [x20]",
"stur d2, [x5, #20]",
"mov x20, v2.d[1]",
"add x21, x5, #0x14 (20)",
"strh w20, [x21, #8]",
"add x20, x4, #0x1e (30)",
"ldr d2, [x20]",
"add x20, x20, #0x8 (8)",
"ld1 {v2.h}[4], [x20]",
"stur d2, [x5, #30]",
"mov x20, v2.d[1]",
"add x21, x5, #0x1e (30)",
"strh w20, [x21, #8]",
"ldrb w20, [x28, #1051]",
"ldrb w21, [x28, #1202]",
"mov w22, #0x1",
"add w20, w20, #0x7 (7)",
"and w20, w20, #0x7",
"lsl w20, w22, w20",
"bic w20, w21, w20",
"strb w20, [x28, #1202]"
]
}
}
}
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