Alyssa Rosenzweig dcb09b085b OpcodeDispatcher: Use AddNZCV/SubNZCV ...

32-bit or 64-bit addition without carry-in. This matches the baseline hardware
semantic. Generalizing to support other cases can come later, this should be a
win already.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>

2023-08-31 09:05:41 -04:00

..

Crypto.cpp

Arm64: Optimize AES operations by caching a zero register

2023-08-30 19:00:43 -07:00

Flags.cpp

OpcodeDispatcher: Use AddNZCV/SubNZCV

2023-08-31 09:05:41 -04:00

Vector.cpp

OpcodeDispatcher: Be super defensive when starting a new block

2023-08-30 20:43:11 -07:00

X87.cpp

IR: Removes implicit sized add

2023-08-29 22:26:51 -07:00

X87F64.cpp

IR: Removes implicit sized add

2023-08-29 22:26:51 -07:00