FEX-Emu--FEX/unittests/InstructionCountCI/PrimaryGroup.json

{
  "Features": {
    "Bitness": 64,
    "EnabledHostFeatures": [],
    "DisabledHostFeatures": [
      "SVE128",
      "SVE256",
      "AFP",
      "FLAGM",
      "FLAGM2"
    ]
  },
  "Comment": [
    "Instructions in this table that are marked optimal don't have their flag calculation part of this assumption",
    "Flags calculation can dramatically change an instruction's lengths so this is mostly ignored here."
  ],
  "Instructions": {
    "add al, 1": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP1 0x80 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "lsl w0, w4, #24",
        "cmn w0, w20, lsl #24",
        "add w26, w4, #0x1 (1)",
        "mov x20, x4",
        "bfxil x20, x26, #0, #8",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "or al, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x80 /1",
      "ExpectedArm64ASM": [
        "orr w26, w4, #0x1",
        "cmn wzr, w26, lsl #24",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "adc al, 1": {
      "ExpectedInstructionCount": 19,
      "Comment": "GROUP1 0x80 /2",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "adc w20, wzr, w20",
        "add w21, w4, w20",
        "uxtb w26, w21",
        "cmp w26, w20",
        "cset x20, lo",
        "cmn wzr, w26, lsl #24",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "eor w21, w4, #0x1",
        "eor w22, w26, w4",
        "bic w21, w22, w21",
        "ubfx x21, x21, #7, #1",
        "orr w20, w20, w21, lsl #28",
        "mov x21, x4",
        "bfxil x21, x26, #0, #8",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x21"
      ]
    },
    "sbb al, 1": {
      "ExpectedInstructionCount": 20,
      "Comment": "GROUP1 0x80 /3",
      "ExpectedArm64ASM": [
        "uxtb w20, w4",
        "mov w21, #0x1",
        "adc w21, wzr, w21",
        "sub w22, w20, w21",
        "uxtb w26, w22",
        "cmp w20, w21",
        "cset x21, lo",
        "cmn wzr, w26, lsl #24",
        "mrs x22, nzcv",
        "orr w21, w22, w21, lsl #29",
        "eor w22, w20, #0x1",
        "eor w20, w26, w20",
        "and w20, w20, w22",
        "ubfx x20, x20, #7, #1",
        "orr w20, w21, w20, lsl #28",
        "mov x21, x4",
        "bfxil x21, x26, #0, #8",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x21"
      ]
    },
    "and al, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x80 /4",
      "ExpectedArm64ASM": [
        "and w26, w4, #0x1",
        "cmn wzr, w26, lsl #24",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "sub al, 1": {
      "ExpectedInstructionCount": 11,
      "Comment": "GROUP1 0x80 /5",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0x1 (1)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "mov x21, x4",
        "bfxil x21, x26, #0, #8",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x21"
      ]
    },
    "xor al, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x80 /6",
      "ExpectedArm64ASM": [
        "eor w26, w4, #0x1",
        "cmn wzr, w26, lsl #24",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "cmp al, 1": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP1 0x80 /7",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0x1 (1)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4"
      ]
    },
    "add al, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP1 0x80 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "mvn w27, w4",
        "lsl w0, w4, #24",
        "cmn w0, w20, lsl #24",
        "add w26, w4, #0xff (255)",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "or al, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x80 /1",
      "ExpectedArm64ASM": [
        "orr w26, w4, #0xff",
        "cmn wzr, w26, lsl #24",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "adc al, -1": {
      "ExpectedInstructionCount": 17,
      "Comment": "GROUP1 0x80 /2",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "mov w20, #0xff",
        "adc w20, wzr, w20",
        "add w21, w4, w20",
        "uxtb w26, w21",
        "cmp w26, w20",
        "cset x20, lo",
        "cmn wzr, w26, lsl #24",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "eor w21, w4, #0xff",
        "eor w22, w26, w4",
        "bic w21, w22, w21",
        "ubfx x21, x21, #7, #1",
        "orr w20, w20, w21, lsl #28",
        "bfxil x4, x26, #0, #8",
        "msr nzcv, x20"
      ]
    },
    "sbb al, -1": {
      "ExpectedInstructionCount": 18,
      "Comment": "GROUP1 0x80 /3",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "uxtb w20, w4",
        "mov w21, #0xff",
        "adc w21, wzr, w21",
        "sub w22, w20, w21",
        "uxtb w26, w22",
        "cmp w20, w21",
        "cset x21, lo",
        "cmn wzr, w26, lsl #24",
        "mrs x22, nzcv",
        "orr w21, w22, w21, lsl #29",
        "eor w22, w20, #0xff",
        "eor w20, w26, w20",
        "and w20, w20, w22",
        "ubfx x20, x20, #7, #1",
        "orr w20, w21, w20, lsl #28",
        "bfxil x4, x26, #0, #8",
        "msr nzcv, x20"
      ]
    },
    "and al, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x80 /4",
      "ExpectedArm64ASM": [
        "and w26, w4, #0xff",
        "cmn wzr, w26, lsl #24",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "sub al, -1": {
      "ExpectedInstructionCount": 9,
      "Comment": "GROUP1 0x80 /5",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "mvn w27, w4",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0xff (255)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "bfxil x4, x26, #0, #8",
        "msr nzcv, x20"
      ]
    },
    "xor al, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x80 /6",
      "ExpectedArm64ASM": [
        "eor w26, w4, #0xff",
        "cmn wzr, w26, lsl #24",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "cmp al, -1": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP1 0x80 /7",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "mvn w27, w4",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0xff (255)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20"
      ]
    },
    "add ax, 256": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP1 0x81 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x100",
        "lsl w0, w4, #16",
        "cmn w0, w20, lsl #16",
        "add w26, w4, #0x100 (256)",
        "mov x20, x4",
        "bfxil x20, x26, #0, #16",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "add eax, 256": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x81 /0",
      "ExpectedArm64ASM": [
        "adds w26, w4, #0x100 (256)",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "add rax, 256": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x81 /0",
      "ExpectedArm64ASM": [
        "adds x26, x4, #0x100 (256)",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "or eax, 256": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x81 /1",
      "ExpectedArm64ASM": [
        "orr w26, w4, #0x100",
        "tst w26, w26",
        "mov x4, x26"
      ]
    },
    "or rax, 256": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x81 /1",
      "ExpectedArm64ASM": [
        "orr x26, x4, #0x100",
        "tst x26, x26",
        "mov x4, x26"
      ]
    },
    "adc eax, 256": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x81 /2",
      "ExpectedArm64ASM": [
        "mov w20, #0x100",
        "adcs w26, w4, w20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "adc rax, 256": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x81 /2",
      "ExpectedArm64ASM": [
        "mov w20, #0x100",
        "adcs x26, x4, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sbb eax, 256": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP1 0x81 /3",
      "ExpectedArm64ASM": [
        "mov w20, #0x100",
        "mrs x21, nzcv",
        "eor w21, w21, #0x20000000",
        "msr nzcv, x21",
        "sbcs w26, w4, w20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sbb rax, 256": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP1 0x81 /3",
      "ExpectedArm64ASM": [
        "mov w20, #0x100",
        "mrs x21, nzcv",
        "eor w21, w21, #0x20000000",
        "msr nzcv, x21",
        "sbcs x26, x4, x20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "and eax, 256": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP1 0x81 /4",
      "ExpectedArm64ASM": [
        "ands w26, w4, #0x100",
        "mov x4, x26"
      ]
    },
    "and rax, 256": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP1 0x81 /4",
      "ExpectedArm64ASM": [
        "ands x26, x4, #0x100",
        "mov x4, x26"
      ]
    },
    "sub eax, 256": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP1 0x81 /5",
      "ExpectedArm64ASM": [
        "subs w26, w4, #0x100 (256)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sub rax, 256": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP1 0x81 /5",
      "ExpectedArm64ASM": [
        "subs x26, x4, #0x100 (256)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "xor eax, 256": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x81 /6",
      "ExpectedArm64ASM": [
        "eor w26, w4, #0x100",
        "tst w26, w26",
        "mov x4, x26"
      ]
    },
    "xor rax, 256": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x81 /6",
      "ExpectedArm64ASM": [
        "eor x26, x4, #0x100",
        "tst x26, x26",
        "mov x4, x26"
      ]
    },
    "cmp eax, 256": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP1 0x81 /7",
      "ExpectedArm64ASM": [
        "subs w26, w4, #0x100 (256)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4"
      ]
    },
    "cmp rax, 256": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP1 0x81 /7",
      "ExpectedArm64ASM": [
        "subs x26, x4, #0x100 (256)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4"
      ]
    },
    "add ax, -256": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP1 0x81 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0xff00",
        "lsl w0, w4, #16",
        "cmn w0, w20, lsl #16",
        "add w26, w4, w20",
        "mov x20, x4",
        "bfxil x20, x26, #0, #16",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "add eax, -256": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x81 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffff00",
        "adds w26, w4, w20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "add rax, -256": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x81 /0",
      "ExpectedArm64ASM": [
        "subs x26, x4, #0x100 (256)",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "or eax, -256": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x81 /1",
      "ExpectedArm64ASM": [
        "orr w26, w4, #0xffffff00",
        "tst w26, w26",
        "mov x4, x26"
      ]
    },
    "or rax, -256": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x81 /1",
      "ExpectedArm64ASM": [
        "orr x26, x4, #0xffffffffffffff00",
        "tst x26, x26",
        "mov x4, x26"
      ]
    },
    "adc eax, -256": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x81 /2",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffff00",
        "adcs w26, w4, w20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "adc rax, -256": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x81 /2",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffff00",
        "adcs x26, x4, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sbb eax, -256": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP1 0x81 /3",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffff00",
        "mrs x21, nzcv",
        "eor w21, w21, #0x20000000",
        "msr nzcv, x21",
        "sbcs w26, w4, w20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sbb rax, -256": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP1 0x81 /3",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffff00",
        "mrs x21, nzcv",
        "eor w21, w21, #0x20000000",
        "msr nzcv, x21",
        "sbcs x26, x4, x20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "and eax, -256": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP1 0x81 /4",
      "ExpectedArm64ASM": [
        "ands w26, w4, #0xffffff00",
        "mov x4, x26"
      ]
    },
    "and rax, -256": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP1 0x81 /4",
      "ExpectedArm64ASM": [
        "ands x26, x4, #0xffffffffffffff00",
        "mov x4, x26"
      ]
    },
    "sub eax, -256": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP1 0x81 /5",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffff00",
        "subs w26, w4, w20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sub rax, -256": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP1 0x81 /5",
      "ExpectedArm64ASM": [
        "adds x26, x4, #0x100 (256)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "xor eax, -256": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x81 /6",
      "ExpectedArm64ASM": [
        "eor w26, w4, #0xffffff00",
        "tst w26, w26",
        "mov x4, x26"
      ]
    },
    "xor rax, -256": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x81 /6",
      "ExpectedArm64ASM": [
        "eor x26, x4, #0xffffffffffffff00",
        "tst x26, x26",
        "mov x4, x26"
      ]
    },
    "cmp eax, -256": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP1 0x81 /7",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffff00",
        "subs w26, w4, w20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4"
      ]
    },
    "cmp rax, -256": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP1 0x81 /7",
      "ExpectedArm64ASM": [
        "adds x26, x4, #0x100 (256)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4"
      ]
    },
    "add ax, 1": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP1 0x83 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "lsl w0, w4, #16",
        "cmn w0, w20, lsl #16",
        "add w26, w4, #0x1 (1)",
        "mov x20, x4",
        "bfxil x20, x26, #0, #16",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "add eax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x83 /0",
      "ExpectedArm64ASM": [
        "adds w26, w4, #0x1 (1)",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "add rax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x83 /0",
      "ExpectedArm64ASM": [
        "adds x26, x4, #0x1 (1)",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "or eax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x83 /1",
      "ExpectedArm64ASM": [
        "orr w26, w4, #0x1",
        "tst w26, w26",
        "mov x4, x26"
      ]
    },
    "or rax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x83 /1",
      "ExpectedArm64ASM": [
        "orr x26, x4, #0x1",
        "tst x26, x26",
        "mov x4, x26"
      ]
    },
    "adc eax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x83 /2",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "adcs w26, w4, w20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "adc rax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x83 /2",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "adcs x26, x4, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sbb eax, 1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP1 0x83 /3",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mrs x21, nzcv",
        "eor w21, w21, #0x20000000",
        "msr nzcv, x21",
        "sbcs w26, w4, w20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sbb rax, 1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP1 0x83 /3",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "mrs x21, nzcv",
        "eor w21, w21, #0x20000000",
        "msr nzcv, x21",
        "sbcs x26, x4, x20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "and eax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP1 0x83 /4",
      "ExpectedArm64ASM": [
        "ands w26, w4, #0x1",
        "mov x4, x26"
      ]
    },
    "and rax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP1 0x83 /4",
      "ExpectedArm64ASM": [
        "ands x26, x4, #0x1",
        "mov x4, x26"
      ]
    },
    "sub eax, 1": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP1 0x83 /5",
      "ExpectedArm64ASM": [
        "subs w26, w4, #0x1 (1)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sub rax, 1": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP1 0x83 /5",
      "ExpectedArm64ASM": [
        "subs x26, x4, #0x1 (1)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "xor eax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x83 /6",
      "ExpectedArm64ASM": [
        "eor w26, w4, #0x1",
        "tst w26, w26",
        "mov x4, x26"
      ]
    },
    "xor rax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x83 /6",
      "ExpectedArm64ASM": [
        "eor x26, x4, #0x1",
        "tst x26, x26",
        "mov x4, x26"
      ]
    },
    "cmp eax, 1": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP1 0x83 /7",
      "ExpectedArm64ASM": [
        "subs w26, w4, #0x1 (1)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4"
      ]
    },
    "cmp rax, 1": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP1 0x83 /7",
      "ExpectedArm64ASM": [
        "subs x26, x4, #0x1 (1)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x4"
      ]
    },
    "add ax, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP1 0x83 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0xffff",
        "mvn w27, w4",
        "lsl w0, w4, #16",
        "cmn w0, w20, lsl #16",
        "add w26, w4, w20",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "add eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x83 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "adds w26, w4, w20",
        "mov x4, x26"
      ]
    },
    "add rax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x83 /0",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "subs x26, x4, #0x1 (1)",
        "mov x4, x26"
      ]
    },
    "or eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x83 /-1",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "orr w26, w4, w20",
        "tst w26, w26",
        "mov x4, x26"
      ]
    },
    "or rax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x83 /-1",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "orr x26, x4, x20",
        "tst x26, x26",
        "mov x4, x26"
      ]
    },
    "adc eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x83 /2",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "adcs w26, w4, w20",
        "mov x4, x26"
      ]
    },
    "adc rax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x83 /2",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "mvn w27, w4",
        "adcs x26, x4, x20",
        "mov x4, x26"
      ]
    },
    "sbb eax, -1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP1 0x83 /3",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "mrs x21, nzcv",
        "eor w21, w21, #0x20000000",
        "msr nzcv, x21",
        "sbcs w26, w4, w20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "sbb rax, -1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP1 0x83 /3",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "mvn w27, w4",
        "mrs x21, nzcv",
        "eor w21, w21, #0x20000000",
        "msr nzcv, x21",
        "sbcs x26, x4, x20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "and eax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x83 /4",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "ands w26, w4, w20",
        "mov x4, x26"
      ]
    },
    "and rax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "GROUP1 0x83 /4",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "ands x26, x4, x20",
        "mov x4, x26"
      ]
    },
    "sub eax, -1": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP1 0x83 /5",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "subs w26, w4, w20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "sub rax, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP1 0x83 /5",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "adds x26, x4, #0x1 (1)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "xor eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x83 /6",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "eor w26, w4, w20",
        "tst w26, w26",
        "mov x4, x26"
      ]
    },
    "xor rax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "GROUP1 0x83 /6",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "eor x26, x4, x20",
        "tst x26, x26",
        "mov x4, x26"
      ]
    },
    "cmp eax, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP1 0x83 /7",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "subs w26, w4, w20",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20"
      ]
    },
    "cmp rax, -1": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP1 0x83 /7",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "adds x26, x4, #0x1 (1)",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20"
      ]
    },
    "rol al, 2": {
      "ExpectedInstructionCount": 9,
      "Comment": "GROUP2 0xC0 /0",
      "ExpectedArm64ASM": [
        "mov w20, w4",
        "bfi w20, w4, #8, #8",
        "bfi w20, w20, #16, #16",
        "ror w20, w20, #30",
        "bfxil x4, x20, #0, #8",
        "ubfx x20, x20, #0, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "ror al, 2": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xC0 /1",
      "ExpectedArm64ASM": [
        "mov w20, w4",
        "bfi w20, w4, #8, #8",
        "ror w20, w20, #2",
        "bfxil x4, x20, #0, #8",
        "ubfx x20, x20, #7, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "rcl al, 2": {
      "ExpectedInstructionCount": 21,
      "Comment": "GROUP2 0xC0 /2",
      "ExpectedArm64ASM": [
        "uxtb w20, w4",
        "mov w21, #0x0",
        "cset w22, hs",
        "bfi x21, x20, #55, #8",
        "bfi x21, x22, #63, #1",
        "bfi x21, x20, #46, #8",
        "bfi x21, x22, #54, #1",
        "bfi x21, x20, #37, #8",
        "bfi x21, x22, #45, #1",
        "bfi x21, x20, #28, #8",
        "bfi x21, x22, #36, #1",
        "bfi x21, x20, #19, #8",
        "bfi x21, x22, #27, #1",
        "bfxil x21, x20, #0, #8",
        "ror x20, x21, #62",
        "bfxil x4, x20, #0, #8",
        "ror x20, x21, #61",
        "ubfx x20, x20, #0, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "rcr al, 2": {
      "ExpectedInstructionCount": 12,
      "Comment": "GROUP2 0xC0 /3",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "uxtb w21, w4",
        "bfi x21, x20, #8, #1",
        "bfi x21, x21, #9, #9",
        "bfi x21, x21, #18, #18",
        "bfi x21, x21, #36, #9",
        "lsr x20, x21, #2",
        "bfxil x4, x20, #0, #8",
        "ubfx x20, x21, #1, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "shl al, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC0 /4",
      "ExpectedArm64ASM": [
        "lsl w26, w4, #2",
        "cmn wzr, w26, lsl #24",
        "ubfx x20, x4, #6, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "shr al, 2": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xC0 /5",
      "ExpectedArm64ASM": [
        "uxtb w20, w4",
        "lsr w26, w20, #2",
        "cmn wzr, w26, lsl #24",
        "ubfx x20, x20, #1, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "sar al, 2": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xC0 /7",
      "ExpectedArm64ASM": [
        "sxtb x20, w4",
        "asr w26, w20, #2",
        "cmn wzr, w26, lsl #24",
        "ubfx x20, x20, #1, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "rol ax, 2": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xC1 /0",
      "ExpectedArm64ASM": [
        "mov w20, w4",
        "bfi w20, w4, #16, #16",
        "ror w20, w20, #30",
        "bfxil x4, x20, #0, #16",
        "ubfx x20, x20, #0, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "rol eax, 2": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP2 0xC1 /0",
      "ExpectedArm64ASM": [
        "ror w4, w4, #30",
        "ubfx x20, x4, #0, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "rol rax, 2": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP2 0xC1 /0",
      "ExpectedArm64ASM": [
        "ror x4, x4, #62",
        "ubfx x20, x4, #0, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "ror ax, 2": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xC1 /1",
      "ExpectedArm64ASM": [
        "mov w20, w4",
        "bfi w20, w4, #16, #16",
        "ror w20, w20, #2",
        "bfxil x4, x20, #0, #16",
        "ubfx x20, x20, #15, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "ror eax, 2": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP2 0xC1 /1",
      "ExpectedArm64ASM": [
        "ror w4, w4, #2",
        "ubfx x20, x4, #31, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "ror rax, 2": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP2 0xC1 /1",
      "ExpectedArm64ASM": [
        "ror x4, x4, #2",
        "lsr x20, x4, #63",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "rcl ax, 2": {
      "ExpectedInstructionCount": 17,
      "Comment": "GROUP2 0xC1 /2",
      "ExpectedArm64ASM": [
        "uxth w20, w4",
        "mov w21, #0x0",
        "cset w22, hs",
        "bfi x21, x20, #47, #16",
        "bfi x21, x22, #63, #1",
        "bfi x21, x20, #30, #16",
        "bfi x21, x22, #46, #1",
        "bfi x21, x20, #13, #16",
        "bfi x21, x22, #29, #1",
        "bfxil x21, x20, #0, #16",
        "ror x20, x21, #62",
        "bfxil x4, x20, #0, #16",
        "ror x20, x21, #61",
        "ubfx x20, x20, #0, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "rcl eax, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC1 /2",
      "ExpectedArm64ASM": [
        "lsl w20, w4, #2",
        "cset w21, hs",
        "orr w20, w20, w4, lsr #31",
        "ubfx x22, x4, #30, #1",
        "lsl x22, x22, #29",
        "orr w4, w20, w21, lsl #1",
        "msr nzcv, x22"
      ]
    },
    "rcl rax, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC1 /2",
      "ExpectedArm64ASM": [
        "lsl x20, x4, #2",
        "cset w21, hs",
        "orr x20, x20, x4, lsr #63",
        "ubfx x22, x4, #62, #1",
        "lsl x22, x22, #29",
        "orr x4, x20, x21, lsl #1",
        "msr nzcv, x22"
      ]
    },
    "rcr ax, 2": {
      "ExpectedInstructionCount": 11,
      "Comment": "GROUP2 0xC1 /3",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "uxth w21, w4",
        "bfi x21, x20, #16, #1",
        "bfi x21, x21, #17, #17",
        "bfi x21, x21, #34, #17",
        "lsr x20, x21, #2",
        "bfxil x4, x20, #0, #16",
        "ubfx x20, x21, #1, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21"
      ]
    },
    "rcr eax, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC1 /3",
      "ExpectedArm64ASM": [
        "lsr w20, w4, #2",
        "cset w21, hs",
        "orr w20, w20, w4, lsl #31",
        "ubfx x22, x4, #1, #1",
        "lsl x22, x22, #29",
        "orr w4, w20, w21, lsl #30",
        "msr nzcv, x22"
      ]
    },
    "rcr rax, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC1 /3",
      "ExpectedArm64ASM": [
        "lsr x20, x4, #2",
        "cset w21, hs",
        "orr x20, x20, x4, lsl #63",
        "ubfx x22, x4, #1, #1",
        "lsl x22, x22, #29",
        "orr x4, x20, x21, lsl #62",
        "msr nzcv, x22"
      ]
    },
    "shl ax, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC1 /4",
      "ExpectedArm64ASM": [
        "lsl w26, w4, #2",
        "cmn wzr, w26, lsl #16",
        "ubfx x20, x4, #14, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "shl eax, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC1 /4",
      "ExpectedArm64ASM": [
        "lsl w26, w4, #2",
        "tst w26, w26",
        "ubfx x20, x4, #30, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "shl rax, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC1 /4",
      "ExpectedArm64ASM": [
        "lsl x26, x4, #2",
        "tst x26, x26",
        "ubfx x20, x4, #62, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "shr ax, 2": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xC1 /5",
      "ExpectedArm64ASM": [
        "uxth w20, w4",
        "lsr w26, w20, #2",
        "cmn wzr, w26, lsl #16",
        "ubfx x20, x20, #1, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "shr eax, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC1 /5",
      "ExpectedArm64ASM": [
        "lsr w26, w4, #2",
        "tst w26, w26",
        "ubfx x20, x4, #1, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "shr rax, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC1 /5",
      "ExpectedArm64ASM": [
        "lsr x26, x4, #2",
        "tst x26, x26",
        "ubfx x20, x4, #1, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "sar ax, 2": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xC1 /7",
      "ExpectedArm64ASM": [
        "sxth x20, w4",
        "asr w26, w20, #2",
        "cmn wzr, w26, lsl #16",
        "ubfx x20, x20, #1, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "sar eax, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC1 /7",
      "ExpectedArm64ASM": [
        "asr w26, w4, #2",
        "tst w26, w26",
        "ubfx x20, x4, #1, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "sar rax, 2": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xC1 /7",
      "ExpectedArm64ASM": [
        "asr x26, x4, #2",
        "tst x26, x26",
        "ubfx x20, x4, #1, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "rol al, 1": {
      "ExpectedInstructionCount": 12,
      "Comment": "GROUP2 0xd0 /0",
      "ExpectedArm64ASM": [
        "mov w20, w4",
        "bfi w20, w4, #8, #8",
        "bfi w20, w20, #16, #16",
        "ror w20, w20, #31",
        "bfxil x4, x20, #0, #8",
        "ubfx x21, x20, #0, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "eor w20, w20, w20, lsr #7",
        "ubfx x20, x20, #0, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "ror al, 1": {
      "ExpectedInstructionCount": 11,
      "Comment": "GROUP2 0xd0 /1",
      "ExpectedArm64ASM": [
        "mov w20, w4",
        "bfi w20, w4, #8, #8",
        "ror w20, w20, #1",
        "bfxil x4, x20, #0, #8",
        "ubfx x21, x20, #7, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "eor w20, w20, w20, lsr #1",
        "ubfx x20, x20, #6, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "rcl al, 1": {
      "ExpectedInstructionCount": 11,
      "Comment": "GROUP2 0xd0 /2",
      "ExpectedArm64ASM": [
        "uxtb w20, w4",
        "cset w21, hs",
        "orr w21, w21, w20, lsl #1",
        "ubfx x22, x20, #7, #1",
        "mrs x23, nzcv",
        "bfi w23, w22, #29, #1",
        "eor w20, w21, w20",
        "ubfx x20, x20, #7, #1",
        "bfi w23, w20, #28, #1",
        "bfxil x4, x21, #0, #8",
        "msr nzcv, x23"
      ]
    },
    "rcr al, 1": {
      "ExpectedInstructionCount": 12,
      "Comment": "GROUP2 0xd0 /3",
      "ExpectedArm64ASM": [
        "uxtb w20, w4",
        "cset w21, hs",
        "ubfx x22, x20, #0, #1",
        "mrs x23, nzcv",
        "bfi w23, w22, #29, #1",
        "ubfx w20, w20, #1, #7",
        "bfi w20, w21, #7, #1",
        "bfxil x4, x20, #0, #8",
        "eor w20, w20, w20, lsr #1",
        "ubfx x20, x20, #6, #1",
        "bfi w23, w20, #28, #1",
        "msr nzcv, x23"
      ]
    },
    "shl al, 1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xd0 /4",
      "ExpectedArm64ASM": [
        "lsl w26, w4, #1",
        "cmn wzr, w26, lsl #24",
        "ubfx x20, x4, #7, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "eor w21, w26, w4",
        "ubfx x21, x21, #7, #1",
        "orr w20, w20, w21, lsl #28",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "shr al, 1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xd0 /5",
      "ExpectedArm64ASM": [
        "uxtb w20, w4",
        "lsr w26, w20, #1",
        "cmn wzr, w26, lsl #24",
        "ubfx x21, x20, #0, #1",
        "mrs x22, nzcv",
        "orr w21, w22, w21, lsl #29",
        "ubfx x20, x20, #7, #1",
        "orr w20, w21, w20, lsl #28",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "sar al, 1": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xd0 /7",
      "ExpectedArm64ASM": [
        "sxtb x20, w4",
        "asr w26, w20, #1",
        "cmn wzr, w26, lsl #24",
        "ubfx x20, x20, #0, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "rol ax, 1": {
      "ExpectedInstructionCount": 11,
      "Comment": "GROUP2 0xd1 /0",
      "ExpectedArm64ASM": [
        "mov w20, w4",
        "bfi w20, w4, #16, #16",
        "ror w20, w20, #31",
        "bfxil x4, x20, #0, #16",
        "ubfx x21, x20, #0, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "eor w20, w20, w20, lsr #15",
        "ubfx x20, x20, #0, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "rol eax, 1": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xd1 /0",
      "ExpectedArm64ASM": [
        "ror w4, w4, #31",
        "ubfx x20, x4, #0, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "eor w20, w4, w4, lsr #31",
        "ubfx x20, x20, #0, #1",
        "bfi w21, w20, #28, #1",
        "msr nzcv, x21"
      ]
    },
    "rol rax, 1": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xd1 /0",
      "ExpectedArm64ASM": [
        "ror x4, x4, #63",
        "ubfx x20, x4, #0, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "eor x20, x4, x4, lsr #63",
        "ubfx x20, x20, #0, #1",
        "bfi w21, w20, #28, #1",
        "msr nzcv, x21"
      ]
    },
    "ror ax, 1": {
      "ExpectedInstructionCount": 11,
      "Comment": "GROUP2 0xd1 /1",
      "ExpectedArm64ASM": [
        "mov w20, w4",
        "bfi w20, w4, #16, #16",
        "ror w20, w20, #1",
        "bfxil x4, x20, #0, #16",
        "ubfx x21, x20, #15, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "eor w20, w20, w20, lsr #1",
        "ubfx x20, x20, #14, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "ror eax, 1": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xd1 /1",
      "ExpectedArm64ASM": [
        "ror w4, w4, #1",
        "ubfx x20, x4, #31, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "eor w20, w4, w4, lsr #1",
        "ubfx x20, x20, #30, #1",
        "bfi w21, w20, #28, #1",
        "msr nzcv, x21"
      ]
    },
    "ror rax, 1": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xd1 /1",
      "ExpectedArm64ASM": [
        "ror x4, x4, #1",
        "lsr x20, x4, #63",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "eor x20, x4, x4, lsr #1",
        "ubfx x20, x20, #62, #1",
        "bfi w21, w20, #28, #1",
        "msr nzcv, x21"
      ]
    },
    "rcl ax, 1": {
      "ExpectedInstructionCount": 11,
      "Comment": "GROUP2 0xd1 /2",
      "ExpectedArm64ASM": [
        "uxth w20, w4",
        "cset w21, hs",
        "orr w21, w21, w20, lsl #1",
        "ubfx x22, x20, #15, #1",
        "mrs x23, nzcv",
        "bfi w23, w22, #29, #1",
        "eor w20, w21, w20",
        "ubfx x20, x20, #15, #1",
        "bfi w23, w20, #28, #1",
        "bfxil x4, x21, #0, #16",
        "msr nzcv, x23"
      ]
    },
    "rcl eax, 1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xd1 /2",
      "ExpectedArm64ASM": [
        "mov w20, w4",
        "cset w21, hs",
        "orr w4, w21, w20, lsl #1",
        "ubfx x21, x20, #31, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "eor w20, w4, w20",
        "ubfx x20, x20, #31, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "rcl rax, 1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xd1 /2",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "orr x20, x20, x4, lsl #1",
        "lsr x21, x4, #63",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "eor x21, x20, x4",
        "lsr x21, x21, #63",
        "bfi w22, w21, #28, #1",
        "msr nzcv, x22",
        "mov x4, x20"
      ]
    },
    "rcr ax, 1": {
      "ExpectedInstructionCount": 11,
      "Comment": "GROUP2 0xd1 /3",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "ubfx x21, x4, #0, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "ubfx w21, w4, #1, #15",
        "orr w20, w21, w20, lsl #15",
        "bfxil x4, x20, #0, #16",
        "eor x20, x20, x20, lsr #1",
        "ubfx x20, x20, #14, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "rcr eax, 1": {
      "ExpectedInstructionCount": 9,
      "Comment": "GROUP2 0xd1 /3",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "ubfx x21, x4, #0, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "extr w4, w20, w4, #1",
        "eor x20, x4, x4, lsr #1",
        "ubfx x20, x20, #30, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "rcr rax, 1": {
      "ExpectedInstructionCount": 9,
      "Comment": "GROUP2 0xd1 /3",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "ubfx x21, x4, #0, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "extr x4, x20, x4, #1",
        "eor x20, x4, x4, lsr #1",
        "ubfx x20, x20, #62, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "shl ax, 1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xd1 /4",
      "ExpectedArm64ASM": [
        "lsl w26, w4, #1",
        "cmn wzr, w26, lsl #16",
        "ubfx x20, x4, #15, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "eor w21, w26, w4",
        "ubfx x21, x21, #15, #1",
        "orr w20, w20, w21, lsl #28",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "shl eax, 1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xd1 /4",
      "ExpectedArm64ASM": [
        "lsl w26, w4, #1",
        "tst w26, w26",
        "ubfx x20, x4, #31, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "eor w21, w26, w4",
        "ubfx x21, x21, #31, #1",
        "orr w20, w20, w21, lsl #28",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "shl rax, 1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xd1 /4",
      "ExpectedArm64ASM": [
        "lsl x26, x4, #1",
        "tst x26, x26",
        "lsr x20, x4, #63",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "eor x21, x26, x4",
        "lsr x21, x21, #63",
        "orr w20, w20, w21, lsl #28",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "shr ax, 1": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xd1 /5",
      "ExpectedArm64ASM": [
        "uxth w20, w4",
        "lsr w26, w20, #1",
        "cmn wzr, w26, lsl #16",
        "ubfx x21, x20, #0, #1",
        "mrs x22, nzcv",
        "orr w21, w22, w21, lsl #29",
        "ubfx x20, x20, #15, #1",
        "orr w20, w21, w20, lsl #28",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "shr eax, 1": {
      "ExpectedInstructionCount": 9,
      "Comment": "GROUP2 0xd1 /5",
      "ExpectedArm64ASM": [
        "lsr w26, w4, #1",
        "tst w26, w26",
        "ubfx x20, x4, #0, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "ubfx x21, x4, #31, #1",
        "orr w20, w20, w21, lsl #28",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "shr rax, 1": {
      "ExpectedInstructionCount": 9,
      "Comment": "GROUP2 0xd1 /5",
      "ExpectedArm64ASM": [
        "lsr x26, x4, #1",
        "tst x26, x26",
        "ubfx x20, x4, #0, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "lsr x21, x4, #63",
        "orr w20, w20, w21, lsl #28",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "sar ax, 1": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xd1 /7",
      "ExpectedArm64ASM": [
        "sxth x20, w4",
        "asr w26, w20, #1",
        "cmn wzr, w26, lsl #16",
        "ubfx x20, x20, #0, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "sar eax, 1": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xd1 /7",
      "ExpectedArm64ASM": [
        "asr w26, w4, #1",
        "tst w26, w26",
        "ubfx x20, x4, #0, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "sar rax, 1": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xd1 /7",
      "ExpectedArm64ASM": [
        "asr x26, x4, #1",
        "tst x26, x26",
        "ubfx x20, x4, #0, #1",
        "mrs x21, nzcv",
        "orr w20, w21, w20, lsl #29",
        "msr nzcv, x20",
        "mov x4, x26"
      ]
    },
    "rol al, cl": {
      "ExpectedInstructionCount": 15,
      "Comment": "GROUP2 0xd2 /0",
      "ExpectedArm64ASM": [
        "and x20, x5, #0x1f",
        "cbz x20, #+0x38",
        "mov w20, w4",
        "bfi w20, w4, #8, #8",
        "bfi w20, w20, #16, #16",
        "neg w21, w5",
        "ror w20, w20, w21",
        "bfxil x4, x20, #0, #8",
        "ubfx x21, x20, #0, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "eor w20, w20, w20, lsr #7",
        "ubfx x20, x20, #0, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "ror al, cl": {
      "ExpectedInstructionCount": 14,
      "Comment": "GROUP2 0xd2 /1",
      "ExpectedArm64ASM": [
        "and x20, x5, #0x1f",
        "cbz x20, #+0x34",
        "mov w20, w4",
        "bfi w20, w4, #8, #8",
        "bfi w20, w20, #16, #16",
        "ror w20, w20, w5",
        "bfxil x4, x20, #0, #8",
        "ubfx x21, x20, #7, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "eor w20, w20, w20, lsr #1",
        "ubfx x20, x20, #6, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "rcl al, cl": {
      "ExpectedInstructionCount": 30,
      "Comment": "GROUP2 0xd2 /2",
      "ExpectedArm64ASM": [
        "and w20, w5, #0x1f",
        "cbz x20, #+0x74",
        "and w20, w5, #0x1f",
        "uxtb w21, w4",
        "mov w22, #0x0",
        "cset w23, hs",
        "bfi x22, x21, #55, #8",
        "bfi x22, x23, #63, #1",
        "bfi x22, x21, #46, #8",
        "bfi x22, x23, #54, #1",
        "bfi x22, x21, #37, #8",
        "bfi x22, x23, #45, #1",
        "bfi x22, x21, #28, #8",
        "bfi x22, x23, #36, #1",
        "bfi x22, x21, #19, #8",
        "bfi x22, x23, #27, #1",
        "bfxil x22, x21, #0, #8",
        "neg w21, w20",
        "ror x21, x22, x21",
        "bfxil x4, x21, #0, #8",
        "mov w23, #0x3f",
        "sub x20, x23, x20",
        "ror x20, x22, x20",
        "ubfx x22, x20, #0, #1",
        "mrs x23, nzcv",
        "bfi w23, w22, #29, #1",
        "eor x20, x20, x21, lsr #7",
        "ubfx x20, x20, #0, #1",
        "bfi w23, w20, #28, #1",
        "msr nzcv, x23"
      ]
    },
    "rcr al, cl": {
      "ExpectedInstructionCount": 20,
      "Comment": "GROUP2 0xd2 /3",
      "ExpectedArm64ASM": [
        "and w20, w5, #0x1f",
        "cbz x20, #+0x4c",
        "and w20, w5, #0x1f",
        "cset w21, hs",
        "uxtb w22, w4",
        "bfi x22, x21, #8, #1",
        "bfi x22, x22, #9, #9",
        "bfi x22, x22, #18, #18",
        "bfi x22, x22, #36, #9",
        "lsr x21, x22, x20",
        "bfxil x4, x21, #0, #8",
        "sub w20, w20, #0x1 (1)",
        "lsr w20, w22, w20",
        "ubfx x20, x20, #0, #1",
        "mrs x22, nzcv",
        "bfi w22, w20, #29, #1",
        "eor w20, w21, w21, lsr #1",
        "ubfx x20, x20, #6, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "shl al, cl": {
      "ExpectedInstructionCount": 13,
      "Comment": "GROUP2 0xd2 /4",
      "ExpectedArm64ASM": [
        "lsl w20, w4, w5",
        "and w0, w5, #0x1f",
        "cbz w0, #+0x28",
        "cmn wzr, w20, lsl #24",
        "mov x26, x20",
        "eor w2, w4, w20",
        "mrs x1, nzcv",
        "lsr x0, x20, #8",
        "bfi w1, w0, #29, #1",
        "lsr w2, w2, #7",
        "bfi w1, w2, #28, #1",
        "msr nzcv, x1",
        "bfxil x4, x20, #0, #8"
      ]
    },
    "shr al, cl": {
      "ExpectedInstructionCount": 15,
      "Comment": "GROUP2 0xd2 /5",
      "ExpectedArm64ASM": [
        "uxtb w20, w4",
        "lsr w21, w20, w5",
        "and w0, w5, #0x1f",
        "cbz w0, #+0x2c",
        "cmn wzr, w21, lsl #24",
        "mov x26, x21",
        "sub x0, x5, #0x1 (1)",
        "lsr w0, w20, w0",
        "eor w2, w20, w21",
        "mrs x1, nzcv",
        "bfi w1, w0, #29, #1",
        "lsr w2, w2, #7",
        "bfi w1, w2, #28, #1",
        "msr nzcv, x1",
        "bfxil x4, x21, #0, #8"
      ]
    },
    "sar al, cl": {
      "ExpectedInstructionCount": 12,
      "Comment": "GROUP2 0xd2 /7",
      "ExpectedArm64ASM": [
        "sxtb x20, w4",
        "asr w21, w20, w5",
        "and w0, w5, #0x1f",
        "cbz w0, #+0x20",
        "cmn wzr, w21, lsl #24",
        "mov x26, x21",
        "sub x0, x5, #0x1 (1)",
        "lsr w0, w20, w0",
        "mrs x1, nzcv",
        "bfi w1, w0, #29, #1",
        "msr nzcv, x1",
        "bfxil x4, x21, #0, #8"
      ]
    },
    "rol ax, cl": {
      "ExpectedInstructionCount": 14,
      "Comment": "GROUP2 0xd3 /0",
      "ExpectedArm64ASM": [
        "and x20, x5, #0x1f",
        "cbz x20, #+0x34",
        "mov w20, w4",
        "bfi w20, w4, #16, #16",
        "neg w21, w5",
        "ror w20, w20, w21",
        "bfxil x4, x20, #0, #16",
        "ubfx x21, x20, #0, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "eor w20, w20, w20, lsr #15",
        "ubfx x20, x20, #0, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "rol eax, cl": {
      "ExpectedInstructionCount": 13,
      "Comment": "GROUP2 0xd3 /0",
      "ExpectedArm64ASM": [
        "and x20, x5, #0x1f",
        "cbz x20, #+0x2c",
        "neg w20, w5",
        "ror w4, w4, w20",
        "ubfx x20, x4, #0, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "eor w20, w4, w4, lsr #31",
        "ubfx x20, x20, #0, #1",
        "bfi w21, w20, #28, #1",
        "msr nzcv, x21",
        "b #+0x8",
        "mov w4, w4"
      ]
    },
    "rol rax, cl": {
      "ExpectedInstructionCount": 11,
      "Comment": "GROUP2 0xd3 /0",
      "ExpectedArm64ASM": [
        "and x20, x5, #0x3f",
        "cbz x20, #+0x28",
        "neg x20, x5",
        "ror x4, x4, x20",
        "ubfx x20, x4, #0, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "eor x20, x4, x4, lsr #63",
        "ubfx x20, x20, #0, #1",
        "bfi w21, w20, #28, #1",
        "msr nzcv, x21"
      ]
    },
    "ror ax, cl": {
      "ExpectedInstructionCount": 13,
      "Comment": "GROUP2 0xd3 /1",
      "ExpectedArm64ASM": [
        "and x20, x5, #0x1f",
        "cbz x20, #+0x30",
        "mov w20, w4",
        "bfi w20, w4, #16, #16",
        "ror w20, w20, w5",
        "bfxil x4, x20, #0, #16",
        "ubfx x21, x20, #15, #1",
        "mrs x22, nzcv",
        "bfi w22, w21, #29, #1",
        "eor w20, w20, w20, lsr #1",
        "ubfx x20, x20, #14, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "ror eax, cl": {
      "ExpectedInstructionCount": 12,
      "Comment": "GROUP2 0xd3 /1",
      "ExpectedArm64ASM": [
        "and x20, x5, #0x1f",
        "cbz x20, #+0x28",
        "ror w4, w4, w5",
        "ubfx x20, x4, #31, #1",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "eor w20, w4, w4, lsr #1",
        "ubfx x20, x20, #30, #1",
        "bfi w21, w20, #28, #1",
        "msr nzcv, x21",
        "b #+0x8",
        "mov w4, w4"
      ]
    },
    "ror rax, cl": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xd3 /1",
      "ExpectedArm64ASM": [
        "and x20, x5, #0x3f",
        "cbz x20, #+0x24",
        "ror x4, x4, x5",
        "lsr x20, x4, #63",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "eor x20, x4, x4, lsr #1",
        "ubfx x20, x20, #62, #1",
        "bfi w21, w20, #28, #1",
        "msr nzcv, x21"
      ]
    },
    "rcl ax, cl": {
      "ExpectedInstructionCount": 26,
      "Comment": "GROUP2 0xd3 /2",
      "ExpectedArm64ASM": [
        "and w20, w5, #0x1f",
        "cbz x20, #+0x64",
        "and w20, w5, #0x1f",
        "uxth w21, w4",
        "mov w22, #0x0",
        "cset w23, hs",
        "bfi x22, x21, #47, #16",
        "bfi x22, x23, #63, #1",
        "bfi x22, x21, #30, #16",
        "bfi x22, x23, #46, #1",
        "bfi x22, x21, #13, #16",
        "bfi x22, x23, #29, #1",
        "bfxil x22, x21, #0, #16",
        "neg w21, w20",
        "ror x21, x22, x21",
        "bfxil x4, x21, #0, #16",
        "mov w23, #0x3f",
        "sub x20, x23, x20",
        "ror x20, x22, x20",
        "ubfx x22, x20, #0, #1",
        "mrs x23, nzcv",
        "bfi w23, w22, #29, #1",
        "eor x20, x20, x21, lsr #15",
        "ubfx x20, x20, #0, #1",
        "bfi w23, w20, #28, #1",
        "msr nzcv, x23"
      ]
    },
    "rcl eax, cl": {
      "ExpectedInstructionCount": 20,
      "Comment": "GROUP2 0xd3 /2",
      "ExpectedArm64ASM": [
        "and w20, w5, #0x1f",
        "cbz x20, #+0x48",
        "lsl w20, w4, w5",
        "cset w21, hs",
        "neg w22, w5",
        "lsr w23, w4, w22",
        "orr w20, w20, w23, lsr #1",
        "lsr w22, w4, w22",
        "ubfx x23, x22, #0, #1",
        "mrs x24, nzcv",
        "bfi w24, w23, #29, #1",
        "sub w23, w5, #0x1 (1)",
        "lsl w21, w21, w23",
        "orr w4, w20, w21",
        "eor w20, w4, w22, lsl #31",
        "ubfx x20, x20, #31, #1",
        "bfi w24, w20, #28, #1",
        "msr nzcv, x24",
        "b #+0x8",
        "mov w4, w4"
      ]
    },
    "rcl rax, cl": {
      "ExpectedInstructionCount": 18,
      "Comment": "GROUP2 0xd3 /2",
      "ExpectedArm64ASM": [
        "and x20, x5, #0x3f",
        "cbz x20, #+0x44",
        "lsl x20, x4, x5",
        "cset w21, hs",
        "neg x22, x5",
        "lsr x23, x4, x22",
        "orr x20, x20, x23, lsr #1",
        "lsr x22, x4, x22",
        "ubfx x23, x22, #0, #1",
        "mrs x24, nzcv",
        "bfi w24, w23, #29, #1",
        "sub x23, x5, #0x1 (1)",
        "lsl x21, x21, x23",
        "orr x4, x20, x21",
        "eor x20, x4, x22, lsl #63",
        "lsr x20, x20, #63",
        "bfi w24, w20, #28, #1",
        "msr nzcv, x24"
      ]
    },
    "rcr ax, cl": {
      "ExpectedInstructionCount": 19,
      "Comment": "GROUP2 0xd3 /3",
      "ExpectedArm64ASM": [
        "and w20, w5, #0x1f",
        "cbz x20, #+0x48",
        "and w20, w5, #0x1f",
        "cset w21, hs",
        "uxth w22, w4",
        "bfi x22, x21, #16, #1",
        "bfi x22, x22, #17, #17",
        "bfi x22, x22, #34, #17",
        "lsr x21, x22, x20",
        "bfxil x4, x21, #0, #16",
        "sub w20, w20, #0x1 (1)",
        "lsr w20, w22, w20",
        "ubfx x20, x20, #0, #1",
        "mrs x22, nzcv",
        "bfi w22, w20, #29, #1",
        "eor w20, w21, w21, lsr #1",
        "ubfx x20, x20, #14, #1",
        "bfi w22, w20, #28, #1",
        "msr nzcv, x22"
      ]
    },
    "rcr eax, cl": {
      "ExpectedInstructionCount": 20,
      "Comment": "GROUP2 0xd3 /3",
      "ExpectedArm64ASM": [
        "and w20, w5, #0x1f",
        "cbz x20, #+0x48",
        "lsr w20, w4, w5",
        "cset w21, hs",
        "neg w22, w5",
        "lsl w23, w4, w22",
        "orr w20, w20, w23, lsl #1",
        "sub w23, w5, #0x1 (1)",
        "lsr w23, w4, w23",
        "ubfx x23, x23, #0, #1",
        "mrs x24, nzcv",
        "bfi w24, w23, #29, #1",
        "lsl w21, w21, w22",
        "orr w4, w20, w21",
        "eor w20, w4, w4, lsr #1",
        "ubfx x20, x20, #30, #1",
        "bfi w24, w20, #28, #1",
        "msr nzcv, x24",
        "b #+0x8",
        "mov w4, w4"
      ]
    },
    "rcr rax, cl": {
      "ExpectedInstructionCount": 18,
      "Comment": "GROUP2 0xd3 /3",
      "ExpectedArm64ASM": [
        "and x20, x5, #0x3f",
        "cbz x20, #+0x44",
        "lsr x20, x4, x5",
        "cset w21, hs",
        "neg x22, x5",
        "lsl x23, x4, x22",
        "orr x20, x20, x23, lsl #1",
        "sub x23, x5, #0x1 (1)",
        "lsr x23, x4, x23",
        "ubfx x23, x23, #0, #1",
        "mrs x24, nzcv",
        "bfi w24, w23, #29, #1",
        "lsl x21, x21, x22",
        "orr x4, x20, x21",
        "eor x20, x4, x4, lsr #1",
        "ubfx x20, x20, #62, #1",
        "bfi w24, w20, #28, #1",
        "msr nzcv, x24"
      ]
    },
    "shl ax, cl": {
      "ExpectedInstructionCount": 13,
      "Comment": "GROUP2 0xd3 /4",
      "ExpectedArm64ASM": [
        "lsl w20, w4, w5",
        "and w0, w5, #0x1f",
        "cbz w0, #+0x28",
        "cmn wzr, w20, lsl #16",
        "mov x26, x20",
        "eor w2, w4, w20",
        "mrs x1, nzcv",
        "lsr x0, x20, #16",
        "bfi w1, w0, #29, #1",
        "lsr w2, w2, #15",
        "bfi w1, w2, #28, #1",
        "msr nzcv, x1",
        "bfxil x4, x20, #0, #16"
      ]
    },
    "shl eax, cl": {
      "ExpectedInstructionCount": 13,
      "Comment": "GROUP2 0xd3 /4",
      "ExpectedArm64ASM": [
        "lsl w20, w4, w5",
        "and w0, w5, #0x1f",
        "cbz w0, #+0x28",
        "ands w26, w20, w20",
        "neg w0, w5",
        "lsr w0, w4, w0",
        "eor w2, w4, w20",
        "mrs x1, nzcv",
        "bfi w1, w0, #29, #1",
        "lsr w2, w2, #31",
        "bfi w1, w2, #28, #1",
        "msr nzcv, x1",
        "mov x4, x20"
      ]
    },
    "shl rax, cl": {
      "ExpectedInstructionCount": 13,
      "Comment": "GROUP2 0xd3 /4",
      "ExpectedArm64ASM": [
        "lsl x20, x4, x5",
        "and w0, w5, #0x3f",
        "cbz x0, #+0x28",
        "ands x26, x20, x20",
        "neg x0, x5",
        "lsr x0, x4, x0",
        "eor x2, x4, x20",
        "mrs x1, nzcv",
        "bfi w1, w0, #29, #1",
        "lsr x2, x2, #63",
        "bfi w1, w2, #28, #1",
        "msr nzcv, x1",
        "mov x4, x20"
      ]
    },
    "shr ax, cl": {
      "ExpectedInstructionCount": 15,
      "Comment": "GROUP2 0xd3 /5",
      "ExpectedArm64ASM": [
        "uxth w20, w4",
        "lsr w21, w20, w5",
        "and w0, w5, #0x1f",
        "cbz w0, #+0x2c",
        "cmn wzr, w21, lsl #16",
        "mov x26, x21",
        "sub x0, x5, #0x1 (1)",
        "lsr w0, w20, w0",
        "eor w2, w20, w21",
        "mrs x1, nzcv",
        "bfi w1, w0, #29, #1",
        "lsr w2, w2, #15",
        "bfi w1, w2, #28, #1",
        "msr nzcv, x1",
        "bfxil x4, x21, #0, #16"
      ]
    },
    "shr eax, cl": {
      "ExpectedInstructionCount": 13,
      "Comment": "GROUP2 0xd3 /5",
      "ExpectedArm64ASM": [
        "lsr w20, w4, w5",
        "and w0, w5, #0x1f",
        "cbz w0, #+0x28",
        "ands w26, w20, w20",
        "sub x0, x5, #0x1 (1)",
        "lsr w0, w4, w0",
        "eor w2, w4, w20",
        "mrs x1, nzcv",
        "bfi w1, w0, #29, #1",
        "lsr w2, w2, #31",
        "bfi w1, w2, #28, #1",
        "msr nzcv, x1",
        "mov x4, x20"
      ]
    },
    "shr rax, cl": {
      "ExpectedInstructionCount": 13,
      "Comment": "GROUP2 0xd3 /5",
      "ExpectedArm64ASM": [
        "lsr x20, x4, x5",
        "and w0, w5, #0x3f",
        "cbz x0, #+0x28",
        "ands x26, x20, x20",
        "sub x0, x5, #0x1 (1)",
        "lsr x0, x4, x0",
        "eor x2, x4, x20",
        "mrs x1, nzcv",
        "bfi w1, w0, #29, #1",
        "lsr x2, x2, #63",
        "bfi w1, w2, #28, #1",
        "msr nzcv, x1",
        "mov x4, x20"
      ]
    },
    "sar ax, cl": {
      "ExpectedInstructionCount": 12,
      "Comment": "GROUP2 0xd3 /7",
      "ExpectedArm64ASM": [
        "sxth x20, w4",
        "asr w21, w20, w5",
        "and w0, w5, #0x1f",
        "cbz w0, #+0x20",
        "cmn wzr, w21, lsl #16",
        "mov x26, x21",
        "sub x0, x5, #0x1 (1)",
        "lsr w0, w20, w0",
        "mrs x1, nzcv",
        "bfi w1, w0, #29, #1",
        "msr nzcv, x1",
        "bfxil x4, x21, #0, #16"
      ]
    },
    "sar eax, cl": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xd3 /7",
      "ExpectedArm64ASM": [
        "asr w20, w4, w5",
        "and w0, w5, #0x1f",
        "cbz w0, #+0x1c",
        "ands w26, w20, w20",
        "sub x0, x5, #0x1 (1)",
        "lsr w0, w4, w0",
        "mrs x1, nzcv",
        "bfi w1, w0, #29, #1",
        "msr nzcv, x1",
        "mov x4, x20"
      ]
    },
    "sar rax, cl": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xd3 /7",
      "ExpectedArm64ASM": [
        "asr x20, x4, x5",
        "and w0, w5, #0x3f",
        "cbz x0, #+0x1c",
        "ands x26, x20, x20",
        "sub x0, x5, #0x1 (1)",
        "lsr x0, x4, x0",
        "mrs x1, nzcv",
        "bfi w1, w0, #29, #1",
        "msr nzcv, x1",
        "mov x4, x20"
      ]
    },
    "test bl, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP2 0xf6 /0",
      "ExpectedArm64ASM": [
        "and w26, w7, #0x1",
        "cmn wzr, w26, lsl #24"
      ]
    },
    "not bl": {
      "ExpectedInstructionCount": 1,
      "Comment": "GROUP2 0xf6 /2",
      "ExpectedArm64ASM": [
        "eor x7, x7, #0xff"
      ]
    },
    "not bh": {
      "ExpectedInstructionCount": 1,
      "Comment": "GROUP2 0xf6 /2",
      "ExpectedArm64ASM": [
        "eor x7, x7, #0xff00"
      ]
    },
    "neg bl": {
      "ExpectedInstructionCount": 9,
      "Comment": "GROUP2 0xf6 /3",
      "ExpectedArm64ASM": [
        "cmp wzr, w7, lsl #24",
        "neg w26, w7",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "mov x21, x7",
        "bfxil x21, x26, #0, #8",
        "msr nzcv, x20",
        "mov x27, x7",
        "mov x7, x21"
      ]
    },
    "mul bl": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xf6 /4",
      "ExpectedArm64ASM": [
        "uxtb x20, w7",
        "uxtb x21, w4",
        "mul x20, x20, x21",
        "bfxil x4, x20, #0, #16",
        "ubfx x20, x20, #8, #8",
        "cmp x20, #0x0 (0)",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "imul bl": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xf6 /5",
      "ExpectedArm64ASM": [
        "sxtb x20, w7",
        "sxtb x21, w4",
        "mul x20, x20, x21",
        "bfxil x4, x20, #0, #16",
        "sbfx x21, x20, #8, #8",
        "sbfx x20, x20, #7, #1",
        "cmp x21, x20",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "div bl": {
      "ExpectedInstructionCount": 11,
      "Comment": "GROUP2 0xf6 /6",
      "ExpectedArm64ASM": [
        "uxtb w20, w7",
        "uxth w21, w4",
        "uxth w0, w21",
        "uxth w1, w20",
        "udiv w22, w0, w1",
        "uxth w0, w21",
        "uxth w1, w20",
        "udiv w2, w0, w1",
        "msub w20, w2, w1, w0",
        "bfi x22, x20, #8, #8",
        "bfxil x4, x22, #0, #16"
      ]
    },
    "idiv bl": {
      "ExpectedInstructionCount": 9,
      "Comment": "GROUP2 0xf6 /7",
      "ExpectedArm64ASM": [
        "uxtb w20, w7",
        "uxth w21, w4",
        "sxth x21, w21",
        "sxtb x20, w20",
        "sdiv x22, x21, x20",
        "sdiv x0, x21, x20",
        "msub x20, x0, x20, x21",
        "bfi x22, x20, #8, #8",
        "bfxil x4, x22, #0, #16"
      ]
    },
    "test bx, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP2 0xf7 /0",
      "ExpectedArm64ASM": [
        "and w26, w7, #0x1",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "test ebx, 1": {
      "ExpectedInstructionCount": 1,
      "Comment": "GROUP2 0xf7 /0",
      "ExpectedArm64ASM": [
        "ands w26, w7, #0x1"
      ]
    },
    "test rbx, 1": {
      "ExpectedInstructionCount": 1,
      "Comment": "GROUP2 0xf7 /0",
      "ExpectedArm64ASM": [
        "ands x26, x7, #0x1"
      ]
    },
    "test bx, -1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP2 0xf7 /0",
      "ExpectedArm64ASM": [
        "mov x26, x7",
        "cmn wzr, w26, lsl #16"
      ]
    },
    "test ebx, -1": {
      "ExpectedInstructionCount": 1,
      "Comment": "GROUP2 0xf7 /0",
      "ExpectedArm64ASM": [
        "ands w26, w7, w7"
      ]
    },
    "test rbx, -1": {
      "ExpectedInstructionCount": 1,
      "Comment": "GROUP2 0xf7 /0",
      "ExpectedArm64ASM": [
        "ands x26, x7, x7"
      ]
    },
    "not bx": {
      "ExpectedInstructionCount": 1,
      "Comment": "GROUP2 0xf7 /1",
      "ExpectedArm64ASM": [
        "eor x7, x7, #0xffff"
      ]
    },
    "not ebx": {
      "ExpectedInstructionCount": 1,
      "Comment": "GROUP2 0xf7 /1",
      "ExpectedArm64ASM": [
        "mvn w7, w7"
      ]
    },
    "not rbx": {
      "ExpectedInstructionCount": 1,
      "Comment": "GROUP2 0xf7 /1",
      "ExpectedArm64ASM": [
        "mvn x7, x7"
      ]
    },
    "neg bx": {
      "ExpectedInstructionCount": 9,
      "Comment": "GROUP2 0xf7 /2",
      "ExpectedArm64ASM": [
        "cmp wzr, w7, lsl #16",
        "neg w26, w7",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "mov x21, x7",
        "bfxil x21, x26, #0, #16",
        "msr nzcv, x20",
        "mov x27, x7",
        "mov x7, x21"
      ]
    },
    "neg ebx": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP2 0xf7 /2",
      "ExpectedArm64ASM": [
        "negs w26, w7",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x7",
        "mov x7, x26"
      ]
    },
    "neg rbx": {
      "ExpectedInstructionCount": 6,
      "Comment": "GROUP2 0xf7 /2",
      "ExpectedArm64ASM": [
        "negs x26, x7",
        "mrs x20, nzcv",
        "eor w20, w20, #0x20000000",
        "msr nzcv, x20",
        "mov x27, x7",
        "mov x7, x26"
      ]
    },
    "mul bx": {
      "ExpectedInstructionCount": 8,
      "Comment": "GROUP2 0xf7 /3",
      "ExpectedArm64ASM": [
        "uxth x20, w7",
        "uxth x21, w4",
        "mul x20, x20, x21",
        "bfxil x4, x20, #0, #16",
        "ubfx x20, x20, #16, #16",
        "bfxil x6, x20, #0, #16",
        "cmp x20, #0x0 (0)",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "mul ebx": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP2 0xf7 /3",
      "ExpectedArm64ASM": [
        "mov w20, w7",
        "mov w21, w4",
        "mul x20, x20, x21",
        "mov w4, w20",
        "lsr x6, x20, #32",
        "cmp x6, #0x0 (0)",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "mul rbx": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP2 0xf7 /3",
      "ExpectedArm64ASM": [
        "mul x20, x7, x4",
        "umulh x6, x7, x4",
        "cmp x6, #0x0 (0)",
        "ccmn xzr, #0, #nzCV, eq",
        "mov x4, x20"
      ]
    },
    "imul bx": {
      "ExpectedInstructionCount": 9,
      "Comment": "GROUP2 0xf7 /5",
      "ExpectedArm64ASM": [
        "sxth x20, w7",
        "sxth x21, w4",
        "mul x20, x20, x21",
        "bfxil x4, x20, #0, #16",
        "sbfx x21, x20, #16, #16",
        "bfxil x6, x21, #0, #16",
        "sbfx x20, x20, #15, #1",
        "cmp x21, x20",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "imul ebx": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP2 0xf7 /5",
      "ExpectedArm64ASM": [
        "sxtw x20, w7",
        "sxtw x21, w4",
        "mul x20, x20, x21",
        "mov w4, w20",
        "lsr x6, x20, #32",
        "asr x21, x20, #32",
        "sxtw x20, w20",
        "sbfx x20, x20, #31, #1",
        "cmp x21, x20",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "imul rbx": {
      "ExpectedInstructionCount": 5,
      "Comment": "GROUP2 0xf7 /5",
      "ExpectedArm64ASM": [
        "smulh x6, x7, x4",
        "mul x4, x7, x4",
        "asr x20, x4, #63",
        "cmp x6, x20",
        "ccmn xzr, #0, #nzCV, eq"
      ]
    },
    "div bx": {
      "ExpectedInstructionCount": 12,
      "Comment": "GROUP2 0xf7 /6",
      "ExpectedArm64ASM": [
        "uxth w20, w7",
        "uxth w21, w4",
        "uxth w22, w6",
        "uxth w0, w21",
        "bfi w0, w22, #16, #16",
        "udiv w23, w0, w20",
        "uxth w0, w21",
        "bfi w0, w22, #16, #16",
        "udiv w1, w0, w20",
        "msub w20, w1, w20, w0",
        "bfxil x4, x23, #0, #16",
        "bfxil x6, x20, #0, #16"
      ]
    },
    "div ebx": {
      "ExpectedInstructionCount": 12,
      "Comment": "GROUP2 0xf7 /6",
      "ExpectedArm64ASM": [
        "mov w20, w7",
        "mov w21, w4",
        "mov w22, w6",
        "mov x0, x21",
        "bfi x0, x22, #32, #32",
        "udiv x23, x0, x20",
        "mov w4, w23",
        "mov x0, x21",
        "bfi x0, x22, #32, #32",
        "udiv x1, x0, x20",
        "msub x20, x1, x20, x0",
        "mov w6, w20"
      ]
    },
    "div rbx": {
      "ExpectedInstructionCount": 24,
      "Comment": "GROUP2 0xf7 /6",
      "ExpectedArm64ASM": [
        "cbz x6, #+0x28",
        "mov x0, x6",
        "mov x1, x4",
        "mov x2, x7",
        "ldr x3, [x28, #2800]",
        "str x30, [sp, #-16]!",
        "blr x3",
        "ldr x30, [sp], #16",
        "mov x20, x0",
        "b #+0x8",
        "udiv x20, x4, x7",
        "cbz x6, #+0x28",
        "mov x0, x6",
        "mov x1, x4",
        "mov x2, x7",
        "ldr x3, [x28, #2816]",
        "str x30, [sp, #-16]!",
        "blr x3",
        "ldr x30, [sp], #16",
        "mov x6, x0",
        "b #+0xc",
        "udiv x0, x4, x7",
        "msub x6, x0, x7, x4",
        "mov x4, x20"
      ]
    },
    "idiv bx": {
      "ExpectedInstructionCount": 14,
      "Comment": "GROUP2 0xf7 /7",
      "ExpectedArm64ASM": [
        "uxth w20, w7",
        "uxth w21, w4",
        "uxth w22, w6",
        "uxth w0, w21",
        "bfi w0, w22, #16, #16",
        "sxth w1, w20",
        "sdiv w23, w0, w1",
        "uxth w0, w21",
        "bfi w0, w22, #16, #16",
        "sxth w1, w20",
        "sdiv w2, w0, w1",
        "msub w20, w2, w1, w0",
        "bfxil x4, x23, #0, #16",
        "bfxil x6, x20, #0, #16"
      ]
    },
    "idiv ebx": {
      "ExpectedInstructionCount": 14,
      "Comment": "GROUP2 0xf7 /7",
      "ExpectedArm64ASM": [
        "mov w20, w7",
        "mov w21, w4",
        "mov w22, w6",
        "mov x0, x21",
        "bfi x0, x22, #32, #32",
        "sxtw x1, w20",
        "sdiv x23, x0, x1",
        "mov w4, w23",
        "mov x0, x21",
        "bfi x0, x22, #32, #32",
        "sxtw x2, w20",
        "sdiv x1, x0, x2",
        "msub x20, x1, x2, x0",
        "mov w6, w20"
      ]
    },
    "idiv rbx": {
      "ExpectedInstructionCount": 28,
      "Comment": "GROUP2 0xf7 /7",
      "ExpectedArm64ASM": [
        "asr x0, x4, #63",
        "eor x0, x0, x6",
        "cbz x0, #+0x28",
        "mov x0, x6",
        "mov x1, x4",
        "mov x2, x7",
        "ldr x3, [x28, #2808]",
        "str x30, [sp, #-16]!",
        "blr x3",
        "ldr x30, [sp], #16",
        "mov x20, x0",
        "b #+0x8",
        "sdiv x20, x4, x7",
        "asr x0, x4, #63",
        "eor x0, x0, x6",
        "cbz x0, #+0x28",
        "mov x0, x6",
        "mov x1, x4",
        "mov x2, x7",
        "ldr x3, [x28, #2824]",
        "str x30, [sp, #-16]!",
        "blr x3",
        "ldr x30, [sp], #16",
        "mov x6, x0",
        "b #+0xc",
        "sdiv x0, x4, x7",
        "msub x6, x0, x7, x4",
        "mov x4, x20"
      ]
    },
    "inc al": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP3 0xfe /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "uxtb w27, w4",
        "cset w21, hs",
        "lsl w0, w27, #24",
        "cmn w0, w20, lsl #24",
        "add w26, w27, #0x1 (1)",
        "mrs x20, nzcv",
        "bfi w20, w21, #29, #1",
        "bfxil x4, x26, #0, #8",
        "msr nzcv, x20"
      ]
    },
    "dec al": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP3 0xfe /1",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "uxtb w27, w4",
        "cset w21, hs",
        "lsl w0, w27, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w27, #0x1 (1)",
        "mrs x20, nzcv",
        "bfi w20, w21, #29, #1",
        "bfxil x4, x26, #0, #8",
        "msr nzcv, x20"
      ]
    },
    "inc ax": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP4 0xfe /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "uxth w27, w4",
        "cset w21, hs",
        "lsl w0, w27, #16",
        "cmn w0, w20, lsl #16",
        "add w26, w27, #0x1 (1)",
        "mrs x20, nzcv",
        "bfi w20, w21, #29, #1",
        "bfxil x4, x26, #0, #16",
        "msr nzcv, x20"
      ]
    },
    "inc eax": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP4 0xfe /0",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "adds w26, w4, #0x1 (1)",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "inc rax": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP4 0xfe /0",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "adds x26, x4, #0x1 (1)",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "dec ax": {
      "ExpectedInstructionCount": 10,
      "Comment": "GROUP4 0xfe /1",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "uxth w27, w4",
        "cset w21, hs",
        "lsl w0, w27, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w27, #0x1 (1)",
        "mrs x20, nzcv",
        "bfi w20, w21, #29, #1",
        "bfxil x4, x26, #0, #16",
        "msr nzcv, x20"
      ]
    },
    "dec eax": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP4 0xfe /1",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "subs w26, w4, #0x1 (1)",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "dec rax": {
      "ExpectedInstructionCount": 7,
      "Comment": "GROUP4 0xfe /1",
      "ExpectedArm64ASM": [
        "cset w20, hs",
        "subs x26, x4, #0x1 (1)",
        "mrs x21, nzcv",
        "bfi w21, w20, #29, #1",
        "msr nzcv, x21",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "push ax": {
      "ExpectedInstructionCount": 1,
      "Comment": "GROUP4 0xff /6",
      "ExpectedArm64ASM": [
        "strh w4, [x8, #-2]!"
      ]
    },
    "push rax": {
      "ExpectedInstructionCount": 1,
      "Comment": "GROUP4 0xff /6",
      "ExpectedArm64ASM": [
        "str x4, [x8, #-8]!"
      ]
    },
    "mov byte [rax], 0": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc6 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x0",
        "strb w20, [x4]"
      ]
    },
    "mov word [rax], 0": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc7 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x0",
        "strh w20, [x4]"
      ]
    },
    "mov dword [rax], 0": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc7 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x0",
        "str w20, [x4]"
      ]
    },
    "mov qword [rax], 0": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc7 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x0",
        "str x20, [x4]"
      ]
    },
    "mov byte [rax], 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc6 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "strb w20, [x4]"
      ]
    },
    "mov word [rax], 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc7 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "strh w20, [x4]"
      ]
    },
    "mov dword [rax], 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc7 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "str w20, [x4]"
      ]
    },
    "mov qword [rax], 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc7 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "str x20, [x4]"
      ]
    },
    "mov byte [rax], -1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc6 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "strb w20, [x4]"
      ]
    },
    "mov word [rax], -1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc7 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0xffff",
        "strh w20, [x4]"
      ]
    },
    "mov dword [rax], -1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc7 /0",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "str w20, [x4]"
      ]
    },
    "mov qword [rax], -1": {
      "ExpectedInstructionCount": 2,
      "Comment": "GROUP11 0xc7 /0",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "str x20, [x4]"
      ]
    }
  }
}