mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 15:00:17 +02:00
Ryan Houdek
9c44e295fa
All the changes are RA changes and spilling/filling taking another instruction.
4067 lines
102 KiB
JSON
4067 lines
102 KiB
JSON
{
|
|
"Features": {
|
|
"Bitness": 64,
|
|
"EnabledHostFeatures": [
|
|
"SVE256"
|
|
],
|
|
"DisabledHostFeatures": []
|
|
},
|
|
"Instructions": {
|
|
"vpshufb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x00 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movi v4.16b, #0x8f",
|
|
"and v3.16b, v3.16b, v4.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpshufb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x00 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z4.b, #-113",
|
|
"and z3.d, z3.d, z4.d",
|
|
"tbl v4.16b, {v2.16b}, v3.16b",
|
|
"mov z1.q, z2.q[1]",
|
|
"mov z2.b, p6/m, z1.b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"mov z1.q, q2",
|
|
"mov z2.d, z4.d",
|
|
"not p0.b, p7/z, p6.b",
|
|
"mov z2.b, p0/m, z1.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphaddw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x01 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"addp v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphaddw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x01 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movprfx z0, z2",
|
|
"addp z0.h, p7/m, z0.h, z3.h",
|
|
"uzp1 z2.h, z0.h, z0.h",
|
|
"uzp2 z1.h, z0.h, z0.h",
|
|
"splice z2.d, p6, z2.d, z1.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphaddd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x02 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"addp v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphaddd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x02 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movprfx z0, z2",
|
|
"addp z0.s, p7/m, z0.s, z3.s",
|
|
"uzp1 z2.s, z0.s, z0.s",
|
|
"uzp2 z1.s, z0.s, z0.s",
|
|
"splice z2.d, p6, z2.d, z1.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphaddsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x03 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 v4.8h, v2.8h, v3.8h",
|
|
"uzp2 v2.8h, v2.8h, v3.8h",
|
|
"sqadd v2.8h, v4.8h, v2.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphaddsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x03 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 z4.h, z2.h, z3.h",
|
|
"uzp2 z2.h, z2.h, z3.h",
|
|
"sqadd z2.h, z4.h, z2.h",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaddubsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x04 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uxtl v4.8h, v2.8b",
|
|
"sxtl v5.8h, v3.8b",
|
|
"mul v4.8h, v4.8h, v5.8h",
|
|
"uxtl2 v2.8h, v2.16b",
|
|
"sxtl2 v3.8h, v3.16b",
|
|
"mul v2.8h, v2.8h, v3.8h",
|
|
"uzp1 v3.8h, v4.8h, v2.8h",
|
|
"uzp2 v2.8h, v4.8h, v2.8h",
|
|
"sqadd v2.8h, v3.8h, v2.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaddubsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 12,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x04 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uunpklo z4.h, z2.b",
|
|
"sunpklo z5.h, z3.b",
|
|
"mul z4.h, z4.h, z5.h",
|
|
"uunpkhi z2.h, z2.b",
|
|
"sunpkhi z3.h, z3.b",
|
|
"mul z2.h, z2.h, z3.h",
|
|
"uzp1 z3.h, z4.h, z2.h",
|
|
"uzp2 z2.h, z4.h, z2.h",
|
|
"sqadd z2.h, z3.h, z2.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphsubw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x05 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 v4.8h, v2.8h, v3.8h",
|
|
"uzp2 v2.8h, v2.8h, v3.8h",
|
|
"sub v2.8h, v4.8h, v2.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphsubw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x05 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 z4.h, z2.h, z3.h",
|
|
"uzp2 z2.h, z2.h, z3.h",
|
|
"sub z2.h, z4.h, z2.h",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphsubd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x06 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 v4.4s, v2.4s, v3.4s",
|
|
"uzp2 v2.4s, v2.4s, v3.4s",
|
|
"sub v2.4s, v4.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphsubd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x06 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 z4.s, z2.s, z3.s",
|
|
"uzp2 z2.s, z2.s, z3.s",
|
|
"sub z2.s, z4.s, z2.s",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphsubsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x07 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 v4.8h, v2.8h, v3.8h",
|
|
"uzp2 v2.8h, v2.8h, v3.8h",
|
|
"sqsub v2.8h, v4.8h, v2.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphsubsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 16,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x07 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 z4.h, z2.h, z3.h",
|
|
"uzp2 z2.h, z2.h, z3.h",
|
|
"sqsub z2.h, z4.h, z2.h",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsignb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x08 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqshl v3.16b, v3.16b, #7",
|
|
"srshr v3.16b, v3.16b, #7",
|
|
"mul v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsignb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x08 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqshl z3.b, p7/m, z3.b, #7",
|
|
"srshr z3.b, p7/m, z3.b, #7",
|
|
"mul z2.b, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsignw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x09 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqshl v3.8h, v3.8h, #15",
|
|
"srshr v3.8h, v3.8h, #15",
|
|
"mul v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsignw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x09 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqshl z3.h, p7/m, z3.h, #15",
|
|
"srshr z3.h, p7/m, z3.h, #15",
|
|
"mul z2.h, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsignd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqshl v3.4s, v3.4s, #31",
|
|
"srshr v3.4s, v3.4s, #31",
|
|
"mul v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsignd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0a 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqshl z3.s, p7/m, z3.s, #31",
|
|
"srshr z3.s, p7/m, z3.s, #31",
|
|
"mul z2.s, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmulhrsw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 15,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0b 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smull v4.4s, v2.4h, v3.4h",
|
|
"smull2 v2.4s, v2.8h, v3.8h",
|
|
"sshr v3.4s, v4.4s, #14",
|
|
"sshr v2.4s, v2.4s, #14",
|
|
"movi v4.4s, #0x1, lsl #0",
|
|
"add v3.4s, v3.4s, v4.4s",
|
|
"add v2.4s, v2.4s, v4.4s",
|
|
"shrn v3.4h, v3.4s, #1",
|
|
"mov v0.16b, v3.16b",
|
|
"shrn2 v0.8h, v2.4s, #1",
|
|
"mov v2.16b, v0.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmulhrsw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 21,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0b 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smullb z0.s, z2.h, z3.h",
|
|
"smullt z1.s, z2.h, z3.h",
|
|
"zip1 z4.s, z0.s, z1.s",
|
|
"smullb z0.s, z2.h, z3.h",
|
|
"smullt z1.s, z2.h, z3.h",
|
|
"zip2 z2.s, z0.s, z1.s",
|
|
"movprfx z3, z4",
|
|
"asr z3.s, p7/m, z3.s, #14",
|
|
"asr z2.s, p7/m, z2.s, #14",
|
|
"mov z4.s, #1",
|
|
"add z3.s, z3.s, z4.s",
|
|
"add z2.s, z2.s, z4.s",
|
|
"shrnb z3.h, z3.s, #1",
|
|
"uzp1 z3.h, z3.h, z3.h",
|
|
"shrnb z1.h, z2.s, #1",
|
|
"uzp1 z1.h, z1.h, z1.h",
|
|
"movprfx z2, z3",
|
|
"splice z2.h, p6, z2.h, z1.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpermilps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 14,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movi v4.4s, #0x3, lsl #0",
|
|
"and v3.16b, v3.16b, v4.16b",
|
|
"trn1 v3.16b, v3.16b, v3.16b",
|
|
"trn1 v3.8h, v3.8h, v3.8h",
|
|
"shl v3.16b, v3.16b, #2",
|
|
"mov w20, #0x100",
|
|
"movk w20, #0x302, lsl #16",
|
|
"dup v4.4s, w20",
|
|
"add v3.16b, v4.16b, v3.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpermilps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z4.s, #3",
|
|
"and z3.d, z3.d, z4.d",
|
|
"trn1 z3.b, z3.b, z3.b",
|
|
"trn1 z3.h, z3.h, z3.h",
|
|
"lsl z3.b, p7/m, z3.b, #2",
|
|
"mov w20, #0x100",
|
|
"movk w20, #0x302, lsl #16",
|
|
"mov z4.s, w20",
|
|
"movi v5.2d, #0x0",
|
|
"mov z6.b, #16",
|
|
"mov z1.q, q6",
|
|
"not p0.b, p7/z, p6.b",
|
|
"mov z5.b, p0/m, z1.b",
|
|
"add z4.b, z4.b, z5.b",
|
|
"add z3.b, z4.b, z3.b",
|
|
"tbl z2.b, {z2.b}, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpermilpd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"ushr v3.2d, v3.2d, #1",
|
|
"mov w0, #0x1",
|
|
"dup v4.2d, x0",
|
|
"and v3.16b, v3.16b, v4.16b",
|
|
"trn1 v3.16b, v3.16b, v3.16b",
|
|
"trn1 v3.8h, v3.8h, v3.8h",
|
|
"trn1 v3.4s, v3.4s, v3.4s",
|
|
"shl v3.16b, v3.16b, #3",
|
|
"mov x20, #0x100",
|
|
"movk x20, #0x302, lsl #16",
|
|
"movk x20, #0x504, lsl #32",
|
|
"movk x20, #0x706, lsl #48",
|
|
"dup v4.2d, x20",
|
|
"add v3.16b, v4.16b, v3.16b",
|
|
"tbl v2.16b, {v2.16b}, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpermilpd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 23,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"lsr z3.d, p7/m, z3.d, #1",
|
|
"mov z4.d, #1",
|
|
"and z3.d, z3.d, z4.d",
|
|
"trn1 z3.b, z3.b, z3.b",
|
|
"trn1 z3.h, z3.h, z3.h",
|
|
"trn1 z3.s, z3.s, z3.s",
|
|
"lsl z3.b, p7/m, z3.b, #3",
|
|
"mov x20, #0x100",
|
|
"movk x20, #0x302, lsl #16",
|
|
"movk x20, #0x504, lsl #32",
|
|
"movk x20, #0x706, lsl #48",
|
|
"mov z4.d, x20",
|
|
"movi v5.2d, #0x0",
|
|
"mov z6.b, #16",
|
|
"mov z1.q, q6",
|
|
"not p0.b, p7/z, p6.b",
|
|
"mov z5.b, p0/m, z1.b",
|
|
"add z4.b, z4.b, z5.b",
|
|
"add z3.b, z4.b, z3.b",
|
|
"tbl z2.b, {z2.b}, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vtestps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"mov w20, #0x80000000",
|
|
"dup v4.4s, w20",
|
|
"and v5.16b, v3.16b, v2.16b",
|
|
"bic v2.16b, v3.16b, v2.16b",
|
|
"and v3.16b, v5.16b, v4.16b",
|
|
"and v2.16b, v2.16b, v4.16b",
|
|
"cnt v3.16b, v3.16b",
|
|
"cnt v2.16b, v2.16b",
|
|
"addv h3, v3.8h",
|
|
"addv h2, v2.8h",
|
|
"umov w20, v3.h[0]",
|
|
"umov w21, v2.h[0]",
|
|
"mov w22, #0x0",
|
|
"mov w23, #0x1",
|
|
"cmp x20, #0x0 (0)",
|
|
"cset x20, eq",
|
|
"cmp x21, #0x0 (0)",
|
|
"cset x21, eq",
|
|
"lsl x20, x20, #30",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"mov w21, #0x90000000",
|
|
"bic x20, x20, x21",
|
|
"strb w23, [x28, #706]",
|
|
"strb w22, [x28, #708]",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"vtestps ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 35,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"mov w20, #0x80000000",
|
|
"mov z4.s, w20",
|
|
"and z5.d, z3.d, z2.d",
|
|
"bic z2.d, z3.d, z2.d",
|
|
"and z3.d, z5.d, z4.d",
|
|
"and z2.d, z2.d, z4.d",
|
|
"cnt z3.b, p7/m, z3.b",
|
|
"cnt z2.b, p7/m, z2.b",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z3.d",
|
|
"addv h1, v3.8h",
|
|
"addv h0, v0.8h",
|
|
"add v3.8h, v0.8h, v1.8h",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z2.d",
|
|
"addv h1, v2.8h",
|
|
"addv h0, v0.8h",
|
|
"add v2.8h, v0.8h, v1.8h",
|
|
"umov w20, v3.h[0]",
|
|
"umov w21, v2.h[0]",
|
|
"mov w22, #0x0",
|
|
"mov w23, #0x1",
|
|
"cmp x20, #0x0 (0)",
|
|
"cset x20, eq",
|
|
"cmp x21, #0x0 (0)",
|
|
"cset x21, eq",
|
|
"lsl x20, x20, #30",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"mov w21, #0x90000000",
|
|
"bic x20, x20, x21",
|
|
"strb w23, [x28, #706]",
|
|
"strb w22, [x28, #708]",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"vtestpd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 27,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"mov x20, #0x8000000000000000",
|
|
"dup v4.2d, x20",
|
|
"and v5.16b, v3.16b, v2.16b",
|
|
"bic v2.16b, v3.16b, v2.16b",
|
|
"and v3.16b, v5.16b, v4.16b",
|
|
"and v2.16b, v2.16b, v4.16b",
|
|
"cnt v3.16b, v3.16b",
|
|
"cnt v2.16b, v2.16b",
|
|
"addv h3, v3.8h",
|
|
"addv h2, v2.8h",
|
|
"umov w20, v3.h[0]",
|
|
"umov w21, v2.h[0]",
|
|
"mov w22, #0x0",
|
|
"mov w23, #0x1",
|
|
"cmp x20, #0x0 (0)",
|
|
"cset x20, eq",
|
|
"cmp x21, #0x0 (0)",
|
|
"cset x21, eq",
|
|
"lsl x20, x20, #30",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"mov w21, #0x90000000",
|
|
"bic x20, x20, x21",
|
|
"strb w23, [x28, #706]",
|
|
"strb w22, [x28, #708]",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"vtestpd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 35,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x0f 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"mov x20, #0x8000000000000000",
|
|
"mov z4.d, x20",
|
|
"and z5.d, z3.d, z2.d",
|
|
"bic z2.d, z3.d, z2.d",
|
|
"and z3.d, z5.d, z4.d",
|
|
"and z2.d, z2.d, z4.d",
|
|
"cnt z3.b, p7/m, z3.b",
|
|
"cnt z2.b, p7/m, z2.b",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z3.d",
|
|
"addv h1, v3.8h",
|
|
"addv h0, v0.8h",
|
|
"add v3.8h, v0.8h, v1.8h",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z2.d",
|
|
"addv h1, v2.8h",
|
|
"addv h0, v0.8h",
|
|
"add v2.8h, v0.8h, v1.8h",
|
|
"umov w20, v3.h[0]",
|
|
"umov w21, v2.h[0]",
|
|
"mov w22, #0x0",
|
|
"mov w23, #0x1",
|
|
"cmp x20, #0x0 (0)",
|
|
"cset x20, eq",
|
|
"cmp x21, #0x0 (0)",
|
|
"cset x21, eq",
|
|
"lsl x20, x20, #30",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"mov w21, #0x90000000",
|
|
"bic x20, x20, x21",
|
|
"strb w23, [x28, #706]",
|
|
"strb w22, [x28, #708]",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"vcvtph2ps xmm0, xmm1": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x13 128-bit"
|
|
]
|
|
},
|
|
"vcvtph2ps ymm0, xmm1": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x13 256-bit"
|
|
]
|
|
},
|
|
"vpermps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x16 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z4.s, #7",
|
|
"and z2.d, z2.d, z4.d",
|
|
"trn1 z2.b, z2.b, z2.b",
|
|
"trn1 z2.h, z2.h, z2.h",
|
|
"lsl z2.b, p7/m, z2.b, #2",
|
|
"mov w20, #0x100",
|
|
"movk w20, #0x302, lsl #16",
|
|
"mov z4.s, w20",
|
|
"add z2.b, z2.b, z4.b",
|
|
"tbl z2.b, {z3.b}, z2.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vptest xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 23,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x16 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"and v4.16b, v2.16b, v3.16b",
|
|
"bic v2.16b, v3.16b, v2.16b",
|
|
"cnt v3.16b, v4.16b",
|
|
"cnt v2.16b, v2.16b",
|
|
"addv h3, v3.8h",
|
|
"addv h2, v2.8h",
|
|
"umov w20, v3.h[0]",
|
|
"umov w21, v2.h[0]",
|
|
"mov w22, #0x0",
|
|
"mov w23, #0x1",
|
|
"cmp x20, #0x0 (0)",
|
|
"cset x20, eq",
|
|
"cmp x21, #0x0 (0)",
|
|
"cset x21, eq",
|
|
"lsl x20, x20, #30",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"mov w21, #0x90000000",
|
|
"bic x20, x20, x21",
|
|
"strb w23, [x28, #706]",
|
|
"strb w22, [x28, #708]",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"vptest ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 31,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x16 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"and z4.d, z2.d, z3.d",
|
|
"bic z2.d, z3.d, z2.d",
|
|
"cnt z3.b, p7/m, z4.b",
|
|
"cnt z2.b, p7/m, z2.b",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z3.d",
|
|
"addv h1, v3.8h",
|
|
"addv h0, v0.8h",
|
|
"add v3.8h, v0.8h, v1.8h",
|
|
"not p0.b, p7/z, p6.b",
|
|
"compact z0.d, p0, z2.d",
|
|
"addv h1, v2.8h",
|
|
"addv h0, v0.8h",
|
|
"add v2.8h, v0.8h, v1.8h",
|
|
"umov w20, v3.h[0]",
|
|
"umov w21, v2.h[0]",
|
|
"mov w22, #0x0",
|
|
"mov w23, #0x1",
|
|
"cmp x20, #0x0 (0)",
|
|
"cset x20, eq",
|
|
"cmp x21, #0x0 (0)",
|
|
"cset x21, eq",
|
|
"lsl x20, x20, #30",
|
|
"orr w20, w20, w21, lsl #29",
|
|
"mov w21, #0x90000000",
|
|
"bic x20, x20, x21",
|
|
"strb w23, [x28, #706]",
|
|
"strb w22, [x28, #708]",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"vbroadcastss xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x18 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1rw {z2.s}, p6/z, [x4]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vbroadcastss ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x18 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1rw {z2.s}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vbroadcastsd ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x19 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1rd {z2.d}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vbroadcastf128 ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x1a 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1rqb {z2.b}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpabsb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x1c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"abs v2.16b, v2.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpabsb ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x1c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"abs z2.b, p7/m, z2.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpabsw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x1d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"abs v2.8h, v2.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpabsw ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x1d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"abs z2.h, p7/m, z2.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpabsd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x1e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"abs v2.4s, v2.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpabsd ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x1e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"abs z2.s, p7/m, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxbw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x20 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sxtl v2.8h, v2.8b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxbw ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x20 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sunpklo z2.h, z2.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxbd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x21 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sxtl v2.8h, v2.8b",
|
|
"sxtl v2.4s, v2.4h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxbd ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x21 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sunpklo z2.h, z2.b",
|
|
"sunpklo z2.s, z2.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxbq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x22 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sxtl v2.8h, v2.8b",
|
|
"sxtl v2.4s, v2.4h",
|
|
"sxtl v2.2d, v2.2s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxbq ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x22 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sunpklo z2.h, z2.b",
|
|
"sunpklo z2.s, z2.h",
|
|
"sunpklo z2.d, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxwd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x23 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sxtl v2.4s, v2.4h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxwd ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x23 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sunpklo z2.s, z2.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxwq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x24 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sxtl v2.4s, v2.4h",
|
|
"sxtl v2.2d, v2.2s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxwq ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x24 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sunpklo z2.s, z2.h",
|
|
"sunpklo z2.d, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxdq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x25 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sxtl v2.2d, v2.2s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovsxdq ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x25 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"sunpklo z2.d, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmuldq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x28 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 v2.4s, v2.4s, v2.4s",
|
|
"uzp1 v3.4s, v3.4s, v3.4s",
|
|
"smull v2.2d, v2.2s, v3.2s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmuldq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x28 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"uzp1 z2.s, z2.s, z2.s",
|
|
"uzp1 z3.s, z3.s, z3.s",
|
|
"smullb z0.d, z2.s, z3.s",
|
|
"smullt z1.d, z2.s, z3.s",
|
|
"zip1 z2.d, z0.d, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpeqq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x29 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmeq v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpeqq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x29 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmpeq p0.d, p7/z, z2.d, z3.d",
|
|
"not z0.d, p0/m, z2.d",
|
|
"movprfx z2.d, p0/z, z2.d",
|
|
"orr z2.d, p0/m, z2.d, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovntdqa xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr q2, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmovntdqa ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2a 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1b {z2.b}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpackusdw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2b 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqxtun v2.4h, v2.4s",
|
|
"sqxtun2 v2.8h, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpackusdw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2b 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"sqxtunb z1.h, z3.s",
|
|
"uzp1 z1.h, z1.h, z1.h",
|
|
"sqxtunb z2.h, z2.s",
|
|
"uzp1 z2.h, z2.h, z2.h",
|
|
"splice z2.h, p6, z2.h, z1.h",
|
|
"mov z1.d, z2.d[1]",
|
|
"mov z3.d, z2.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #0",
|
|
"mov z3.d, p0/m, z1.d",
|
|
"mov z1.d, z2.d[2]",
|
|
"mov z2.d, z3.d",
|
|
"index z0.d, #-2, #1",
|
|
"cmpeq p0.d, p7/z, z0.d, #-1",
|
|
"mov z2.d, p0/m, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaskmovps xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"cmplt p0.s, p6/z, z2.s, #0",
|
|
"ld1w {z2.s}, p0/z, [x4]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaskmovps ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"cmplt p0.s, p7/z, z2.s, #0",
|
|
"ld1w {z2.s}, p0/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaskmovpd xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"cmplt p0.d, p6/z, z2.d, #0",
|
|
"ld1d {z2.d}, p0/z, [x4]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaskmovpd ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"cmplt p0.d, p7/z, z2.d, #0",
|
|
"ld1d {z2.d}, p0/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vmaskmovps [rax], xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"cmplt p0.s, p6/z, z2.s, #0",
|
|
"st1w {z3.s}, p0, [x4]"
|
|
]
|
|
},
|
|
"vmaskmovps [rax], ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"cmplt p0.s, p7/z, z2.s, #0",
|
|
"st1w {z3.s}, p0, [x4]"
|
|
]
|
|
},
|
|
"vmaskmovpd [rax], xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"cmplt p0.d, p6/z, z2.d, #0",
|
|
"st1d {z3.d}, p0, [x4]"
|
|
]
|
|
},
|
|
"vmaskmovpd [rax], ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x2f 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"cmplt p0.d, p7/z, z2.d, #0",
|
|
"st1d {z3.d}, p0, [x4]"
|
|
]
|
|
},
|
|
"vpmovzxbw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x30 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uxtl v2.8h, v2.8b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovzxbw ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x30 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uunpklo z2.h, z2.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovzxbd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x31 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uxtl v2.8h, v2.8b",
|
|
"uxtl v2.4s, v2.4h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovzxbd ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x31 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uunpklo z2.h, z2.b",
|
|
"uunpklo z2.s, z2.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovzxbq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x32 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uxtl v2.8h, v2.8b",
|
|
"uxtl v2.4s, v2.4h",
|
|
"uxtl v2.2d, v2.2s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovzxbq ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x32 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uunpklo z2.h, z2.b",
|
|
"uunpklo z2.s, z2.h",
|
|
"uunpklo z2.d, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovzxwd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x33 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uxtl v2.4s, v2.4h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovzxwd ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x33 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uunpklo z2.s, z2.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovzxwq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x34 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uxtl v2.4s, v2.4h",
|
|
"uxtl v2.2d, v2.2s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovzxwq ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x34 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uunpklo z2.s, z2.h",
|
|
"uunpklo z2.d, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovzxdq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x35 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uxtl v2.2d, v2.2s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmovzxdq ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x35 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"uunpklo z2.d, z2.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpermd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 13,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x36 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z4.s, #7",
|
|
"and z2.d, z2.d, z4.d",
|
|
"trn1 z2.b, z2.b, z2.b",
|
|
"trn1 z2.h, z2.h, z2.h",
|
|
"lsl z2.b, p7/m, z2.b, #2",
|
|
"mov w20, #0x100",
|
|
"movk w20, #0x302, lsl #16",
|
|
"mov z4.s, w20",
|
|
"add z2.b, z2.b, z4.b",
|
|
"tbl z2.b, {z3.b}, z2.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpgtq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x37 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmgt v2.2d, v2.2d, v3.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpcmpgtq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x37 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"cmpgt p0.d, p7/z, z2.d, z3.d",
|
|
"not z0.d, p0/m, z2.d",
|
|
"movprfx z2.d, p0/z, z2.d",
|
|
"orr z2.d, p0/m, z2.d, z0.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminsb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x38 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smin v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminsb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x38 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smin z2.b, p7/m, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x39 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smin v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminsd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x39 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smin z2.s, p7/m, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminuw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3a 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umin v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminuw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3a 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umin z2.h, p7/m, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminud xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3b 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umin v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpminud ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3b 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umin z2.s, p7/m, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxsb xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smax v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxsb ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smax z2.b, p7/m, z2.b, z3.b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxsd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3d 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smax v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxsd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3d 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"smax z2.s, p7/m, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxuw xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umax v2.8h, v2.8h, v3.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxuw ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umax z2.h, p7/m, z2.h, z3.h",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxud xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3f 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umax v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaxud ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x3f 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"umax z2.s, p7/m, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmulld xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x40 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mul v2.4s, v2.4s, v3.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmulld ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x40 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mul z2.s, z2.s, z3.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vphminposuw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x41 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"ldr x0, [x28, #1552]",
|
|
"ldr q3, [x0]",
|
|
"zip1 v4.8h, v3.8h, v2.8h",
|
|
"zip2 v2.8h, v3.8h, v2.8h",
|
|
"umin v2.4s, v4.4s, v2.4s",
|
|
"uminv s2, v2.4s",
|
|
"rev32 v2.8h, v2.8h",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrlvd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x45 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movi v0.4s, #0x20, lsl #0",
|
|
"umin v0.4s, v0.4s, v3.4s",
|
|
"neg v0.4s, v0.4s",
|
|
"ushl v2.4s, v2.4s, v0.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrlvd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x45 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z1.s, #32",
|
|
"umin z1.s, p7/m, z1.s, z3.s",
|
|
"lsr z2.s, p7/m, z2.s, z1.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrlvq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x45 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov w0, #0x40",
|
|
"dup v0.2d, x0",
|
|
"cmhi v1.2d, v3.2d, v0.2d",
|
|
"bif v0.16b, v3.16b, v1.16b",
|
|
"neg v0.2d, v0.2d",
|
|
"ushl v2.2d, v2.2d, v0.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsrlvq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x45 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z1.d, #64",
|
|
"umin z1.d, p7/m, z1.d, z3.d",
|
|
"lsr z2.d, p7/m, z2.d, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsravd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x46 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movi v0.4s, #0x1f, lsl #0",
|
|
"umin v0.4s, v0.4s, v3.4s",
|
|
"neg v0.4s, v0.4s",
|
|
"sshl v2.4s, v2.4s, v0.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsravd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x46 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z0.s, #31",
|
|
"umin z0.s, p7/m, z0.s, z3.s",
|
|
"asr z2.s, p7/m, z2.s, z0.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsllvd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x47 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movi v0.4s, #0x20, lsl #0",
|
|
"umin v0.4s, v0.4s, v3.4s",
|
|
"ushl v2.4s, v2.4s, v0.4s",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsllvd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x47 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z1.s, #32",
|
|
"umin z1.s, p7/m, z1.s, z3.s",
|
|
"lsl z2.s, p7/m, z2.s, z1.s",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsllvq xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x47 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov w0, #0x40",
|
|
"dup v0.2d, x0",
|
|
"cmhi v1.2d, v3.2d, v0.2d",
|
|
"bif v0.16b, v3.16b, v1.16b",
|
|
"ushl v2.2d, v2.2d, v0.2d",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpsllvq ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x47 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"mov z1.d, #64",
|
|
"umin z1.d, p7/m, z1.d, z3.d",
|
|
"lsl z2.d, p7/m, z2.d, z1.d",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastd xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x58 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"dup v2.4s, v2.s[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastd xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x58 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1rw {z2.s}, p6/z, [x4]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastd ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x58 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z2.s, s2",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastd ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x58 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1rw {z2.s}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastq xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x59 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"dup v2.2d, v2.d[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastq xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x59 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1rd {z2.d}, p6/z, [x4]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastq ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x59 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z2.d, d2",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastq ymm0, [rax]": {
|
|
"ExpectedInstructiqonCount": -1,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x59 256-bit"
|
|
],
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"ld1rd {z2.d}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vbroadcasti128 ymm0, [rax]": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x5a 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1rqb {z2.b}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastb xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x78 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"dup v2.16b, v2.b[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastb xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x78 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1rb {z2.b}, p6/z, [x4]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastb ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x78 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z2.b, b2",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastb ymm0, [rax]": {
|
|
"ExpectedInstructiqonCount": -1,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x78 256-bit"
|
|
],
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"ld1rb {z2.b}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastw xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x79 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"dup v2.8h, v2.h[0]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastw xmm0, [rax]": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x79 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ld1rh {z2.h}, p6/z, [x4]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastw ymm0, xmm1": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x79 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z2.h, h2",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpbroadcastw ymm0, [rax]": {
|
|
"ExpectedInstructiqonCount": -1,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x79 256-bit"
|
|
],
|
|
"ExpectedInstructionCount": 2,
|
|
"ExpectedArm64ASM": [
|
|
"ld1rh {z2.h}, p7/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaskmovd xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x8c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"cmplt p0.s, p6/z, z2.s, #0",
|
|
"ld1w {z2.s}, p0/z, [x4]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaskmovd ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x8c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"cmplt p0.s, p7/z, z2.s, #0",
|
|
"ld1w {z2.s}, p0/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaskmovq xmm0, xmm1, [rax]": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x8c 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"cmplt p0.d, p6/z, z2.d, #0",
|
|
"ld1d {z2.d}, p0/z, [x4]",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaskmovq ymm0, ymm1, [rax]": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x8c 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"cmplt p0.d, p7/z, z2.d, #0",
|
|
"ld1d {z2.d}, p0/z, [x4]",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vpmaskmovd [rax], xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x8e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"cmplt p0.s, p6/z, z2.s, #0",
|
|
"st1w {z3.s}, p0, [x4]"
|
|
]
|
|
},
|
|
"vpmaskmovd [rax], ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x8e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"cmplt p0.s, p7/z, z2.s, #0",
|
|
"st1w {z3.s}, p0, [x4]"
|
|
]
|
|
},
|
|
"vpmaskmovq [rax], xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x8e 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"cmplt p0.d, p6/z, z2.d, #0",
|
|
"st1d {z3.d}, p0, [x4]"
|
|
]
|
|
},
|
|
"vpmaskmovq [rax], ymm0, ymm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0x8e 256-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z16.d",
|
|
"mov z3.d, p7/m, z17.d",
|
|
"cmplt p0.d, p7/z, z2.d, #0",
|
|
"st1d {z3.d}, p0, [x4]"
|
|
]
|
|
},
|
|
"vpgatherdd xmm0, [xmm1*1 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 128-bit"
|
|
]
|
|
},
|
|
"vpgatherdd xmm0, [xmm1*2 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 128-bit"
|
|
]
|
|
},
|
|
"vpgatherdd xmm0, [xmm1*4 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 128-bit"
|
|
]
|
|
},
|
|
"vpgatherdd xmm0, [xmm1*8 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 128-bit"
|
|
]
|
|
},
|
|
"vpgatherdd ymm0, [ymm1*1 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 256-bit"
|
|
]
|
|
},
|
|
"vpgatherdd ymm0, [ymm1*2 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 256-bit"
|
|
]
|
|
},
|
|
"vpgatherdd ymm0, [ymm1*4 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 256-bit"
|
|
]
|
|
},
|
|
"vpgatherdd ymm0, [ymm1*8 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 256-bit"
|
|
]
|
|
},
|
|
"vpgatherdq xmm0, [xmm1*1 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 128-bit"
|
|
]
|
|
},
|
|
"vpgatherdq xmm0, [xmm1*2 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 128-bit"
|
|
]
|
|
},
|
|
"vpgatherdq xmm0, [xmm1*4 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 128-bit"
|
|
]
|
|
},
|
|
"vpgatherdq xmm0, [xmm1*8 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 128-bit"
|
|
]
|
|
},
|
|
"vpgatherdq ymm0, [xmm1*1 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 256-bit"
|
|
]
|
|
},
|
|
"vpgatherdq ymm0, [xmm1*2 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 256-bit"
|
|
]
|
|
},
|
|
"vpgatherdq ymm0, [xmm1*4 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 256-bit"
|
|
]
|
|
},
|
|
"vpgatherdq ymm0, [xmm1*8 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x90 256-bit"
|
|
]
|
|
},
|
|
"vpgatherqd xmm0, [xmm1*1 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 128-bit"
|
|
]
|
|
},
|
|
"vpgatherqd xmm0, [xmm1*2 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 128-bit"
|
|
]
|
|
},
|
|
"vpgatherqd xmm0, [xmm1*4 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 128-bit"
|
|
]
|
|
},
|
|
"vpgatherqd xmm0, [xmm1*8 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 128-bit"
|
|
]
|
|
},
|
|
"vpgatherqd xmm0, [ymm1*1 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 256-bit"
|
|
]
|
|
},
|
|
"vpgatherqd xmm0, [ymm1*2 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 256-bit"
|
|
]
|
|
},
|
|
"vpgatherqd xmm0, [ymm1*4 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 256-bit"
|
|
]
|
|
},
|
|
"vpgatherqd xmm0, [ymm1*8 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 256-bit"
|
|
]
|
|
},
|
|
"vpgatherqq xmm0, [xmm1*1 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 128-bit"
|
|
]
|
|
},
|
|
"vpgatherqq xmm0, [xmm1*2 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 128-bit"
|
|
]
|
|
},
|
|
"vpgatherqq xmm0, [xmm1*4 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 128-bit"
|
|
]
|
|
},
|
|
"vpgatherqq xmm0, [xmm1*8 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 128-bit"
|
|
]
|
|
},
|
|
"vpgatherqq ymm0, [ymm1*1 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 256-bit"
|
|
]
|
|
},
|
|
"vpgatherqq ymm0, [ymm1*2 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 256-bit"
|
|
]
|
|
},
|
|
"vpgatherqq ymm0, [ymm1*4 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 256-bit"
|
|
]
|
|
},
|
|
"vpgatherqq ymm0, [ymm1*8 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x91 256-bit"
|
|
]
|
|
},
|
|
"vgatherdps xmm0, [xmm1*1 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 128-bit"
|
|
]
|
|
},
|
|
"vgatherdps xmm0, [xmm1*2 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 128-bit"
|
|
]
|
|
},
|
|
"vgatherdps xmm0, [xmm1*4 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 128-bit"
|
|
]
|
|
},
|
|
"vgatherdps xmm0, [xmm1*8 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 128-bit"
|
|
]
|
|
},
|
|
"vgatherdps ymm0, [ymm1*1 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 256-bit"
|
|
]
|
|
},
|
|
"vgatherdps ymm0, [ymm1*2 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 256-bit"
|
|
]
|
|
},
|
|
"vgatherdps ymm0, [ymm1*4 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 256-bit"
|
|
]
|
|
},
|
|
"vgatherdps ymm0, [ymm1*8 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 256-bit"
|
|
]
|
|
},
|
|
"vgatherdpd xmm0, [xmm1*1 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 128-bit"
|
|
]
|
|
},
|
|
"vgatherdpd xmm0, [xmm1*2 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 128-bit"
|
|
]
|
|
},
|
|
"vgatherdpd xmm0, [xmm1*4 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 128-bit"
|
|
]
|
|
},
|
|
"vgatherdpd xmm0, [xmm1*8 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 128-bit"
|
|
]
|
|
},
|
|
"vgatherdpd ymm0, [xmm1*1 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 256-bit"
|
|
]
|
|
},
|
|
"vgatherdpd ymm0, [xmm1*2 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 256-bit"
|
|
]
|
|
},
|
|
"vgatherdpd ymm0, [xmm1*4 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 256-bit"
|
|
]
|
|
},
|
|
"vgatherdpd ymm0, [xmm1*8 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x92 256-bit"
|
|
]
|
|
},
|
|
"vgatherqps xmm0, [xmm1*1 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 128-bit"
|
|
]
|
|
},
|
|
"vgatherqps xmm0, [xmm1*2 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 128-bit"
|
|
]
|
|
},
|
|
"vgatherqps xmm0, [xmm1*4 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 128-bit"
|
|
]
|
|
},
|
|
"vgatherqps xmm0, [xmm1*8 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 128-bit"
|
|
]
|
|
},
|
|
"vgatherqps xmm0, [ymm1*1 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 256-bit"
|
|
]
|
|
},
|
|
"vgatherqps xmm0, [ymm1*2 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 256-bit"
|
|
]
|
|
},
|
|
"vgatherqps xmm0, [ymm1*4 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 256-bit"
|
|
]
|
|
},
|
|
"vgatherqps xmm0, [ymm1*8 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 256-bit"
|
|
]
|
|
},
|
|
"vgatherqpd xmm0, [xmm1*1 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 128-bit"
|
|
]
|
|
},
|
|
"vgatherqpd xmm0, [xmm1*2 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 128-bit"
|
|
]
|
|
},
|
|
"vgatherqpd xmm0, [xmm1*4 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 128-bit"
|
|
]
|
|
},
|
|
"vgatherqpd xmm0, [xmm1*8 + rax], xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 128-bit"
|
|
]
|
|
},
|
|
"vgatherqpd ymm0, [ymm1*1 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 256-bit"
|
|
]
|
|
},
|
|
"vgatherqpd ymm0, [ymm1*2 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 256-bit"
|
|
]
|
|
},
|
|
"vgatherqpd ymm0, [ymm1*4 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 256-bit"
|
|
]
|
|
},
|
|
"vgatherqpd ymm0, [ymm1*8 + rax], ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x93 256-bit"
|
|
]
|
|
},
|
|
"vfmaddsub132ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x96 128-bit"
|
|
]
|
|
},
|
|
"vfmaddsub132ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x96 256-bit"
|
|
]
|
|
},
|
|
"vfmaddsub132pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x96 128-bit"
|
|
]
|
|
},
|
|
"vfmaddsub132pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x96 256-bit"
|
|
]
|
|
},
|
|
"vfmsubadd132ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x97 128-bit"
|
|
]
|
|
},
|
|
"vfmsubadd132ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x97 256-bit"
|
|
]
|
|
},
|
|
"vfmsubadd132pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x97 128-bit"
|
|
]
|
|
},
|
|
"vfmsubadd132pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x97 256-bit"
|
|
]
|
|
},
|
|
"vfmadd132ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x98 128-bit"
|
|
]
|
|
},
|
|
"vfmadd132ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x98 256-bit"
|
|
]
|
|
},
|
|
"vfmadd132pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x98 128-bit"
|
|
]
|
|
},
|
|
"vfmadd132pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x98 256-bit"
|
|
]
|
|
},
|
|
"vfmadd132ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x99 128-bit"
|
|
]
|
|
},
|
|
"vfmadd132sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x99 128-bit"
|
|
]
|
|
},
|
|
"vfmsub132ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9a 128-bit"
|
|
]
|
|
},
|
|
"vfmsub132ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9a 256-bit"
|
|
]
|
|
},
|
|
"vfmsub132pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9a 128-bit"
|
|
]
|
|
},
|
|
"vfmsub132pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9a 256-bit"
|
|
]
|
|
},
|
|
"vfmsub132ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9b 128-bit"
|
|
]
|
|
},
|
|
"vfmsub132sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9b 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd132ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9c 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd132ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9c 256-bit"
|
|
]
|
|
},
|
|
"vfnmadd132pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9c 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd132pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9c 256-bit"
|
|
]
|
|
},
|
|
"vfnmadd132ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9d 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd132sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9d 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub132ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9e 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub132ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9e 256-bit"
|
|
]
|
|
},
|
|
"vfnmsub132pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9e 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub132pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9e 256-bit"
|
|
]
|
|
},
|
|
"vfnmsub132ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9f 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub132sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0x9f 128-bit"
|
|
]
|
|
},
|
|
"vfmadd213ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa8 128-bit"
|
|
]
|
|
},
|
|
"vfmadd213ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa8 256-bit"
|
|
]
|
|
},
|
|
"vfmadd213pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa8 128-bit"
|
|
]
|
|
},
|
|
"vfmadd213pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa8 256-bit"
|
|
]
|
|
},
|
|
"vfmadd213ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa9 128-bit"
|
|
]
|
|
},
|
|
"vfmadd213sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa9 128-bit"
|
|
]
|
|
},
|
|
"vfmsub213ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xaa 128-bit"
|
|
]
|
|
},
|
|
"vfmsub213ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xaa 256-bit"
|
|
]
|
|
},
|
|
"vfmsub213pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xaa 128-bit"
|
|
]
|
|
},
|
|
"vfmsub213pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xaa 256-bit"
|
|
]
|
|
},
|
|
"vfmsub213ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xab 128-bit"
|
|
]
|
|
},
|
|
"vfmsub213sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xab 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd213ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xac 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd213ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xac 256-bit"
|
|
]
|
|
},
|
|
"vfnmadd213pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xac 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd213pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xac 256-bit"
|
|
]
|
|
},
|
|
"vfnmadd213ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xad 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd213sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xad 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub213ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xae 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub213ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xae 256-bit"
|
|
]
|
|
},
|
|
"vfnmsub213pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xae 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub213pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xae 256-bit"
|
|
]
|
|
},
|
|
"vfnmsub213ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xaf 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub213sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xaf 128-bit"
|
|
]
|
|
},
|
|
"vfmadd231ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb8 128-bit"
|
|
]
|
|
},
|
|
"vfmadd231ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb8 256-bit"
|
|
]
|
|
},
|
|
"vfmadd231pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb8 128-bit"
|
|
]
|
|
},
|
|
"vfmadd231pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb8 256-bit"
|
|
]
|
|
},
|
|
"vfmadd231ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb9 128-bit"
|
|
]
|
|
},
|
|
"vfmadd231sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb9 128-bit"
|
|
]
|
|
},
|
|
"vfmsub231ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xba 128-bit"
|
|
]
|
|
},
|
|
"vfmsub231ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xba 256-bit"
|
|
]
|
|
},
|
|
"vfmsub231pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xba 128-bit"
|
|
]
|
|
},
|
|
"vfmsub231pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xba 256-bit"
|
|
]
|
|
},
|
|
"vfmsub231ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbb 128-bit"
|
|
]
|
|
},
|
|
"vfmsub231sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbb 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd231ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbc 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd231ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbc 256-bit"
|
|
]
|
|
},
|
|
"vfnmadd231pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbc 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd231pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbc 256-bit"
|
|
]
|
|
},
|
|
"vfnmadd231ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbd 128-bit"
|
|
]
|
|
},
|
|
"vfnmadd231sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbd 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub231ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbe 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub231ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbe 256-bit"
|
|
]
|
|
},
|
|
"vfnmsub231pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbe 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub231pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbe 256-bit"
|
|
]
|
|
},
|
|
"vfnmsub231ss xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbf 128-bit"
|
|
]
|
|
},
|
|
"vfnmsub231sd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xbf 128-bit"
|
|
]
|
|
},
|
|
"vfmaddsub213ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa6 128-bit"
|
|
]
|
|
},
|
|
"vfmaddsub213ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa6 256-bit"
|
|
]
|
|
},
|
|
"vfmaddsub213pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa6 128-bit"
|
|
]
|
|
},
|
|
"vfmaddsub213pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa6 256-bit"
|
|
]
|
|
},
|
|
"vfmsubadd213ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa7 128-bit"
|
|
]
|
|
},
|
|
"vfmsubadd213ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa7 256-bit"
|
|
]
|
|
},
|
|
"vfmsubadd213pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa7 128-bit"
|
|
]
|
|
},
|
|
"vfmsubadd213pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xa7 256-bit"
|
|
]
|
|
},
|
|
"vfmaddsub231ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb6 128-bit"
|
|
]
|
|
},
|
|
"vfmaddsub231ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb6 256-bit"
|
|
]
|
|
},
|
|
"vfmaddsub231pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb6 128-bit"
|
|
]
|
|
},
|
|
"vfmaddsub231pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb6 256-bit"
|
|
]
|
|
},
|
|
"vfmsubadd231ps xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb7 128-bit"
|
|
]
|
|
},
|
|
"vfmsubadd231ps ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb7 256-bit"
|
|
]
|
|
},
|
|
"vfmsubadd231pd xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb7 128-bit"
|
|
]
|
|
},
|
|
"vfmsubadd231pd ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xb7 256-bit"
|
|
]
|
|
},
|
|
"vaesimc xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0xdb 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"unimplemented (Unimplemented)",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaesenc xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0xdc 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movi v4.2d, #0x0",
|
|
"unimplemented (Unimplemented)",
|
|
"unimplemented (Unimplemented)",
|
|
"eor v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaesenc ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xdc 256-bit"
|
|
]
|
|
},
|
|
"vaesenclast xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0xdd 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movi v4.2d, #0x0",
|
|
"unimplemented (Unimplemented)",
|
|
"eor v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaesenclast ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xdd 256-bit"
|
|
]
|
|
},
|
|
"vaesdec xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0xde 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movi v4.2d, #0x0",
|
|
"unimplemented (Unimplemented)",
|
|
"unimplemented (Unimplemented)",
|
|
"eor v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaesdec ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xde 256-bit"
|
|
]
|
|
},
|
|
"vaesdeclast xmm0, xmm1, xmm2": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0xdf 128-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov z2.d, p7/m, z17.d",
|
|
"mov z3.d, p7/m, z18.d",
|
|
"movi v4.2d, #0x0",
|
|
"unimplemented (Unimplemented)",
|
|
"eor v2.16b, v2.16b, v3.16b",
|
|
"mov v2.16b, v2.16b",
|
|
"mov z16.d, p7/m, z2.d"
|
|
]
|
|
},
|
|
"vaesdeclast ymm0, ymm1, ymm2": {
|
|
"ExpectedInstructionCount": -1,
|
|
"Optimal": "Unknown",
|
|
"Skip": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xdf 256-bit"
|
|
]
|
|
},
|
|
"andn eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b00 0xf2 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w7, #0",
|
|
"lsr w21, w5, #0",
|
|
"bic w4, w21, w20",
|
|
"strb w4, [x28, #706]",
|
|
"tst w4, w4",
|
|
"mrs x20, nzcv",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"andn rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b00 0xf2 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"bic x4, x5, x7",
|
|
"strb w4, [x28, #706]",
|
|
"tst x4, x4",
|
|
"mrs x20, nzcv",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"bzhi eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 18,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b00 0xf5 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w7, #0",
|
|
"lsr w21, w5, #0",
|
|
"and x21, x21, #0xff",
|
|
"mov w22, #0xffff",
|
|
"movk w22, #0xffff, lsl #16",
|
|
"lsl w22, w22, w21",
|
|
"bic w22, w20, w22",
|
|
"cmp x21, #0x1f (31)",
|
|
"csel w4, w20, w22, hi",
|
|
"ldr w20, [x28, #728]",
|
|
"and w20, w20, #0xefffffff",
|
|
"cmp x4, #0x0 (0)",
|
|
"cset x22, eq",
|
|
"bfi w20, w22, #30, #1",
|
|
"cmp x21, #0x1f (31)",
|
|
"cset x21, hi",
|
|
"bfi w20, w21, #29, #1",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"bzhi rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b00 0xf5 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"and x20, x5, #0xff",
|
|
"mov x21, #0xffffffffffffffff",
|
|
"lsl x21, x21, x20",
|
|
"bic x21, x7, x21",
|
|
"cmp x20, #0x3f (63)",
|
|
"csel x4, x7, x21, hi",
|
|
"ldr w21, [x28, #728]",
|
|
"and w21, w21, #0xefffffff",
|
|
"cmp x4, #0x0 (0)",
|
|
"cset x22, eq",
|
|
"bfi w21, w22, #30, #1",
|
|
"cmp x20, #0x3f (63)",
|
|
"cset x20, hi",
|
|
"mov w0, w21",
|
|
"bfi w0, w20, #29, #1",
|
|
"mov w20, w0",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"pext eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b10 0xf5 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w7, #0",
|
|
"lsr w21, w5, #0",
|
|
"cbz w21, #+0x40",
|
|
"mov w0, w21",
|
|
"mov w3, wzr",
|
|
"mov w21, wzr",
|
|
"rbit w1, w0",
|
|
"clz w1, w1",
|
|
"sub w2, w0, #0x1 (1)",
|
|
"ands w0, w2, w0",
|
|
"lsr w1, w20, w1",
|
|
"and w1, w1, #0x1",
|
|
"lsl w1, w1, w3",
|
|
"add w3, w3, #0x1 (1)",
|
|
"orr w21, w1, w21",
|
|
"b.ne #-0x24",
|
|
"mov w4, w21",
|
|
"b #+0x8",
|
|
"mov w4, wzr"
|
|
]
|
|
},
|
|
"pext rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b10 0xf5 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cbz x5, #+0x48",
|
|
"mov x0, x5",
|
|
"mov x3, xzr",
|
|
"str x5, [x28, #16]",
|
|
"mov x5, xzr",
|
|
"rbit x1, x0",
|
|
"clz x1, x1",
|
|
"sub x2, x0, #0x1 (1)",
|
|
"ands x0, x2, x0",
|
|
"lsr x1, x7, x1",
|
|
"and x1, x1, #0x1",
|
|
"lsl x1, x1, x3",
|
|
"add x3, x3, #0x1 (1)",
|
|
"orr x5, x1, x5",
|
|
"b.ne #-0x24",
|
|
"mov x4, x5",
|
|
"ldr x5, [x28, #16]",
|
|
"b #+0x8",
|
|
"mov x4, xzr"
|
|
]
|
|
},
|
|
"pdep eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 25,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b11 0xf5 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w7, #0",
|
|
"lsr w21, w5, #0",
|
|
"cbz w21, #+0x58",
|
|
"mov w3, wzr",
|
|
"stp x4, x5, [x28, #8]",
|
|
"str x6, [x28, #24]",
|
|
"mov w4, w20",
|
|
"mov w5, w21",
|
|
"mov w6, wzr",
|
|
"rbit w0, w5",
|
|
"clz w0, w0",
|
|
"lsr w1, w4, w3",
|
|
"and w1, w1, #0x1",
|
|
"sub w2, w5, #0x1 (1)",
|
|
"add w3, w3, #0x1 (1)",
|
|
"ands w5, w5, w2",
|
|
"lsl w0, w1, w0",
|
|
"orr w6, w6, w0",
|
|
"b.ne #-0x24",
|
|
"mov w3, w6",
|
|
"ldp x4, x5, [x28, #8]",
|
|
"ldr x6, [x28, #24]",
|
|
"mov w4, w3",
|
|
"b #+0x8",
|
|
"mov w4, wzr"
|
|
]
|
|
},
|
|
"pdep rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 23,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b11 0xf5 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"cbz x5, #+0x58",
|
|
"mov x3, xzr",
|
|
"stp x4, x5, [x28, #8]",
|
|
"str x6, [x28, #24]",
|
|
"mov x4, x7",
|
|
"mov x5, x5",
|
|
"mov x6, xzr",
|
|
"rbit x0, x5",
|
|
"clz x0, x0",
|
|
"lsr x1, x4, x3",
|
|
"and x1, x1, #0x1",
|
|
"sub x2, x5, #0x1 (1)",
|
|
"add x3, x3, #0x1 (1)",
|
|
"ands x5, x5, x2",
|
|
"lsl x0, x1, x0",
|
|
"orr x6, x6, x0",
|
|
"b.ne #-0x24",
|
|
"mov x3, x6",
|
|
"ldp x4, x5, [x28, #8]",
|
|
"ldr x6, [x28, #24]",
|
|
"mov x4, x3",
|
|
"b #+0x8",
|
|
"mov x4, xzr"
|
|
]
|
|
},
|
|
"mulx eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b11 0xf6 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w5, #0",
|
|
"lsr w21, w6, #0",
|
|
"mul w7, w20, w21",
|
|
"ubfx x0, x20, #0, #32",
|
|
"ubfx x1, x21, #0, #32",
|
|
"mul x4, x0, x1",
|
|
"lsr x4, x4, #32"
|
|
]
|
|
},
|
|
"mulx rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Optimal": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b11 0xf6 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mul x7, x5, x6",
|
|
"umulh x4, x5, x6"
|
|
]
|
|
},
|
|
"bextr eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b00 0xf7 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w7, #0",
|
|
"lsr w21, w5, #0",
|
|
"mov w22, #0x1f",
|
|
"uxtb w23, w21",
|
|
"lsr w20, w20, w23",
|
|
"mov w24, #0x0",
|
|
"cmp w23, #0x1f (31)",
|
|
"csel w20, w20, w24, ls",
|
|
"ubfx w21, w21, #8, #8",
|
|
"cmp w21, #0x1f (31)",
|
|
"csel w21, w21, w22, ls",
|
|
"mov w22, #0x1",
|
|
"lsl w21, w22, w21",
|
|
"sub w21, w21, #0x1 (1)",
|
|
"and w4, w20, w21",
|
|
"cmp x4, #0x0 (0)",
|
|
"cset x20, eq",
|
|
"lsl x20, x20, #30",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"bextr rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 17,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b00 0xf7 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x3f",
|
|
"uxtb x21, w5",
|
|
"lsr x22, x7, x21",
|
|
"mov w23, #0x0",
|
|
"cmp x21, #0x3f (63)",
|
|
"csel x21, x22, x23, ls",
|
|
"ubfx x22, x5, #8, #8",
|
|
"cmp x22, #0x3f (63)",
|
|
"csel x20, x22, x20, ls",
|
|
"mov w22, #0x1",
|
|
"lsl x20, x22, x20",
|
|
"sub x20, x20, #0x1 (1)",
|
|
"and x4, x21, x20",
|
|
"cmp x4, #0x0 (0)",
|
|
"cset x20, eq",
|
|
"lsl x20, x20, #30",
|
|
"str w20, [x28, #728]"
|
|
]
|
|
},
|
|
"shlx eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b01 0xf7 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w7, #0",
|
|
"lsr w21, w5, #0",
|
|
"lsl w4, w20, w21"
|
|
]
|
|
},
|
|
"shlx rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Optimal": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b01 0xf7 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"lsl x4, x7, x5"
|
|
]
|
|
},
|
|
"sarx eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b10 0xf7 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w7, #0",
|
|
"lsr w21, w5, #0",
|
|
"asr w4, w20, w21"
|
|
]
|
|
},
|
|
"sarx rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Optimal": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b10 0xf7 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"asr x4, x7, x5"
|
|
]
|
|
},
|
|
"shrx eax, ebx, ecx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Optimal": "No",
|
|
"Comment": [
|
|
"Map 2 0b11 0xf7 32-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w7, #0",
|
|
"lsr w21, w5, #0",
|
|
"lsr w4, w20, w21"
|
|
]
|
|
},
|
|
"shrx rax, rbx, rcx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Optimal": "Yes",
|
|
"Comment": [
|
|
"Map 2 0b11 0xf7 64-bit"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"lsr x4, x7, x5"
|
|
]
|
|
}
|
|
}
|
|
}
|