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Alyssa Rosenzweig
725d0e187a
I recommend viewing the new source file as the diff is quite messy. --- The old RA commits every "how not to write an RA" sin in the book. Chaitin spill-one loop? Check. Potential spilling caused by alignment issues since there's no live range splitting? Check. Panic spilling? Check. Generating an interference graph with linear live ranges, so you get the code quality of linear scan with the cost of graph colouring? Check. ... It is wholly unsuitable to any application, and specifically unsuitable for FEX. --- The new RA exploits a key IR invariant unique to FEX: no values are live across block boundaries. This is validated. Because of this invariant, all RA is block local. This lets us use a dead simple 2 pass RA that generates ~optimal code in linear time. The first pass walks the IR backwards, analyzing the IR. This is a souped up analogue to liveness analysis. The second pass walks the IR forward, blasting out registers. If necessary, it will insert spill and/or shuffle code on the fly. Spilling uses the well-known furthest-first heuristic, which has excellent results for straight line code. That's it :-) Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
38 lines
892 B
C++
38 lines
892 B
C++
// SPDX-License-Identifier: MIT
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/*
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$info$
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tags: ir|opts
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$end_info$
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*/
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#pragma once
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#include "Interface/IR/PassManager.h"
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#include <memory>
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#include <stdint.h>
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namespace FEXCore::IR {
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class RegisterAllocationData;
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struct RegisterAllocationDataDeleter;
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struct RegisterClassType;
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class RegisterAllocationPass : public FEXCore::IR::Pass {
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public:
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virtual void AddRegisters(FEXCore::IR::RegisterClassType Class, uint32_t RegisterCount) = 0;
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// Number of GPRs usable for pairs at start of GPR set. Must be even.
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uint32_t PairRegs;
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/**
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* @brief Returns the register and class map array
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*/
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virtual RegisterAllocationData* GetAllocationData() = 0;
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/**
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* @brief Returns and transfers ownership of the register and class map array
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*/
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virtual std::unique_ptr<RegisterAllocationData, RegisterAllocationDataDeleter> PullAllocationData() = 0;
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};
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} // namespace FEXCore::IR
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