mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-09 19:00:20 +02:00
Scott Mansell
d32ebc0de0
Needed to support binaries linked with glibc 2.30 and later. glibc doesn't actually check CPUID, as kernel support is needed. Instead, it just calls ARCH_CET_STATUS and checks for an error.
122 lines
3.7 KiB
C++
122 lines
3.7 KiB
C++
#include "Interface/Core/CPUID.h"
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namespace FEXCore {
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CPUIDEmu::FunctionResults CPUIDEmu::Function_0h() {
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CPUIDEmu::FunctionResults Res{};
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Res.Res[0] = 0x16; // Let's say we are a Skylake
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// EBX, EDX, ECX become the manufacturer id string
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Res.Res[1] = 0x756E6547; // "Genu"
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Res.Res[2] = 0x49656E69; // "ineI"
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Res.Res[3] = 0x6C65746E; // "ntel"
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return Res;
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}
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// Processor Info and Features bits
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CPUIDEmu::FunctionResults CPUIDEmu::Function_01h() {
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CPUIDEmu::FunctionResults Res{};
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Res.Res[0] = 0 | // Stepping
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(0 << 4) | // Model
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(0 << 8) | // Family ID
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(0 << 12) | // Processor type
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(0 << 16) | // Extended model ID
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(0 << 20); // Extended family ID
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Res.Res[1] = 0 | // Brand index
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(8 << 8) | // Cache line size in bytes
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(8 << 16) | // Number of addressable IDs for the logical cores in the physical CPU
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(0 << 24); // Local APIC ID
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Res.Res[2] = ~0U; // Let's say we support every feature for fun
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Res.Res[3] = ~0U; // Let's say we support every feature for fun
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Res.Res[3] &= ~(3 << 26); // Let's say that XSAVE isn't enabled by the OS. Prevents glibc from using XSAVE/XGETBV
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return Res;
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}
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// Cache and TLB description
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CPUIDEmu::FunctionResults CPUIDEmu::Function_02h() {
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CPUIDEmu::FunctionResults Res{};
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return Res;
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}
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// Deterministic cache parameters for each level
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CPUIDEmu::FunctionResults CPUIDEmu::Function_04h() {
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CPUIDEmu::FunctionResults Res{};
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return Res;
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}
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CPUIDEmu::FunctionResults CPUIDEmu::Function_07h() {
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CPUIDEmu::FunctionResults Res{};
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// Number of subfunctions
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Res.Res[0] = 0x0;
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Res.Res[1] =
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(1 << 0) | // FS/GS support
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(1 << 3) | // BMI 1 support
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(1 << 5) | // AVX2 support
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(1 << 7) | // SMEP support
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(1 << 8) // BMI2 support
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;
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Res.Res[2] = ~0U;
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Res.Res[3] = ~0U;
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Res.Res[2] &= ~(1 << 20); // we don't support CET indirect branch tracking
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Res.Res[3] &= ~(1 << 7); // we don't support CET shadow stack features
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return Res;
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}
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CPUIDEmu::FunctionResults CPUIDEmu::Function_0Dh() {
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CPUIDEmu::FunctionResults Res{};
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return Res;
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}
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// Highest extended function implemented
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CPUIDEmu::FunctionResults CPUIDEmu::Function_8000_0000h() {
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CPUIDEmu::FunctionResults Res{};
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Res.Res[0] = 0x8000001F;
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return Res;
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}
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// Extended processor and feature bits
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CPUIDEmu::FunctionResults CPUIDEmu::Function_8000_0001h() {
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CPUIDEmu::FunctionResults Res{};
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Res.Res[2] = ~0U; // Let's say we support every feature for fun
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Res.Res[3] = ~0U; // Let's say we support every feature for fun
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return Res;
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}
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// Advanced power management
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CPUIDEmu::FunctionResults CPUIDEmu::Function_8000_0006h() {
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CPUIDEmu::FunctionResults Res{};
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Res.Res[0] = (1 << 2); // APIC timer not affected by p-state
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return Res;
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}
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CPUIDEmu::FunctionResults CPUIDEmu::Function_8000_0007h() {
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CPUIDEmu::FunctionResults Res{};
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return Res;
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}
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// Virtual and physical address sizes
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CPUIDEmu::FunctionResults CPUIDEmu::Function_8000_0008h() {
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CPUIDEmu::FunctionResults Res{};
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return Res;
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}
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void CPUIDEmu::Init() {
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RegisterFunction(0, std::bind(&CPUIDEmu::Function_0h, this));
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RegisterFunction(1, std::bind(&CPUIDEmu::Function_01h, this));
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RegisterFunction(2, std::bind(&CPUIDEmu::Function_02h, this));
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RegisterFunction(4, std::bind(&CPUIDEmu::Function_04h, this));
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RegisterFunction(7, std::bind(&CPUIDEmu::Function_07h, this));
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RegisterFunction(0xD, std::bind(&CPUIDEmu::Function_0Dh, this));
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RegisterFunction(0x8000'0000, std::bind(&CPUIDEmu::Function_8000_0000h, this));
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RegisterFunction(0x8000'0001, std::bind(&CPUIDEmu::Function_8000_0001h, this));
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RegisterFunction(0x8000'0006, std::bind(&CPUIDEmu::Function_8000_0006h, this));
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RegisterFunction(0x8000'0007, std::bind(&CPUIDEmu::Function_8000_0007h, this));
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RegisterFunction(0x8000'0008, std::bind(&CPUIDEmu::Function_8000_0008h, this));
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}
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}
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