FEX-Emu--FEX/unittests/InstructionCountCI/VEX_map1_FRINTTS.json

{
  "Features": {
    "Bitness": 64,
    "EnabledHostFeatures": [
      "SVE128",
      "SVE256",
      "FRINTTS"
    ],
    "DisabledHostFeatures": [
      "FCMA",
      "RPRES",
      "AFP",
      "FLAGM",
      "FLAGM2"
    ],
    "BinaryCacheVersion": 12
  },
  "Instructions": {
    "vcvttss2si eax, xmm0": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "Map 1 0b10 0x2c 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint32z s2, s16",
        "fcvtzs w4, s2"
      ]
    },
    "vcvttss2si rax, xmm0": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "Map 1 0b10 0x2c 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint64z s2, s16",
        "fcvtzs x4, s2"
      ]
    },
    "vcvttsd2si eax, xmm0": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "Map 1 0b11 0x2c 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint32z d2, d16",
        "fcvtzs w4, d2"
      ]
    },
    "vcvttsd2si rax, xmm0": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "Map 1 0b11 0x2c 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint64z d2, d16",
        "fcvtzs x4, d2"
      ]
    },
    "vcvtss2si eax, xmm0": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "Map 1 0b10 0x2d 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint32x s2, s16",
        "fcvtzs w4, s2"
      ]
    },
    "vcvtss2si rax, xmm0": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "Map 1 0b10 0x2d 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint64x s2, s16",
        "fcvtzs x4, s2"
      ]
    },
    "vcvtsd2si eax, xmm0": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "Map 1 0b11 0x2d 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint32x d2, d16",
        "fcvtzs w4, d2"
      ]
    },
    "vcvtsd2si rax, xmm0": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "Map 1 0b11 0x2d 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint64x d2, d16",
        "fcvtzs x4, d2"
      ]
    },
    "vcvtps2dq xmm0, xmm1": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "Map 1 0b01 0x5b 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint32x v2.4s, v17.4s",
        "fcvtzs v16.4s, v2.4s"
      ]
    },
    "vcvtps2dq ymm0, ymm1": {
      "ExpectedInstructionCount": 13,
      "Comment": [
        "Map 1 0b01 0x5b 256-bit"
      ],
      "ExpectedArm64ASM": [
        "frinti z2.s, p7/m, z17.s",
        "ldr x0, [x28, #2664]",
        "ld1b {z3.b}, p7/z, [x0]",
        "ldr x0, [x28, #2616]",
        "ld1b {z4.b}, p7/z, [x0]",
        "fcvtzs z5.s, p7/m, z2.s",
        "fcmgt p0.s, p7/z, z4.s, z2.s",
        "not z0.s, p0/m, z4.s",
        "movprfx z2.s, p0/z, z4.s",
        "orr z2.s, p0/m, z2.s, z0.s",
        "movprfx z0, z5",
        "bsl z0.d, z0.d, z3.d, z2.d",
        "mov z16.d, z0.d"
      ]
    },
    "vcvttps2dq xmm0, xmm1": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "Map 1 0b10 0x5b 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint32z v2.4s, v17.4s",
        "fcvtzs v16.4s, v2.4s"
      ]
    },
    "vcvttps2dq ymm0, ymm1": {
      "ExpectedInstructionCount": 12,
      "Comment": [
        "Map 1 0b10 0x5b 256-bit"
      ],
      "ExpectedArm64ASM": [
        "ldr x0, [x28, #2664]",
        "ld1b {z2.b}, p7/z, [x0]",
        "ldr x0, [x28, #2616]",
        "ld1b {z3.b}, p7/z, [x0]",
        "fcvtzs z4.s, p7/m, z17.s",
        "fcmgt p0.s, p7/z, z3.s, z17.s",
        "not z0.s, p0/m, z3.s",
        "movprfx z3.s, p0/z, z3.s",
        "orr z3.s, p0/m, z3.s, z0.s",
        "movprfx z0, z4",
        "bsl z0.d, z0.d, z2.d, z3.d",
        "mov z16.d, z0.d"
      ]
    },
    "vcvttpd2dq xmm0, xmm1": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "Map 1 0b01 0xe6 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint32z v2.2d, v17.2d",
        "fcvtzs v2.2d, v2.2d",
        "xtn v16.2s, v2.2d"
      ]
    },
    "vcvttpd2dq xmm0, ymm1": {
      "ExpectedInstructionCount": 15,
      "Comment": [
        "Map 1 0b01 0xe6 256-bit"
      ],
      "ExpectedArm64ASM": [
        "ldr q2, [x28, #3664]",
        "ldr x0, [x28, #2640]",
        "ld1b {z3.b}, p7/z, [x0]",
        "fcvtzs z4.s, p7/m, z17.d",
        "uzp1 z4.s, z4.s, z4.s",
        "mov v4.16b, v4.16b",
        "fcmgt p0.d, p7/z, z3.d, z17.d",
        "not z0.d, p0/m, z3.d",
        "movprfx z3.d, p0/z, z3.d",
        "orr z3.d, p0/m, z3.d, z0.d",
        "shrnb z3.s, z3.d, #32",
        "uzp1 z3.s, z3.s, z3.s",
        "movprfx z0, z4",
        "bsl z0.d, z0.d, z2.d, z3.d",
        "mov z16.d, z0.d"
      ]
    },
    "vcvtpd2dq xmm0, xmm1": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "Map 1 0b11 0xe6 128-bit"
      ],
      "ExpectedArm64ASM": [
        "frint32x v2.2d, v17.2d",
        "fcvtzs v2.2d, v2.2d",
        "xtn v16.2s, v2.2d"
      ]
    },
    "vcvtpd2dq xmm0, ymm1": {
      "ExpectedInstructionCount": 16,
      "Comment": [
        "Map 1 0b11 0xe6 256-bit"
      ],
      "ExpectedArm64ASM": [
        "frinti z2.d, p7/m, z17.d",
        "ldr q3, [x28, #3664]",
        "ldr x0, [x28, #2640]",
        "ld1b {z4.b}, p7/z, [x0]",
        "fcvtzs z5.s, p7/m, z2.d",
        "uzp1 z5.s, z5.s, z5.s",
        "mov v5.16b, v5.16b",
        "fcmgt p0.d, p7/z, z4.d, z2.d",
        "not z0.d, p0/m, z4.d",
        "movprfx z2.d, p0/z, z4.d",
        "orr z2.d, p0/m, z2.d, z0.d",
        "shrnb z2.s, z2.d, #32",
        "uzp1 z2.s, z2.s, z2.s",
        "movprfx z0, z5",
        "bsl z0.d, z0.d, z3.d, z2.d",
        "mov z16.d, z0.d"
      ]
    }
  }
}