mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 08:00:15 +02:00
1205 lines
33 KiB
JSON
1205 lines
33 KiB
JSON
{
|
|
"Features": {
|
|
"Env": {
|
|
"FEX_X87REDUCEDPRECISION": "1"
|
|
},
|
|
"Bitness": 32,
|
|
"EnabledHostFeatures": [
|
|
"FLAGM",
|
|
"FLAGM2"
|
|
],
|
|
"DisabledHostFeatures": [
|
|
"SVE128",
|
|
"SVE256",
|
|
"AFP"
|
|
],
|
|
"BinaryCacheVersion": 12
|
|
},
|
|
"Instructions": {
|
|
"Block1": {
|
|
"x86InstructionCount": 70,
|
|
"ExpectedInstructionCount": 107,
|
|
"x86Insts": [
|
|
"sub esp,0x2c",
|
|
"mov ecx,dword [esp + 0x34]",
|
|
"mov edx,dword [esp + 0x30]",
|
|
"mov eax,dword [esp + 0x38]",
|
|
"fld dword [ecx]",
|
|
"fld dword [edx]",
|
|
"fld st1",
|
|
"fsub st0,st1",
|
|
"fld dword [ecx + 0x4]",
|
|
"fld dword [edx + 0x4]",
|
|
"fld st1",
|
|
"fsub st0,st1",
|
|
"fstp dword [esp + 0x10]",
|
|
"fld dword [ecx + 0x8]",
|
|
"fld dword [edx + 0x8]",
|
|
"fld st1",
|
|
"fsub st0,st1",
|
|
"fstp dword [esp + 0x14]",
|
|
"fld dword [eax]",
|
|
"fsubr st7,st0",
|
|
"fxch st7",
|
|
"fstp dword [esp + 0x18]",
|
|
"fld dword [eax + 0x4]",
|
|
"fsubr st4,st0",
|
|
"fxch st4",
|
|
"fstp dword [esp + 0x1c]",
|
|
"fld dword [eax + 0x8]",
|
|
"fsubr st2,st0",
|
|
"fxch st6",
|
|
"fsubrp st7,st0",
|
|
"fxch st2",
|
|
"fsubrp st3,st0",
|
|
"fxch st4",
|
|
"fsubp",
|
|
"fxch st2",
|
|
"fmul st0",
|
|
"fldz",
|
|
"faddp",
|
|
"fld dword [esp + 0x10]",
|
|
"fld st0",
|
|
"fmulp",
|
|
"faddp",
|
|
"fld dword [esp + 0x14]",
|
|
"fld st0",
|
|
"fmulp",
|
|
"faddp",
|
|
"fld dword [esp + 0x18]",
|
|
"fld st0",
|
|
"fmulp",
|
|
"fldz",
|
|
"faddp",
|
|
"fld dword [esp + 0x1c]",
|
|
"fld st0",
|
|
"fmulp",
|
|
"faddp",
|
|
"fxch st4",
|
|
"fmul st0",
|
|
"faddp st4,st0",
|
|
"fxch st4",
|
|
"fmul st0",
|
|
"fldz",
|
|
"faddp",
|
|
"fxch",
|
|
"fmul st0",
|
|
"faddp",
|
|
"fxch",
|
|
"fmul st0",
|
|
"faddp",
|
|
"fxch st2",
|
|
"fucomi st0,st1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sub w8, w8, #0x2c (44)",
|
|
"ldr w7, [x8, #52]",
|
|
"ldr w5, [x8, #48]",
|
|
"ldr w4, [x8, #56]",
|
|
"ldr s2, [x7]",
|
|
"fcvt d2, s2",
|
|
"ldr s3, [x5]",
|
|
"fcvt d3, s3",
|
|
"fsub d4, d2, d3",
|
|
"ldr s5, [x7, #4]",
|
|
"fcvt d5, s5",
|
|
"ldr s6, [x5, #4]",
|
|
"fcvt d6, s6",
|
|
"fsub d7, d5, d6",
|
|
"fcvt s7, d7",
|
|
"str s7, [x8, #16]",
|
|
"ldr s7, [x7, #8]",
|
|
"fcvt d7, s7",
|
|
"ldr s8, [x5, #8]",
|
|
"fcvt d8, s8",
|
|
"fsub d9, d7, d8",
|
|
"fcvt s9, d9",
|
|
"str s9, [x8, #20]",
|
|
"ldr s9, [x4]",
|
|
"fcvt d9, s9",
|
|
"fsub d2, d9, d2",
|
|
"mov w27, #0x0",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcvt s2, d2",
|
|
"str s2, [x8, #24]",
|
|
"ldr s2, [x4, #4]",
|
|
"fcvt d2, s2",
|
|
"fsub d5, d2, d5",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcvt s5, d5",
|
|
"str s5, [x8, #28]",
|
|
"ldr s5, [x4, #8]",
|
|
"fcvt d5, s5",
|
|
"fsub d7, d5, d7",
|
|
"strb wzr, [x28, #1049]",
|
|
"fsub d3, d3, d9",
|
|
"strb wzr, [x28, #1049]",
|
|
"fsub d2, d6, d2",
|
|
"strb wzr, [x28, #1049]",
|
|
"fsub d5, d8, d5",
|
|
"strb wzr, [x28, #1049]",
|
|
"fmul d4, d4, d4",
|
|
"fmov d6, x27",
|
|
"fadd d4, d4, d6",
|
|
"ldr s6, [x8, #16]",
|
|
"fcvt d6, s6",
|
|
"fmul d6, d6, d6",
|
|
"fadd d4, d4, d6",
|
|
"ldr s6, [x8, #20]",
|
|
"fcvt d6, s6",
|
|
"fmul d6, d6, d6",
|
|
"fadd d4, d4, d6",
|
|
"ldr s6, [x8, #24]",
|
|
"fcvt d6, s6",
|
|
"fmul d6, d6, d6",
|
|
"fmov d8, x27",
|
|
"fadd d6, d6, d8",
|
|
"ldr s8, [x8, #28]",
|
|
"fcvt d8, s8",
|
|
"fmul d8, d8, d8",
|
|
"fadd d6, d6, d8",
|
|
"strb wzr, [x28, #1049]",
|
|
"fmul d7, d7, d7",
|
|
"fadd d6, d6, d7",
|
|
"strb wzr, [x28, #1049]",
|
|
"fmul d3, d3, d3",
|
|
"fmov d7, x27",
|
|
"fadd d3, d3, d7",
|
|
"strb wzr, [x28, #1049]",
|
|
"fmul d2, d2, d2",
|
|
"fadd d2, d3, d2",
|
|
"strb wzr, [x28, #1049]",
|
|
"fmul d3, d5, d5",
|
|
"fadd d2, d2, d3",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcmp d4, d6",
|
|
"cset x26, vc",
|
|
"axflag",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x5 (5)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d4, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"str d6, [x21, #1056]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x8",
|
|
"sub w20, w22, w20",
|
|
"mov w22, #0x707",
|
|
"lsr w22, w22, w20",
|
|
"orr w21, w21, w22",
|
|
"mov w22, #0xf8f8",
|
|
"lsr w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"Block2": {
|
|
"x86InstructionCount": 37,
|
|
"ExpectedInstructionCount": 70,
|
|
"x86Insts": [
|
|
"sub esp,0x1c",
|
|
"mov edx,dword [esp + 0x20]",
|
|
"mov eax,dword [esp + 0x24]",
|
|
"fld dword [edx]",
|
|
"fabs",
|
|
"fld dword [eax]",
|
|
"fabs",
|
|
"fxch",
|
|
"fucomi st0,st1",
|
|
"fcmovbe st0,st1",
|
|
"fstp st1",
|
|
"fld dword [edx + 0x4]",
|
|
"fabs",
|
|
"fld dword [eax + 0x4]",
|
|
"fabs",
|
|
"fxch",
|
|
"fucomi st0,st1",
|
|
"fcmovbe st0,st1",
|
|
"fstp st1",
|
|
"fld dword [edx + 0x8]",
|
|
"fabs",
|
|
"fld dword [eax + 0x8]",
|
|
"fabs",
|
|
"fxch",
|
|
"fucomi st0,st1",
|
|
"fcmovbe st0,st1",
|
|
"fstp st1",
|
|
"fld st2",
|
|
"fmulp st3",
|
|
"fxch",
|
|
"fmul st0",
|
|
"faddp st2,st0",
|
|
"fmul st0",
|
|
"faddp",
|
|
"fld st0",
|
|
"fsqrt",
|
|
"fucomi st0,st0"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"sub w8, w8, #0x1c (28)",
|
|
"ldr w5, [x8, #32]",
|
|
"ldr w4, [x8, #36]",
|
|
"ldr s2, [x5]",
|
|
"fcvt d2, s2",
|
|
"fabs d2, d2",
|
|
"ldr s3, [x4]",
|
|
"fcvt d3, s3",
|
|
"fabs d3, d3",
|
|
"mov w27, #0x0",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcmp d2, d3",
|
|
"axflag",
|
|
"csetm x20, ls",
|
|
"dup v4.2d, x20",
|
|
"bsl v4.16b, v3.16b, v2.16b",
|
|
"ldr s2, [x5, #4]",
|
|
"fcvt d2, s2",
|
|
"fabs d2, d2",
|
|
"ldr s3, [x4, #4]",
|
|
"fcvt d3, s3",
|
|
"fabs d3, d3",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcmp d2, d3",
|
|
"axflag",
|
|
"csetm x20, ls",
|
|
"dup v5.2d, x20",
|
|
"bsl v5.16b, v3.16b, v2.16b",
|
|
"ldr s2, [x5, #8]",
|
|
"fcvt d2, s2",
|
|
"fabs d2, d2",
|
|
"ldr s3, [x4, #8]",
|
|
"fcvt d3, s3",
|
|
"fabs d3, d3",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcmp d2, d3",
|
|
"axflag",
|
|
"csetm x20, ls",
|
|
"dup v6.2d, x20",
|
|
"bsl v6.16b, v3.16b, v2.16b",
|
|
"fmul d2, d4, d4",
|
|
"strb wzr, [x28, #1049]",
|
|
"fmul d3, d5, d5",
|
|
"fadd d2, d2, d3",
|
|
"fmul d3, d6, d6",
|
|
"fadd d2, d2, d3",
|
|
"fsqrt d3, d2",
|
|
"fcmp d3, d3",
|
|
"cset x26, vc",
|
|
"axflag",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x6 (6)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d3, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x8",
|
|
"sub w20, w22, w20",
|
|
"mov w22, #0x303",
|
|
"lsr w22, w22, w20",
|
|
"orr w21, w21, w22",
|
|
"mov w22, #0xc0c0",
|
|
"lsr w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"Block3": {
|
|
"x86InstructionCount": 32,
|
|
"ExpectedInstructionCount": 60,
|
|
"x86Insts": [
|
|
"fld dword [ecx]",
|
|
"fld dword [edx + 0x4]",
|
|
"fld dword [ecx + 0x4]",
|
|
"fld dword [edx]",
|
|
"fld dword [ecx + 0x8]",
|
|
"fstp dword [esp]",
|
|
"fld dword [edx + 0x8]",
|
|
"fld st4",
|
|
"fmul st4",
|
|
"fld st3",
|
|
"fmul st3",
|
|
"fsubp",
|
|
"fmul dword [eax + 0x8]",
|
|
"fxch st2",
|
|
"fmul dword [esp]",
|
|
"fxch st5",
|
|
"fmul st1",
|
|
"fsubp st5,st0",
|
|
"fld dword [eax + 0x4]",
|
|
"fmulp st5",
|
|
"fxch st4",
|
|
"faddp",
|
|
"fxch st3",
|
|
"fmulp",
|
|
"fxch",
|
|
"fmul dword [esp]",
|
|
"mov byte [esp],0x1",
|
|
"fsubp",
|
|
"fmul dword [eax]",
|
|
"faddp",
|
|
"fdivrp",
|
|
"fstp dword [esi]"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x7]",
|
|
"fcvt d2, s2",
|
|
"ldr s3, [x5, #4]",
|
|
"fcvt d3, s3",
|
|
"ldr s4, [x7, #4]",
|
|
"fcvt d4, s4",
|
|
"ldr s5, [x5]",
|
|
"fcvt d5, s5",
|
|
"ldr s6, [x7, #8]",
|
|
"str s6, [x8]",
|
|
"ldr s6, [x5, #8]",
|
|
"fcvt d6, s6",
|
|
"fmul d7, d2, d3",
|
|
"fmul d8, d4, d5",
|
|
"fsub d7, d7, d8",
|
|
"ldr s8, [x4, #8]",
|
|
"fcvt d8, s8",
|
|
"fmul d7, d7, d8",
|
|
"strb wzr, [x28, #1049]",
|
|
"ldr s8, [x8]",
|
|
"fcvt d8, s8",
|
|
"fmul d5, d5, d8",
|
|
"strb wzr, [x28, #1049]",
|
|
"fmul d2, d2, d6",
|
|
"fsub d2, d5, d2",
|
|
"ldr s5, [x4, #4]",
|
|
"fcvt d5, s5",
|
|
"fmul d2, d2, d5",
|
|
"strb wzr, [x28, #1049]",
|
|
"fadd d2, d7, d2",
|
|
"strb wzr, [x28, #1049]",
|
|
"fmul d4, d4, d6",
|
|
"strb wzr, [x28, #1049]",
|
|
"ldr s5, [x8]",
|
|
"fcvt d5, s5",
|
|
"fmul d3, d3, d5",
|
|
"mov w20, #0x1",
|
|
"strb w20, [x8]",
|
|
"fsub d3, d4, d3",
|
|
"ldr s4, [x4]",
|
|
"fcvt d4, s4",
|
|
"fmul d3, d3, d4",
|
|
"fadd d2, d2, d3",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"fdiv d3, d2, d3",
|
|
"fcvt s4, d3",
|
|
"str s4, [x10]",
|
|
"add w21, w21, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"strb w21, [x28, #1051]",
|
|
"str d2, [x20, #1056]",
|
|
"str d3, [x22, #1056]",
|
|
"strb wzr, [x28, #1202]"
|
|
]
|
|
},
|
|
"Block4": {
|
|
"x86InstructionCount": 54,
|
|
"ExpectedInstructionCount": 36,
|
|
"x86Insts": [
|
|
"push ebp",
|
|
"push edi",
|
|
"push esi",
|
|
"push ebx",
|
|
"sub esp,0x4c",
|
|
"mov eax,dword [esp + 0x68]",
|
|
"lea ebp,[esp + 0x38]",
|
|
"lea esi,[esp + 0x30]",
|
|
"fld qword [0x00052098]",
|
|
"mov dword [esp + 0xc],esi",
|
|
"mov edi,dword [esp + 0x64]",
|
|
"mov dword [esp + 0x8],ebp",
|
|
"mov ebx,dword [esp + 0x6c]",
|
|
"mov dword [esp + 0x28],eax",
|
|
"mov eax,dword [esp + 0x60]",
|
|
"fmul dword [eax + 0x4]",
|
|
"fstp dword [esp + 0x2c]",
|
|
"fld dword [esp + 0x2c]",
|
|
"fstp qword [esp]",
|
|
"call 0x0006d100",
|
|
"mov eax,dword [esp + 0x60]",
|
|
"mov dword [esp + 0xc],esi",
|
|
"mov dword [esp + 0x8],ebp",
|
|
"fld qword [esp + 0x38]",
|
|
"fstp dword [esp + 0x18]",
|
|
"fld qword [esp + 0x30]",
|
|
"fstp dword [esp + 0x1c]",
|
|
"fld qword [0x00052098]",
|
|
"fmul dword [eax]",
|
|
"fstp dword [esp + 0x2c]",
|
|
"fld dword [esp + 0x2c]",
|
|
"fstp qword [esp]",
|
|
"call 0x0006d100",
|
|
"mov eax,dword [esp + 0x60]",
|
|
"mov dword [esp + 0xc],esi",
|
|
"mov dword [esp + 0x8],ebp",
|
|
"fld qword [esp + 0x38]",
|
|
"fstp dword [esp + 0x20]",
|
|
"fld qword [esp + 0x30]",
|
|
"fstp dword [esp + 0x24]",
|
|
"fld qword [0x00052098]",
|
|
"fmul dword [eax + 0x8]",
|
|
"fstp dword [esp + 0x2c]",
|
|
"fld dword [esp + 0x2c]",
|
|
"fstp qword [esp]",
|
|
"call 0x0006d100",
|
|
"test edi,edi",
|
|
"mov eax,dword [esp + 0x28]",
|
|
"fld qword [esp + 0x38]",
|
|
"fstp dword [esp + 0x2c]",
|
|
"fld dword [esp + 0x2c]",
|
|
"fld qword [esp + 0x30]",
|
|
"fstp dword [esp + 0x2c]",
|
|
"fld dword [esp + 0x2c]"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"stp w11, w9, [x8, #-8]!",
|
|
"stp w6, w10, [x8, #-8]!",
|
|
"subs w26, w8, #0x4c (76)",
|
|
"mov x27, x8",
|
|
"mov x8, x26",
|
|
"ldr w4, [x8, #104]",
|
|
"add w9, w8, #0x38 (56)",
|
|
"add w10, w8, #0x30 (48)",
|
|
"mov w20, #0x2098",
|
|
"movk w20, #0x5, lsl #16",
|
|
"ldr d2, [x20]",
|
|
"str w10, [x8, #12]",
|
|
"ldr w11, [x8, #100]",
|
|
"str w9, [x8, #8]",
|
|
"ldr w6, [x8, #108]",
|
|
"str w4, [x8, #40]",
|
|
"ldr w4, [x8, #96]",
|
|
"ldr s3, [x4, #4]",
|
|
"fcvt d3, s3",
|
|
"fmul d2, d2, d3",
|
|
"fcvt s2, d2",
|
|
"str s2, [x8, #44]",
|
|
"ldr s2, [x8, #44]",
|
|
"fcvt d2, s2",
|
|
"str d2, [x8]",
|
|
"mov w20, #0x44",
|
|
"movk w20, #0x1, lsl #16",
|
|
"str w20, [x8, #-4]!",
|
|
"ldrb w21, [x28, #1051]",
|
|
"ldrb w22, [x28, #1202]",
|
|
"mov w23, #0x1",
|
|
"add w21, w21, #0x7 (7)",
|
|
"and w21, w21, #0x7",
|
|
"lsl w21, w23, w21",
|
|
"bic w21, w22, w21",
|
|
"strb w21, [x28, #1202]"
|
|
]
|
|
},
|
|
"Block5": {
|
|
"x86InstructionCount": 49,
|
|
"ExpectedInstructionCount": 88,
|
|
"x86Insts": [
|
|
"fld dword [esp + 0x80]",
|
|
"fsub dword [esp + 0x7c]",
|
|
"mov eax,dword [esp + 0x88]",
|
|
"mov ecx,dword [esp + 0x8c]",
|
|
"movss xmm1,dword [esp + 0x7c]",
|
|
"mov dword [esp + 0x38],edx",
|
|
"fst dword [esp + 0x34]",
|
|
"fld dword [esp + 0x24]",
|
|
"fld st0",
|
|
"fmulp st2",
|
|
"fxch",
|
|
"fadd dword [esp + 0x7c]",
|
|
"fstp dword [esp + 0x2c]",
|
|
"fld dword [eax]",
|
|
"fsub dword [ebp]",
|
|
"movss xmm0,dword [esp + 0x2c]",
|
|
"fmul st1",
|
|
"fadd dword [ebp]",
|
|
"fstp dword [esp + 0x44]",
|
|
"fld dword [eax + 0x4]",
|
|
"fsub dword [ebp + 0x4]",
|
|
"fmul st1",
|
|
"fadd dword [ebp + 0x4]",
|
|
"fstp dword [esp + 0x48]",
|
|
"fld dword [eax + 0x8]",
|
|
"fsub dword [ebp + 0x8]",
|
|
"fmulp",
|
|
"fadd dword [ebp + 0x8]",
|
|
"mov dword [esp + 0x1c],ecx",
|
|
"movss dword [esp + 0x10],xmm0",
|
|
"lea ecx,[esp + 0x44]",
|
|
"movss dword [esp + 0xc],xmm1",
|
|
"mov dword [esp + 0x18],ecx",
|
|
"mov dword [esp + 0x14],ebp",
|
|
"fstp dword [esp + 0x4c]",
|
|
"fldz",
|
|
"fld dword [esp + 0x28]",
|
|
"fxch",
|
|
"fucomip st0,st1",
|
|
"fstp st0",
|
|
"seta byte [esp + 0x30]",
|
|
"movzx eax,byte [esp + 0x30]",
|
|
"movsx eax,word [esi + eax*0x2 + 0x4]",
|
|
"mov dword [esp + 0x8],eax",
|
|
"mov dword [esp + 0x4],ebx",
|
|
"mov dword [esp],edi",
|
|
"call 0x0002b5b0",
|
|
"mov edx,dword [esp + 0x38]",
|
|
"test al,al"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x8, #128]",
|
|
"fcvt d2, s2",
|
|
"ldr s3, [x8, #124]",
|
|
"fcvt d3, s3",
|
|
"fsub d2, d2, d3",
|
|
"ldr w4, [x8, #136]",
|
|
"ldr w7, [x8, #140]",
|
|
"ldr s17, [x8, #124]",
|
|
"str w5, [x8, #56]",
|
|
"fcvt s3, d2",
|
|
"str s3, [x8, #52]",
|
|
"ldr s3, [x8, #36]",
|
|
"fcvt d3, s3",
|
|
"fmul d2, d2, d3",
|
|
"mov w27, #0x0",
|
|
"strb wzr, [x28, #1049]",
|
|
"ldr s4, [x8, #124]",
|
|
"fcvt d4, s4",
|
|
"fadd d2, d2, d4",
|
|
"fcvt s2, d2",
|
|
"str s2, [x8, #44]",
|
|
"ldr s2, [x4]",
|
|
"fcvt d2, s2",
|
|
"ldr s4, [x9]",
|
|
"fcvt d4, s4",
|
|
"fsub d2, d2, d4",
|
|
"ldr s16, [x8, #44]",
|
|
"fmul d2, d2, d3",
|
|
"ldr s4, [x9]",
|
|
"fcvt d4, s4",
|
|
"fadd d2, d2, d4",
|
|
"fcvt s2, d2",
|
|
"str s2, [x8, #68]",
|
|
"ldr s2, [x4, #4]",
|
|
"fcvt d2, s2",
|
|
"ldr s4, [x9, #4]",
|
|
"fcvt d4, s4",
|
|
"fsub d2, d2, d4",
|
|
"fmul d2, d2, d3",
|
|
"ldr s4, [x9, #4]",
|
|
"fcvt d4, s4",
|
|
"fadd d2, d2, d4",
|
|
"fcvt s2, d2",
|
|
"str s2, [x8, #72]",
|
|
"ldr s2, [x4, #8]",
|
|
"fcvt d2, s2",
|
|
"ldr s4, [x9, #8]",
|
|
"fcvt d4, s4",
|
|
"fsub d2, d2, d4",
|
|
"fmul d2, d3, d2",
|
|
"ldr s3, [x9, #8]",
|
|
"fcvt d3, s3",
|
|
"fadd d2, d2, d3",
|
|
"str w7, [x8, #28]",
|
|
"str s16, [x8, #16]",
|
|
"add w7, w8, #0x44 (68)",
|
|
"str s17, [x8, #12]",
|
|
"str w7, [x8, #24]",
|
|
"str w9, [x8, #20]",
|
|
"fcvt s2, d2",
|
|
"str s2, [x8, #76]",
|
|
"fmov d2, x27",
|
|
"ldr s3, [x8, #40]",
|
|
"fcvt d3, s3",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcmp d2, d3",
|
|
"cset x26, vc",
|
|
"axflag",
|
|
"cset x20, hi",
|
|
"strb w20, [x8, #48]",
|
|
"ldrb w4, [x8, #48]",
|
|
"add w20, w10, w4, lsl #1",
|
|
"ldrh w20, [x20, #4]",
|
|
"sxth w4, w20",
|
|
"str w4, [x8, #8]",
|
|
"str w6, [x8, #4]",
|
|
"str w11, [x8]",
|
|
"mov w20, #0xb2",
|
|
"movk w20, #0x1, lsl #16",
|
|
"str w20, [x8, #-4]!",
|
|
"ldrb w21, [x28, #1051]",
|
|
"ldrb w22, [x28, #1202]",
|
|
"mov w23, #0x8",
|
|
"sub w21, w23, w21",
|
|
"mov w23, #0xe0e0",
|
|
"lsr w21, w23, w21",
|
|
"bic w21, w22, w21",
|
|
"strb w21, [x28, #1202]"
|
|
]
|
|
},
|
|
"Block6": {
|
|
"x86InstructionCount": 39,
|
|
"ExpectedInstructionCount": 90,
|
|
"x86Insts": [
|
|
"push ebp",
|
|
"push edi",
|
|
"push esi",
|
|
"push ebx",
|
|
"sub esp,0x4",
|
|
"mov ecx,dword [esp + 0x20]",
|
|
"mov ebx,dword [esp + 0x24]",
|
|
"mov eax,dword [esp + 0x1c]",
|
|
"mov edx,dword [esp + 0x18]",
|
|
"fld dword [ecx]",
|
|
"fmul dword [ebx + 0x4]",
|
|
"mov ebp,dword [esp + 0x28]",
|
|
"mov edi,dword [esp + 0x2c]",
|
|
"mov esi,dword [esp + 0x30]",
|
|
"fld dword [ecx + 0x4]",
|
|
"fmul dword [ebx]",
|
|
"fsubp",
|
|
"fld dword [ebx]",
|
|
"fmul dword [ecx + 0x8]",
|
|
"fld dword [ecx]",
|
|
"fmul dword [ebx + 0x8]",
|
|
"fsubp",
|
|
"fld dword [ecx + 0x4]",
|
|
"fmul dword [ebx + 0x8]",
|
|
"fld dword [ebx + 0x4]",
|
|
"fmul dword [ecx + 0x8]",
|
|
"fsubp",
|
|
"fld dword [eax + 0x8]",
|
|
"fmul st3",
|
|
"fld dword [eax + 0x4]",
|
|
"fmul st3",
|
|
"faddp",
|
|
"fld dword [eax]",
|
|
"fmul st2",
|
|
"faddp",
|
|
"fldz",
|
|
"fxch",
|
|
"fucomi st0,st1",
|
|
"fstp st1"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"stp w11, w9, [x8, #-8]!",
|
|
"stp w6, w10, [x8, #-8]!",
|
|
"sub w8, w8, #0x4 (4)",
|
|
"ldr w7, [x8, #32]",
|
|
"ldr w6, [x8, #36]",
|
|
"ldr w4, [x8, #28]",
|
|
"ldr w5, [x8, #24]",
|
|
"ldr s2, [x7]",
|
|
"fcvt d2, s2",
|
|
"ldr s3, [x6, #4]",
|
|
"fcvt d3, s3",
|
|
"fmul d2, d2, d3",
|
|
"ldr w9, [x8, #40]",
|
|
"ldr w11, [x8, #44]",
|
|
"ldr w10, [x8, #48]",
|
|
"ldr s3, [x7, #4]",
|
|
"fcvt d3, s3",
|
|
"ldr s4, [x6]",
|
|
"fcvt d4, s4",
|
|
"fmul d3, d3, d4",
|
|
"fsub d2, d2, d3",
|
|
"ldr s3, [x6]",
|
|
"fcvt d3, s3",
|
|
"ldr s4, [x7, #8]",
|
|
"fcvt d4, s4",
|
|
"fmul d3, d3, d4",
|
|
"ldr s4, [x7]",
|
|
"fcvt d4, s4",
|
|
"ldr s5, [x6, #8]",
|
|
"fcvt d5, s5",
|
|
"fmul d4, d4, d5",
|
|
"fsub d3, d3, d4",
|
|
"ldr s4, [x7, #4]",
|
|
"fcvt d4, s4",
|
|
"ldr s5, [x6, #8]",
|
|
"fcvt d5, s5",
|
|
"fmul d4, d4, d5",
|
|
"ldr s5, [x6, #4]",
|
|
"fcvt d5, s5",
|
|
"ldr s6, [x7, #8]",
|
|
"fcvt d6, s6",
|
|
"fmul d5, d5, d6",
|
|
"fsub d4, d4, d5",
|
|
"ldr s5, [x4, #8]",
|
|
"fcvt d5, s5",
|
|
"fmul d5, d5, d2",
|
|
"ldr s6, [x4, #4]",
|
|
"fcvt d6, s6",
|
|
"fmul d6, d6, d3",
|
|
"fadd d5, d5, d6",
|
|
"ldr s6, [x4]",
|
|
"fcvt d6, s6",
|
|
"fmul d6, d6, d4",
|
|
"fadd d5, d5, d6",
|
|
"mov w27, #0x0",
|
|
"fmov d6, x27",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcmp d5, d6",
|
|
"cset x26, vc",
|
|
"axflag",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x4 (4)",
|
|
"and w20, w20, #0x7",
|
|
"strb w20, [x28, #1051]",
|
|
"add x21, x28, x20, lsl #4",
|
|
"str d5, [x21, #1056]",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"str d4, [x21, #1056]",
|
|
"add w21, w20, #0x2 (2)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"str d3, [x21, #1056]",
|
|
"add w21, w20, #0x3 (3)",
|
|
"and w21, w21, #0x7",
|
|
"add x21, x28, x21, lsl #4",
|
|
"str d2, [x21, #1056]",
|
|
"ldrb w21, [x28, #1202]",
|
|
"mov w22, #0x8",
|
|
"sub w22, w22, w20",
|
|
"mov w23, #0xf0f",
|
|
"lsr w22, w23, w22",
|
|
"orr w21, w21, w22",
|
|
"mov w22, #0x1",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"lsl w20, w22, w20",
|
|
"bic w20, w21, w20",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"Block7": {
|
|
"x86InstructionCount": 25,
|
|
"ExpectedInstructionCount": 61,
|
|
"x86Insts": [
|
|
"fld dword [ebx + 0x4]",
|
|
"fld dword [ebx]",
|
|
"fld dword [ebx + 0x8]",
|
|
"fld dword [edx]",
|
|
"fmul st3",
|
|
"fld dword [edx + 0x4]",
|
|
"fmul st3",
|
|
"fsubp",
|
|
"fmul dword [eax + 0x8]",
|
|
"fxch st2",
|
|
"fmul dword [edx + 0x8]",
|
|
"fld dword [edx]",
|
|
"fmul st2",
|
|
"fsubp",
|
|
"fmul dword [eax + 0x4]",
|
|
"faddp st2,st0",
|
|
"fmul dword [edx + 0x4]",
|
|
"fxch st2",
|
|
"fmul dword [edx + 0x8]",
|
|
"fsubp st2,st0",
|
|
"fxch",
|
|
"fmul dword [eax]",
|
|
"faddp",
|
|
"fdiv st0,st1",
|
|
"fstp dword [edi]"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldr s2, [x6, #4]",
|
|
"fcvt d2, s2",
|
|
"ldr s3, [x6]",
|
|
"fcvt d3, s3",
|
|
"ldr s4, [x6, #8]",
|
|
"fcvt d4, s4",
|
|
"ldr s5, [x5]",
|
|
"fcvt d5, s5",
|
|
"fmul d5, d5, d2",
|
|
"ldr s6, [x5, #4]",
|
|
"fcvt d6, s6",
|
|
"fmul d6, d6, d3",
|
|
"fsub d5, d5, d6",
|
|
"ldr s6, [x4, #8]",
|
|
"fcvt d6, s6",
|
|
"fmul d5, d5, d6",
|
|
"strb wzr, [x28, #1049]",
|
|
"ldr s6, [x5, #8]",
|
|
"fcvt d6, s6",
|
|
"fmul d3, d3, d6",
|
|
"ldr s6, [x5]",
|
|
"fcvt d6, s6",
|
|
"fmul d6, d6, d4",
|
|
"fsub d3, d3, d6",
|
|
"ldr s6, [x4, #4]",
|
|
"fcvt d6, s6",
|
|
"fmul d3, d3, d6",
|
|
"fadd d3, d5, d3",
|
|
"ldr s5, [x5, #4]",
|
|
"fcvt d5, s5",
|
|
"fmul d4, d4, d5",
|
|
"strb wzr, [x28, #1049]",
|
|
"ldr s5, [x5, #8]",
|
|
"fcvt d5, s5",
|
|
"fmul d2, d2, d5",
|
|
"fsub d2, d4, d2",
|
|
"strb wzr, [x28, #1049]",
|
|
"ldr s4, [x4]",
|
|
"fcvt d4, s4",
|
|
"fmul d2, d2, d4",
|
|
"fadd d2, d3, d2",
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x7 (7)",
|
|
"and w20, w20, #0x7",
|
|
"add w21, w20, #0x1 (1)",
|
|
"and w21, w21, #0x7",
|
|
"add x22, x28, x21, lsl #4",
|
|
"ldr d3, [x22, #1056]",
|
|
"add x20, x28, x20, lsl #4",
|
|
"fdiv d2, d2, d3",
|
|
"fcvt s3, d2",
|
|
"str s3, [x11]",
|
|
"strb w21, [x28, #1051]",
|
|
"str d2, [x20, #1056]",
|
|
"ldrb w20, [x28, #1202]",
|
|
"mov w22, #0x8",
|
|
"sub w21, w22, w21",
|
|
"mov w22, #0xf8f8",
|
|
"lsr w21, w22, w21",
|
|
"bic w20, w20, w21",
|
|
"strb w20, [x28, #1202]"
|
|
]
|
|
},
|
|
"Block8": {
|
|
"x86InstructionCount": 25,
|
|
"ExpectedInstructionCount": 47,
|
|
"x86Insts": [
|
|
"fstp st0",
|
|
"fstp st3",
|
|
"fstp st0",
|
|
"fstp st3",
|
|
"fxch",
|
|
"fxch st2",
|
|
"fstp dword [esp + 0x38]",
|
|
"fxch",
|
|
"fstp dword [esp + 0x2c]",
|
|
"fxch",
|
|
"fstp dword [esp + 0x28]",
|
|
"fstp qword [esp]",
|
|
"call 0x0006d0d8",
|
|
"fld dword [ebx]",
|
|
"fld dword [ebx + 0x4]",
|
|
"fld dword [ebx + 0x8]",
|
|
"fld dword [esp + 0x38]",
|
|
"fld dword [esp + 0x2c]",
|
|
"fld dword [esp + 0x28]",
|
|
"fxch st6",
|
|
"fxch st5",
|
|
"fxch",
|
|
"fxch st4",
|
|
"fxch st3",
|
|
"fxch"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"add x22, x28, x22, lsl #4",
|
|
"ldr d4, [x22, #1056]",
|
|
"strb wzr, [x28, #1049]",
|
|
"add w20, w20, #0x2 (2)",
|
|
"and w20, w20, #0x7",
|
|
"add x23, x28, x20, lsl #4",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcvt s5, d3",
|
|
"str s5, [x8, #56]",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcvt s5, d4",
|
|
"str s5, [x8, #44]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x12, x28, x20, lsl #4",
|
|
"ldr d5, [x12, #1056]",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcvt s6, d5",
|
|
"str s6, [x8, #40]",
|
|
"str d2, [x8]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"mov w13, #0x24",
|
|
"movk w13, #0x1, lsl #16",
|
|
"str w13, [x8, #-4]!",
|
|
"strb w20, [x28, #1051]",
|
|
"str d3, [x21, #1056]",
|
|
"str d4, [x22, #1056]",
|
|
"str d5, [x23, #1056]",
|
|
"str d2, [x12, #1056]",
|
|
"strb wzr, [x28, #1202]"
|
|
]
|
|
},
|
|
"Block9": {
|
|
"x86InstructionCount": 25,
|
|
"ExpectedInstructionCount": 47,
|
|
"x86Insts": [
|
|
"fstp st0",
|
|
"fstp st3",
|
|
"fstp st0",
|
|
"fstp st3",
|
|
"fxch",
|
|
"fxch st2",
|
|
"fstp dword [esp + 0x38]",
|
|
"fxch",
|
|
"fstp dword [esp + 0x2c]",
|
|
"fxch",
|
|
"fstp dword [esp + 0x28]",
|
|
"fstp qword [esp]",
|
|
"call 0x0006d0d8",
|
|
"fld dword [ebx]",
|
|
"fld dword [ebx + 0x4]",
|
|
"fld dword [ebx + 0x8]",
|
|
"fld dword [esp + 0x38]",
|
|
"fld dword [esp + 0x2c]",
|
|
"fld dword [esp + 0x28]",
|
|
"fxch st6",
|
|
"fxch st5",
|
|
"fxch",
|
|
"fxch st4",
|
|
"fxch st3",
|
|
"fxch"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"ldrb w20, [x28, #1051]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d2, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"ldr d3, [x21, #1056]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x21, x28, x20, lsl #4",
|
|
"add w22, w20, #0x1 (1)",
|
|
"and w22, w22, #0x7",
|
|
"add x22, x28, x22, lsl #4",
|
|
"ldr d4, [x22, #1056]",
|
|
"strb wzr, [x28, #1049]",
|
|
"add w20, w20, #0x2 (2)",
|
|
"and w20, w20, #0x7",
|
|
"add x23, x28, x20, lsl #4",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcvt s5, d3",
|
|
"str s5, [x8, #56]",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcvt s5, d4",
|
|
"str s5, [x8, #44]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"add x12, x28, x20, lsl #4",
|
|
"ldr d5, [x12, #1056]",
|
|
"strb wzr, [x28, #1049]",
|
|
"fcvt s6, d5",
|
|
"str s6, [x8, #40]",
|
|
"str d2, [x8]",
|
|
"add w20, w20, #0x1 (1)",
|
|
"and w20, w20, #0x7",
|
|
"mov w13, #0x24",
|
|
"movk w13, #0x1, lsl #16",
|
|
"str w13, [x8, #-4]!",
|
|
"strb w20, [x28, #1051]",
|
|
"str d3, [x21, #1056]",
|
|
"str d4, [x22, #1056]",
|
|
"str d5, [x23, #1056]",
|
|
"str d2, [x12, #1056]",
|
|
"strb wzr, [x28, #1202]"
|
|
]
|
|
},
|
|
"Block10": {
|
|
"x86InstructionCount": 125,
|
|
"ExpectedInstructionCount": 17,
|
|
"x86Insts": [
|
|
"push esi",
|
|
"push ebx",
|
|
"sub esp,0xa4",
|
|
"mov ebx,dword [esp + 0xb0]",
|
|
"lea esi,[esp + 0x18]",
|
|
"mov eax,gs:[0x14]",
|
|
"mov dword [esp + 0x9c],eax",
|
|
"xor eax,eax",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x18]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x1c]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x20]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x24]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x28]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x2c]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x30]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x34]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x38]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x3c]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x40]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x44]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x48]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x4c]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x50]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x54]",
|
|
"call 0x00018ad0",
|
|
"mov dword [esp + 0x58],eax",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x7c]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x80]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x84]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x88]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x8c]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x90]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x94]",
|
|
"call 0x00019090",
|
|
"mov eax,dword [ebx + 0x5869c]",
|
|
"mov dword [esp],eax",
|
|
"fstp dword [esp + 0x98]",
|
|
"call 0x00019700",
|
|
"mov edx,0x1f",
|
|
"mov dword [esp + 0x8],edx",
|
|
"mov dword [esp + 0x4],eax",
|
|
"lea eax,[esp + 0x5c]",
|
|
"mov dword [esp],eax",
|
|
"call 0x0006d0dc",
|
|
"mov eax,dword [ebx + 0x130]",
|
|
"mov byte [esp + 0x7b],0x0",
|
|
"mov edx,dword [eax]",
|
|
"mov dword [esp],eax",
|
|
"mov dword [esp + 0x4],esi",
|
|
"call dword [edx + 0xc4]",
|
|
"mov eax,dword [esp + 0x9c]",
|
|
"xor eax,dword gs:[0x14]"
|
|
],
|
|
"ExpectedArm64ASM": [
|
|
"stp w6, w10, [x8, #-8]!",
|
|
"sub w8, w8, #0xa4 (164)",
|
|
"ldr w6, [x8, #176]",
|
|
"add w10, w8, #0x18 (24)",
|
|
"ldr w20, [x28, #992]",
|
|
"ldr w4, [x20, #20]",
|
|
"str w4, [x8, #156]",
|
|
"subs w26, w4, w4",
|
|
"mov w4, #0x0",
|
|
"mov w20, #0x869c",
|
|
"movk w20, #0x5, lsl #16",
|
|
"add w20, w6, w20",
|
|
"ldr w4, [x20]",
|
|
"str w4, [x8]",
|
|
"mov w20, #0x30",
|
|
"movk w20, #0x1, lsl #16",
|
|
"str w20, [x8, #-4]!"
|
|
]
|
|
}
|
|
}
|
|
}
|