mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 09:00:17 +02:00
120 lines
2.7 KiB
JSON
120 lines
2.7 KiB
JSON
{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [
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"SVE128",
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"SVE256",
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"FLAGM",
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"FLAGM2"
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],
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"DisabledHostFeatures": [
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"FCMA",
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"RPRES",
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"AFP"
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],
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"BinaryCacheVersion": 12
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},
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"Instructions": {
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"vucomiss xmm0, xmm1": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b00 0x2e 128-bit"
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],
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"ExpectedArm64ASM": [
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"fcmp s16, s17",
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"cset x26, vc",
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"mov w27, #0x0",
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"axflag"
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]
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},
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"vucomisd xmm0, xmm1": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b01 0x2e 128-bit"
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],
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"ExpectedArm64ASM": [
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"fcmp d16, d17",
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"cset x26, vc",
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"mov w27, #0x0",
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"axflag"
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]
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},
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"vcomiss xmm0, xmm1": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b00 0x2f 128-bit"
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],
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"ExpectedArm64ASM": [
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"fcmp s16, s17",
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"cset x26, vc",
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"mov w27, #0x0",
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"axflag"
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]
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},
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"vcomisd xmm0, xmm1": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b01 0x2f 128-bit"
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],
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"ExpectedArm64ASM": [
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"fcmp d16, d17",
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"cset x26, vc",
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"mov w27, #0x0",
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"axflag"
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]
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},
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"vpmovmskb rax, xmm0": {
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"ExpectedInstructionCount": 7,
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"Comment": [
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"Map 1 0b01 0xd7 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr q2, [x28, #3408]",
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"cmlt v3.16b, v16.16b, #0",
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"and v2.16b, v3.16b, v2.16b",
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"addp v2.16b, v2.16b, v2.16b",
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"addp v2.8b, v2.8b, v2.8b",
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"addp v2.8b, v2.8b, v2.8b",
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"umov w4, v2.h[0]"
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]
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},
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"vpmovmskb rax, ymm0": {
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"ExpectedInstructionCount": 17,
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"Comment": [
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"Map 1 0b01 0xd7 256-bit"
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],
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"ExpectedArm64ASM": [
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"ldr x0, [x28, #2536]",
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"ld1b {z2.b}, p7/z, [x0]",
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"mrs x0, nzcv",
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"mov z0.d, #0",
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"cmplt p0.b, p7/z, z16.b, #0",
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"not z0.b, p0/m, z16.b",
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"orr z0.b, p0/m, z0.b, z16.b",
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"mov z3.d, z0.d",
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"msr nzcv, x0",
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"and z2.d, z3.d, z2.d",
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"addp z2.b, p7/m, z2.b, z2.b",
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"uzp1 z2.b, z2.b, z2.b",
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"uzp2 z1.b, z2.b, z2.b",
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"splice z2.d, p6, z2.d, z1.d",
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"addp v2.16b, v2.16b, v2.16b",
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"addp v2.8b, v2.8b, v2.8b",
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"mov w4, v2.s[0]"
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]
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},
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"vmaskmovdqu xmm0, xmm1": {
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"ExpectedInstructionCount": 4,
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"Comment": [
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"Map 1 0b01 0xf7 128-bit"
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],
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"ExpectedArm64ASM": [
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"cmlt v2.16b, v17.16b, #0",
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"ldr q3, [x11]",
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"bsl v2.16b, v16.16b, v3.16b",
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"str q2, [x11]"
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]
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}
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}
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}
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