mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 08:00:15 +02:00
129 lines
3.0 KiB
JSON
129 lines
3.0 KiB
JSON
{
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"Features": {
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"Bitness": 64,
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"EnabledHostFeatures": [
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"FLAGM",
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"FLAGM2"
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],
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"DisabledHostFeatures": [
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"SVE128",
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"SVE256",
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"RPRES",
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"AFP",
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"CSSC"
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],
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"BinaryCacheVersion": 12
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},
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"Instructions": {
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"popcnt ax, bx": {
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"ExpectedInstructionCount": 9,
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"Comment": "0xf3 0x0f 0xb8",
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"ExpectedArm64ASM": [
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"uxth w20, w6",
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"fmov s0, w20",
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"cnt v0.8b, v0.8b",
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"addp v0.8b, v0.8b, v0.8b",
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"umov w20, v0.b[0]",
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"bfxil x4, x20, #0, #16",
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"mov w27, #0x0",
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"cmp w20, #0x0 (0)",
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"mov w26, #0x1"
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]
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},
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"popcnt eax, ebx": {
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"ExpectedInstructionCount": 7,
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"Comment": "0xf3 0x0f 0xb8",
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"ExpectedArm64ASM": [
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"fmov s0, w6",
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"cnt v0.8b, v0.8b",
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"addv b0, v0.8b",
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"umov w4, v0.b[0]",
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"mov w27, #0x0",
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"cmp w4, #0x0 (0)",
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"mov w26, #0x1"
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]
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},
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"popcnt rax, rbx": {
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"ExpectedInstructionCount": 7,
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"Comment": "0xf3 0x0f 0xb8",
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"ExpectedArm64ASM": [
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"fmov d0, x6",
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"cnt v0.8b, v0.8b",
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"addv b0, v0.8b",
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"umov w4, v0.b[0]",
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"mov w27, #0x0",
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"cmp w4, #0x0 (0)",
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"mov w26, #0x1"
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]
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},
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"tzcnt ax, bx": {
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"ExpectedInstructionCount": 7,
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"Comment": "0xf3 0x0f 0xbc",
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"ExpectedArm64ASM": [
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"rbit w20, w6",
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"orr w20, w20, #0x8000",
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"clz w20, w20",
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"bfxil x4, x20, #0, #16",
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"cmn wzr, w20, lsl #16",
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"eor x20, x20, #0x10",
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"rmif x20, #3, #nzCv"
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]
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},
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"tzcnt eax, ebx": {
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"ExpectedInstructionCount": 5,
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"Comment": "0xf3 0x0f 0xbc",
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"ExpectedArm64ASM": [
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"rbit w4, w6",
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"clz w4, w4",
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"cmp w4, #0x0 (0)",
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"eor x20, x4, #0x20",
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"rmif x20, #4, #nzCv"
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]
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},
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"tzcnt rax, rbx": {
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"ExpectedInstructionCount": 5,
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"Comment": "0xf3 0x0f 0xbc",
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"ExpectedArm64ASM": [
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"rbit x4, x6",
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"clz x4, x4",
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"cmp x4, #0x0 (0)",
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"eor x20, x4, #0x40",
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"rmif x20, #5, #nzCv"
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]
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},
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"lzcnt ax, bx": {
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"ExpectedInstructionCount": 7,
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"Comment": "0xf3 0x0f 0xbd",
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"ExpectedArm64ASM": [
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"lsl w20, w6, #16",
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"orr w20, w20, #0x8000",
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"clz w20, w20",
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"bfxil x4, x20, #0, #16",
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"cmn wzr, w20, lsl #16",
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"eor x20, x20, #0x10",
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"rmif x20, #3, #nzCv"
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]
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},
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"lzcnt eax, ebx": {
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"ExpectedInstructionCount": 4,
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"Comment": "0xf3 0x0f 0xbd",
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"ExpectedArm64ASM": [
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"clz w4, w6",
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"cmp w4, #0x0 (0)",
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"eor x20, x4, #0x20",
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"rmif x20, #4, #nzCv"
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]
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},
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"lzcnt rax, rbx": {
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"ExpectedInstructionCount": 4,
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"Comment": "0xf3 0x0f 0xbd",
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"ExpectedArm64ASM": [
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"clz x4, x6",
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"cmp x4, #0x0 (0)",
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"eor x20, x4, #0x40",
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"rmif x20, #5, #nzCv"
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]
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}
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}
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}
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