mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 09:00:17 +02:00
1639 lines
40 KiB
JSON
1639 lines
40 KiB
JSON
{
|
|
"Features": {
|
|
"Bitness": 64,
|
|
"EnabledHostFeatures": [
|
|
"FLAGM",
|
|
"FLAGM2"
|
|
],
|
|
"DisabledHostFeatures": [
|
|
"SVE128",
|
|
"SVE256",
|
|
"RPRES",
|
|
"AFP"
|
|
],
|
|
"BinaryCacheVersion": 12
|
|
},
|
|
"Instructions": {
|
|
"ucomiss xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0x2e",
|
|
"ExpectedArm64ASM": [
|
|
"fcmp s16, s17",
|
|
"cset x26, vc",
|
|
"mov w27, #0x0",
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|
"axflag"
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|
]
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|
},
|
|
"comiss xmm0, xmm1": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0x2f",
|
|
"ExpectedArm64ASM": [
|
|
"fcmp s16, s17",
|
|
"cset x26, vc",
|
|
"mov w27, #0x0",
|
|
"axflag"
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|
]
|
|
},
|
|
"cmovo ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x40",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, vs",
|
|
"bfxil x4, x20, #0, #16"
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|
]
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|
},
|
|
"cmovo eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x40",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, vs"
|
|
]
|
|
},
|
|
"cmovo rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x40",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, vs"
|
|
]
|
|
},
|
|
"cmovno ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x41",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, vc",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovno eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x41",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, vc"
|
|
]
|
|
},
|
|
"cmovno rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x41",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, vc"
|
|
]
|
|
},
|
|
"cmovb ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x42",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, lo",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovb eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x42",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, lo"
|
|
]
|
|
},
|
|
"cmovb rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x42",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, lo"
|
|
]
|
|
},
|
|
"cmovnb ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x43",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, hs",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovnb eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x43",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, hs"
|
|
]
|
|
},
|
|
"cmovnb rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x43",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, hs"
|
|
]
|
|
},
|
|
"cmovz ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x44",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, eq",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovz eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x44",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, eq"
|
|
]
|
|
},
|
|
"cmovz rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x44",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, eq"
|
|
]
|
|
},
|
|
"cmovnz ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x45",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, ne",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovnz eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x45",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, ne"
|
|
]
|
|
},
|
|
"cmovnz rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x45",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, ne"
|
|
]
|
|
},
|
|
"cmovbe ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x46",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, ls",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovbe eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x46",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, ls"
|
|
]
|
|
},
|
|
"cmovbe rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x46",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, ls"
|
|
]
|
|
},
|
|
"cmovnbe ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x47",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, hi",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovnbe eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x47",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, hi"
|
|
]
|
|
},
|
|
"cmovnbe rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x47",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, hi"
|
|
]
|
|
},
|
|
"cmovs ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x48",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, mi",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovs eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x48",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, mi"
|
|
]
|
|
},
|
|
"cmovs rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x48",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, mi"
|
|
]
|
|
},
|
|
"cmovns ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x49",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, pl",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovns eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x49",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, pl"
|
|
]
|
|
},
|
|
"cmovns rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x49",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, pl"
|
|
]
|
|
},
|
|
"cmovpe ax, bx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x0f 0x4a",
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"mrs x21, nzcv",
|
|
"tst w20, #0x1",
|
|
"csel w20, w6, w4, ne",
|
|
"bfxil x4, x20, #0, #16",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"cmovpe eax, ebx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x0f 0x4a",
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"mrs x21, nzcv",
|
|
"tst w20, #0x1",
|
|
"csel w4, w6, w4, ne",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"cmovpe rax, rbx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x0f 0x4a",
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"mrs x21, nzcv",
|
|
"tst w20, #0x1",
|
|
"csel x4, x6, x4, ne",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"cmovnp ax, bx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x0f 0x4b",
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"mrs x21, nzcv",
|
|
"tst w20, #0x1",
|
|
"csel w20, w6, w4, ne",
|
|
"bfxil x4, x20, #0, #16",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"cmovnp eax, ebx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x0f 0x4b",
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"mrs x21, nzcv",
|
|
"tst w20, #0x1",
|
|
"csel w4, w6, w4, ne",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"cmovnp rax, rbx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x0f 0x4b",
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"mrs x21, nzcv",
|
|
"tst w20, #0x1",
|
|
"csel x4, x6, x4, ne",
|
|
"msr nzcv, x21"
|
|
]
|
|
},
|
|
"cmovl ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x4c",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, lt",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovl eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x4c",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, lt"
|
|
]
|
|
},
|
|
"cmovl rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x4c",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, lt"
|
|
]
|
|
},
|
|
"cmovnl ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x4d",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, ge",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovnl eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x4d",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, ge"
|
|
]
|
|
},
|
|
"cmovnl rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x4d",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, ge"
|
|
]
|
|
},
|
|
"cmovle ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x4e",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, le",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovle eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x4e",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, le"
|
|
]
|
|
},
|
|
"cmovle rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x4e",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, le"
|
|
]
|
|
},
|
|
"cmovnle ax, bx": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x4f",
|
|
"ExpectedArm64ASM": [
|
|
"csel w20, w6, w4, gt",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmovnle eax, ebx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x4f",
|
|
"ExpectedArm64ASM": [
|
|
"csel w4, w6, w4, gt"
|
|
]
|
|
},
|
|
"cmovnle rax, rbx": {
|
|
"ExpectedInstructionCount": 1,
|
|
"Comment": "0x0f 0x4f",
|
|
"ExpectedArm64ASM": [
|
|
"csel x4, x6, x4, gt"
|
|
]
|
|
},
|
|
"seto al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x90",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, vs",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setno al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x91",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, vc",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setb al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x92",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, lo",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setnb al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x93",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, hs",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setz al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x94",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, eq",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setnz al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x95",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, ne",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setbe al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x96",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, ls",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setnbe al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x97",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, hi",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"sets al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x98",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, mi",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setns al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x99",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, pl",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setpe al": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0x9a",
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eon w20, w0, w0, lsr #1",
|
|
"and w20, w20, #0x1",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setnp al": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0x9b",
|
|
"ExpectedArm64ASM": [
|
|
"eor w0, w26, w26, lsr #4",
|
|
"eor w0, w0, w0, lsr #2",
|
|
"eor w20, w0, w0, lsr #1",
|
|
"and w20, w20, #0x1",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setl al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x9c",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, lt",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setnl al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x9d",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, ge",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setle al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x9e",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, le",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"setnle al": {
|
|
"ExpectedInstructionCount": 2,
|
|
"Comment": "0x0f 0x9f",
|
|
"ExpectedArm64ASM": [
|
|
"cset x20, gt",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"bt ax, bx": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0xa3",
|
|
"ExpectedArm64ASM": [
|
|
"and x20, x6, #0xf",
|
|
"lsr w20, w4, w20",
|
|
"rmif x20, #63, #nzCv",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"bt [rax], bx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x0f 0xa3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #13",
|
|
"ldrb w21, [x4, x21, sxtx]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"bt eax, ebx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x0f 0xa3",
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w4, w6",
|
|
"rmif x20, #63, #nzCv",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"bt [rax], ebx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x0f 0xa3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #29",
|
|
"ldrb w21, [x4, x21, sxtx]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"bt rax, rbx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x0f 0xa3",
|
|
"ExpectedArm64ASM": [
|
|
"lsr x20, x4, x6",
|
|
"rmif x20, #63, #nzCv",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"bt [rax], rbx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x0f 0xa3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"asr x21, x6, #3",
|
|
"ldrb w21, [x4, x21, sxtx]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"shld ax, bx, 1": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w6",
|
|
"uxth w21, w4",
|
|
"lsl x22, x21, #1",
|
|
"lsr w20, w20, #15",
|
|
"orr x26, x22, x20",
|
|
"cmn wzr, w26, lsl #16",
|
|
"eor x20, x21, #0x8000",
|
|
"rmif x20, #14, #nzCv",
|
|
"eor w20, w26, w21",
|
|
"rmif x20, #15, #nzcV",
|
|
"bfxil x4, x26, #0, #16"
|
|
]
|
|
},
|
|
"shld ax, bx, 15": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w6",
|
|
"uxth w21, w4",
|
|
"lsl x22, x21, #15",
|
|
"lsr w20, w20, #1",
|
|
"orr x26, x22, x20",
|
|
"cmn wzr, w26, lsl #16",
|
|
"eor x20, x21, #0x2",
|
|
"rmif x20, #0, #nzCv",
|
|
"bfxil x4, x26, #0, #16"
|
|
]
|
|
},
|
|
"shld ax, bx, 16": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w6",
|
|
"uxth w21, w4",
|
|
"lsl x22, x21, #16",
|
|
"orr x26, x22, x20",
|
|
"cmn wzr, w26, lsl #16",
|
|
"eor x20, x21, #0x1",
|
|
"rmif x20, #63, #nzCv",
|
|
"bfxil x4, x26, #0, #16"
|
|
]
|
|
},
|
|
"shld ax, bx, 31": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w6",
|
|
"uxth w21, w4",
|
|
"lsl x21, x21, #31",
|
|
"lsr w20, w20, #17",
|
|
"orr x26, x21, x20",
|
|
"cmn wzr, w26, lsl #16",
|
|
"bfxil x4, x26, #0, #16",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"shld eax, ebx, 1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"extr w26, w4, w6, #31",
|
|
"cmp w26, #0x0 (0)",
|
|
"eor x20, x4, #0x80000000",
|
|
"rmif x20, #30, #nzCv",
|
|
"eor w20, w26, w4",
|
|
"rmif x20, #31, #nzcV",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"shld eax, ebx, 15": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"extr w26, w4, w6, #17",
|
|
"cmp w26, #0x0 (0)",
|
|
"eor x20, x4, #0x20000",
|
|
"rmif x20, #16, #nzCv",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"shld eax, ebx, 16": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"extr w26, w4, w6, #16",
|
|
"cmp w26, #0x0 (0)",
|
|
"eor x20, x4, #0x10000",
|
|
"rmif x20, #15, #nzCv",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"shld eax, ebx, 31": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"extr w26, w4, w6, #1",
|
|
"cmp w26, #0x0 (0)",
|
|
"eor x20, x4, #0x2",
|
|
"rmif x20, #0, #nzCv",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"shld rax, rbx, 1": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"extr x26, x4, x6, #63",
|
|
"cmp x26, #0x0 (0)",
|
|
"eor x20, x4, #0x8000000000000000",
|
|
"rmif x20, #62, #nzCv",
|
|
"eor x20, x26, x4",
|
|
"rmif x20, #63, #nzcV",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"shld rax, rbx, 15": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"extr x26, x4, x6, #49",
|
|
"cmp x26, #0x0 (0)",
|
|
"eor x20, x4, #0x2000000000000",
|
|
"rmif x20, #48, #nzCv",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"shld rax, rbx, 32": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"extr x26, x4, x6, #32",
|
|
"cmp x26, #0x0 (0)",
|
|
"eor x20, x4, #0x100000000",
|
|
"rmif x20, #31, #nzCv",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"shld rax, rbx, 63": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xac",
|
|
"ExpectedArm64ASM": [
|
|
"extr x26, x4, x6, #1",
|
|
"cmp x26, #0x0 (0)",
|
|
"eor x20, x4, #0x2",
|
|
"rmif x20, #0, #nzCv",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"shld ax, bx, cl": {
|
|
"ExpectedInstructionCount": 21,
|
|
"Comment": "0x0f 0xad",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w6",
|
|
"uxth w21, w4",
|
|
"and x22, x7, #0x1f",
|
|
"mov w23, #0x10",
|
|
"sub x23, x23, x22",
|
|
"lsl x24, x21, x22",
|
|
"lsr w20, w20, w23",
|
|
"orr x20, x24, x20",
|
|
"mrs x23, nzcv",
|
|
"cmp x22, #0x0 (0)",
|
|
"csel x20, x21, x20, eq",
|
|
"msr nzcv, x23",
|
|
"and w0, w22, #0x1f",
|
|
"cbz w0, #+0x1c",
|
|
"cmn wzr, w20, lsl #16",
|
|
"mov x26, x20",
|
|
"mvn x0, x20",
|
|
"eor w2, w21, w20",
|
|
"rmif x0, #15, #nzCv",
|
|
"rmif x2, #15, #nzcV",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"shld eax, ebx, cl": {
|
|
"ExpectedInstructionCount": 20,
|
|
"Comment": "0x0f 0xad",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"and x21, x7, #0x1f",
|
|
"neg x22, x21",
|
|
"lsl x23, x20, x21",
|
|
"lsr w22, w6, w22",
|
|
"orr x22, x23, x22",
|
|
"mrs x23, nzcv",
|
|
"cmp x21, #0x0 (0)",
|
|
"csel x22, x20, x22, eq",
|
|
"msr nzcv, x23",
|
|
"and w0, w21, #0x1f",
|
|
"cbz w0, #+0x20",
|
|
"ands w26, w22, w22",
|
|
"neg w0, w21",
|
|
"lsr w0, w20, w0",
|
|
"mvn x0, x0",
|
|
"eor w2, w20, w22",
|
|
"rmif x0, #63, #nzCv",
|
|
"rmif x2, #31, #nzcV",
|
|
"mov w4, w22"
|
|
]
|
|
},
|
|
"shld rax, rbx, cl": {
|
|
"ExpectedInstructionCount": 19,
|
|
"Comment": "0x0f 0xad",
|
|
"ExpectedArm64ASM": [
|
|
"and x20, x7, #0x3f",
|
|
"neg x21, x20",
|
|
"lsl x22, x4, x20",
|
|
"lsr x21, x6, x21",
|
|
"orr x21, x22, x21",
|
|
"mrs x22, nzcv",
|
|
"cmp x20, #0x0 (0)",
|
|
"csel x21, x4, x21, eq",
|
|
"msr nzcv, x22",
|
|
"and w0, w20, #0x3f",
|
|
"cbz x0, #+0x20",
|
|
"ands x26, x21, x21",
|
|
"neg x0, x20",
|
|
"lsr x0, x4, x0",
|
|
"mvn x0, x0",
|
|
"eor x2, x4, x21",
|
|
"rmif x0, #63, #nzCv",
|
|
"rmif x2, #63, #nzcV",
|
|
"mov x4, x21"
|
|
]
|
|
},
|
|
"bts ax, bx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x0f 0xab",
|
|
"ExpectedArm64ASM": [
|
|
"and x20, x6, #0xf",
|
|
"lsr w21, w4, w20",
|
|
"rmif x21, #63, #nzCv",
|
|
"mov w21, #0x1",
|
|
"lsl w20, w21, w20",
|
|
"orr w20, w4, w20",
|
|
"bfxil x4, x20, #0, #16",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"bts [rax], bx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x0f 0xab",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #13",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"ldrb w23, [x4, x21, sxtx]",
|
|
"orr x22, x23, x22",
|
|
"strb w22, [x4, x21, sxtx]",
|
|
"lsr w20, w23, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"bts eax, ebx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x0f 0xab",
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w4, w6",
|
|
"rmif x20, #63, #nzCv",
|
|
"mov w20, #0x1",
|
|
"lsl w20, w20, w6",
|
|
"orr w4, w4, w20",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"bts [rax], ebx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x0f 0xab",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #29",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"ldrb w23, [x4, x21, sxtx]",
|
|
"orr x22, x23, x22",
|
|
"strb w22, [x4, x21, sxtx]",
|
|
"lsr w20, w23, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"bts rax, rbx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x0f 0xab",
|
|
"ExpectedArm64ASM": [
|
|
"lsr x20, x4, x6",
|
|
"rmif x20, #63, #nzCv",
|
|
"mov w20, #0x1",
|
|
"lsl x20, x20, x6",
|
|
"orr x4, x4, x20",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"bts [rax], rbx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x0f 0xab",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"asr x21, x6, #3",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"ldrb w23, [x4, x21, sxtx]",
|
|
"orr x22, x23, x22",
|
|
"strb w22, [x4, x21, sxtx]",
|
|
"lsr w20, w23, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"lock bts [rax], bx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #13",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"add x21, x4, x21",
|
|
"ldsetalb w22, w21, [x21]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"lock bts [rax], ebx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #29",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"add x21, x4, x21",
|
|
"ldsetalb w22, w21, [x21]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"lock bts [rax], rbx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"asr x21, x6, #3",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"add x21, x4, x21",
|
|
"ldsetalb w22, w21, [x21]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"imul ax, bx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x0f 0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"sxth x20, w4",
|
|
"sxth x21, w6",
|
|
"mul x20, x20, x21",
|
|
"sbfx x21, x20, #16, #16",
|
|
"bfxil x4, x20, #0, #16",
|
|
"sbfx x20, x20, #15, #1",
|
|
"cmp x21, x20",
|
|
"ccmp xzr, #0, #nzcV, eq"
|
|
]
|
|
},
|
|
"imul eax, ebx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x0f 0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"smull x20, w4, w6",
|
|
"asr x20, x20, #32",
|
|
"mul w4, w4, w6",
|
|
"sbfx x21, x4, #31, #1",
|
|
"cmp x20, x21",
|
|
"ccmp xzr, #0, #nzcV, eq"
|
|
]
|
|
},
|
|
"imul rax, rbx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"smulh x20, x4, x6",
|
|
"mul x4, x4, x6",
|
|
"asr x21, x4, #63",
|
|
"cmp x20, x21",
|
|
"ccmp xzr, #0, #nzcV, eq"
|
|
]
|
|
},
|
|
"imul rsi, rax, 0xffffffff8646c299": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x0f 0xaf",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, #0xffffffffffffc299",
|
|
"movk x20, #0x8646, lsl #16",
|
|
"smulh x21, x4, x20",
|
|
"mul x10, x4, x20",
|
|
"asr x20, x10, #63",
|
|
"cmp x21, x20",
|
|
"ccmp xzr, #0, #nzcV, eq"
|
|
]
|
|
},
|
|
"cmpxchg cl, bl": {
|
|
"ExpectedInstructionCount": 7,
|
|
"ExpectedArm64ASM": [
|
|
"eor x27, x4, x7",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w7, lsl #24",
|
|
"sub w26, w4, w7",
|
|
"bfxil x4, x7, #0, #8",
|
|
"csel x20, x6, x7, eq",
|
|
"bfxil x7, x20, #0, #8"
|
|
]
|
|
},
|
|
"cmpxchg cx, bx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"ExpectedArm64ASM": [
|
|
"eor x27, x4, x7",
|
|
"lsl w0, w4, #16",
|
|
"cmp w0, w7, lsl #16",
|
|
"sub w26, w4, w7",
|
|
"bfxil x4, x7, #0, #16",
|
|
"csel x20, x6, x7, eq",
|
|
"bfxil x7, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmpxchg ecx, ebx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w7",
|
|
"eor x27, x4, x20",
|
|
"subs w26, w4, w20",
|
|
"csel x4, x4, x20, eq",
|
|
"mov w20, w6",
|
|
"csel x7, x20, x7, eq"
|
|
]
|
|
},
|
|
"cmpxchg rcx, rbx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"ExpectedArm64ASM": [
|
|
"eor x27, x4, x7",
|
|
"subs x26, x4, x7",
|
|
"csel x20, x6, x7, eq",
|
|
"mov x21, x7",
|
|
"mov x7, x20",
|
|
"mov x4, x21"
|
|
]
|
|
},
|
|
"cmpxchg [rcx], rbx": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0xb1",
|
|
"ExpectedArm64ASM": [
|
|
"mov x20, x4",
|
|
"casal x4, x6, [x7]",
|
|
"eor x27, x20, x4",
|
|
"subs x26, x20, x4"
|
|
]
|
|
},
|
|
"cmpxchg al, bl": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xb0",
|
|
"ExpectedArm64ASM": [
|
|
"mov w27, #0x0",
|
|
"lsl w0, w4, #24",
|
|
"cmp w0, w4, lsl #24",
|
|
"sub w26, w4, w4",
|
|
"bfxil x4, x6, #0, #8"
|
|
]
|
|
},
|
|
"cmpxchg [rcx], bl": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x0f 0xb0",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w6",
|
|
"uxtb x21, w4",
|
|
"mov w1, w4",
|
|
"casalb w1, w20, [x7]",
|
|
"mov w20, w1",
|
|
"eor x27, x21, x20",
|
|
"lsl w0, w21, #24",
|
|
"cmp w0, w20, lsl #24",
|
|
"sub w26, w21, w20",
|
|
"bfxil x4, x20, #0, #8"
|
|
]
|
|
},
|
|
"cmpxchg ax, bx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xb1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w27, #0x0",
|
|
"lsl w0, w4, #16",
|
|
"cmp w0, w4, lsl #16",
|
|
"sub w26, w4, w4",
|
|
"bfxil x4, x6, #0, #16"
|
|
]
|
|
},
|
|
"cmpxchg [rcx], bx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x0f 0xb1",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w6",
|
|
"uxth x21, w4",
|
|
"mov w1, w4",
|
|
"casalh w1, w20, [x7]",
|
|
"mov w20, w1",
|
|
"eor x27, x21, x20",
|
|
"lsl w0, w21, #16",
|
|
"cmp w0, w20, lsl #16",
|
|
"sub w26, w21, w20",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"cmpxchg eax, ebx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x0f 0xb1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w27, #0x0",
|
|
"subs w26, w4, w4",
|
|
"mov w4, w6"
|
|
]
|
|
},
|
|
"cmpxchg [rcx], ebx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x0f 0xb1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w6",
|
|
"mov w21, w4",
|
|
"mov w1, w4",
|
|
"casal w1, w20, [x7]",
|
|
"mov w20, w1",
|
|
"eor x27, x21, x20",
|
|
"subs w26, w21, w20",
|
|
"csel x4, x4, x20, eq"
|
|
]
|
|
},
|
|
"cmpxchg rax, rbx": {
|
|
"ExpectedInstructionCount": 3,
|
|
"Comment": "0x0f 0xb1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w27, #0x0",
|
|
"subs x26, x4, x4",
|
|
"mov x4, x6"
|
|
]
|
|
},
|
|
"btr ax, bx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"and x20, x6, #0xf",
|
|
"lsr w21, w4, w20",
|
|
"rmif x21, #63, #nzCv",
|
|
"mov w21, #0x1",
|
|
"lsl w20, w21, w20",
|
|
"bic w20, w4, w20",
|
|
"bfxil x4, x20, #0, #16",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"btr [rax], bx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #13",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"ldrb w23, [x4, x21, sxtx]",
|
|
"bic x22, x23, x22",
|
|
"strb w22, [x4, x21, sxtx]",
|
|
"lsr w20, w23, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"btr eax, ebx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"lsr w20, w4, w6",
|
|
"rmif x20, #63, #nzCv",
|
|
"mov w20, #0x1",
|
|
"lsl w20, w20, w6",
|
|
"bic w4, w4, w20",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"btr [rax], ebx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #29",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"ldrb w23, [x4, x21, sxtx]",
|
|
"bic x22, x23, x22",
|
|
"strb w22, [x4, x21, sxtx]",
|
|
"lsr w20, w23, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"btr rax, rbx": {
|
|
"ExpectedInstructionCount": 6,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"lsr x20, x4, x6",
|
|
"rmif x20, #63, #nzCv",
|
|
"mov w20, #0x1",
|
|
"lsl x20, x20, x6",
|
|
"bic x4, x4, x20",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"btr [rax], rbx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"asr x21, x6, #3",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"ldrb w23, [x4, x21, sxtx]",
|
|
"bic x22, x23, x22",
|
|
"strb w22, [x4, x21, sxtx]",
|
|
"lsr w20, w23, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"lock btr [rax], bx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #13",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"add x21, x4, x21",
|
|
"ldclralb w22, w21, [x21]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"lock btr [rax], ebx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #29",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"add x21, x4, x21",
|
|
"ldclralb w22, w21, [x21]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"lock btr [rax], rbx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"asr x21, x6, #3",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"add x21, x4, x21",
|
|
"ldclralb w22, w21, [x21]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"btc ax, bx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x0f 0xbb",
|
|
"ExpectedArm64ASM": [
|
|
"and x20, x6, #0xf",
|
|
"mov w21, #0x1",
|
|
"lsl w21, w21, w20",
|
|
"eor w21, w4, w21",
|
|
"lsr w20, w21, w20",
|
|
"rmif x20, #63, #nzCv",
|
|
"bfxil x4, x21, #0, #16"
|
|
]
|
|
},
|
|
"btc [rax], bx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x0f 0xbb",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #13",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"ldrb w23, [x4, x21, sxtx]",
|
|
"eor x22, x23, x22",
|
|
"strb w22, [x4, x21, sxtx]",
|
|
"lsr w20, w23, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"btc eax, ebx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xbb",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"lsl w20, w20, w6",
|
|
"eor w4, w4, w20",
|
|
"lsr w20, w4, w6",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"btc [rax], ebx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x0f 0xbb",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #29",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"ldrb w23, [x4, x21, sxtx]",
|
|
"eor x22, x23, x22",
|
|
"strb w22, [x4, x21, sxtx]",
|
|
"lsr w20, w23, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"btc rax, rbx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xbb",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, #0x1",
|
|
"lsl x20, x20, x6",
|
|
"eor x4, x4, x20",
|
|
"lsr x20, x4, x6",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"btc [rax], rbx": {
|
|
"ExpectedInstructionCount": 10,
|
|
"Comment": "0x0f 0xbb",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"asr x21, x6, #3",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"ldrb w23, [x4, x21, sxtx]",
|
|
"eor x22, x23, x22",
|
|
"strb w22, [x4, x21, sxtx]",
|
|
"lsr w20, w23, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"lock btc [rax], bx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #13",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"add x21, x4, x21",
|
|
"ldeoralb w22, w21, [x21]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"lock btc [rax], ebx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"sbfx x21, x6, #3, #29",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"add x21, x4, x21",
|
|
"ldeoralb w22, w21, [x21]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"lock btc [rax], rbx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xb3",
|
|
"ExpectedArm64ASM": [
|
|
"ubfx x20, x6, #0, #3",
|
|
"asr x21, x6, #3",
|
|
"mov w22, #0x1",
|
|
"lsl x22, x22, x20",
|
|
"add x21, x4, x21",
|
|
"ldeoralb w22, w21, [x21]",
|
|
"lsr w20, w21, w20",
|
|
"eor x20, x20, #0x1",
|
|
"rmif x20, #63, #nzCv"
|
|
]
|
|
},
|
|
"bsf ax, bx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xbc",
|
|
"ExpectedArm64ASM": [
|
|
"rbit w0, w6",
|
|
"clz w20, w0",
|
|
"tst w6, #0xffff",
|
|
"csel x20, x4, x20, eq",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"bsf eax, ebx": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0xbc",
|
|
"ExpectedArm64ASM": [
|
|
"rbit w0, w6",
|
|
"clz w20, w0",
|
|
"tst w6, w6",
|
|
"csel x4, x4, x20, eq"
|
|
]
|
|
},
|
|
"bsf rax, rbx": {
|
|
"ExpectedInstructionCount": 4,
|
|
"Comment": "0x0f 0xbc",
|
|
"ExpectedArm64ASM": [
|
|
"rbit x0, x6",
|
|
"clz x20, x0",
|
|
"tst x6, x6",
|
|
"csel x4, x4, x20, eq"
|
|
]
|
|
},
|
|
"bsr ax, bx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x0f 0xbd",
|
|
"ExpectedArm64ASM": [
|
|
"mov x0, #0xf",
|
|
"lsl w20, w6, #16",
|
|
"clz w20, w20",
|
|
"sub x20, x0, x20",
|
|
"tst w6, #0xffff",
|
|
"csel x20, x4, x20, eq",
|
|
"bfxil x4, x20, #0, #16"
|
|
]
|
|
},
|
|
"bsr eax, ebx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xbd",
|
|
"ExpectedArm64ASM": [
|
|
"mov x0, #0x1f",
|
|
"clz w20, w6",
|
|
"sub x20, x0, x20",
|
|
"tst w6, w6",
|
|
"csel x4, x4, x20, eq"
|
|
]
|
|
},
|
|
"bsr rax, rbx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xbd",
|
|
"ExpectedArm64ASM": [
|
|
"mov x0, #0x3f",
|
|
"clz x20, x6",
|
|
"sub x20, x0, x20",
|
|
"tst x6, x6",
|
|
"csel x4, x4, x20, eq"
|
|
]
|
|
},
|
|
"xadd al, bl": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xc0",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w4",
|
|
"uxtb w21, w6",
|
|
"eor x27, x20, x21",
|
|
"lsl w0, w20, #24",
|
|
"cmn w0, w21, lsl #24",
|
|
"add w26, w20, w21",
|
|
"bfxil x6, x20, #0, #8",
|
|
"bfxil x4, x26, #0, #8",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"xadd [rax], bl": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x0f 0xc0",
|
|
"ExpectedArm64ASM": [
|
|
"uxtb w20, w6",
|
|
"ldaddalb w20, w21, [x4]",
|
|
"eor x27, x21, x20",
|
|
"lsl w0, w21, #24",
|
|
"cmn w0, w20, lsl #24",
|
|
"add w26, w21, w20",
|
|
"bfxil x6, x21, #0, #8",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"xadd ax, bx": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xc1",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w4",
|
|
"uxth w21, w6",
|
|
"eor x27, x20, x21",
|
|
"lsl w0, w20, #16",
|
|
"cmn w0, w21, lsl #16",
|
|
"add w26, w20, w21",
|
|
"bfxil x6, x20, #0, #16",
|
|
"bfxil x4, x26, #0, #16",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"xadd [rax], bx": {
|
|
"ExpectedInstructionCount": 8,
|
|
"Comment": "0x0f 0xc1",
|
|
"ExpectedArm64ASM": [
|
|
"uxth w20, w6",
|
|
"ldaddalh w20, w21, [x4]",
|
|
"eor x27, x21, x20",
|
|
"lsl w0, w21, #16",
|
|
"cmn w0, w20, lsl #16",
|
|
"add w26, w21, w20",
|
|
"bfxil x6, x21, #0, #16",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"xadd eax, ebx": {
|
|
"ExpectedInstructionCount": 7,
|
|
"Comment": "0x0f 0xc1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w4",
|
|
"mov w21, w6",
|
|
"eor x27, x20, x21",
|
|
"adds w26, w20, w21",
|
|
"cfinv",
|
|
"mov x6, x20",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"xadd [rax], ebx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xc1",
|
|
"ExpectedArm64ASM": [
|
|
"mov w20, w6",
|
|
"ldaddal w20, w6, [x4]",
|
|
"eor x27, x6, x20",
|
|
"adds w26, w6, w20",
|
|
"cfinv"
|
|
]
|
|
},
|
|
"xadd rax, rbx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xc1",
|
|
"ExpectedArm64ASM": [
|
|
"eor x27, x4, x6",
|
|
"adds x26, x4, x6",
|
|
"cfinv",
|
|
"mov x6, x4",
|
|
"mov x4, x26"
|
|
]
|
|
},
|
|
"xadd [rax], rbx": {
|
|
"ExpectedInstructionCount": 5,
|
|
"Comment": "0x0f 0xc1",
|
|
"ExpectedArm64ASM": [
|
|
"ldaddal x6, x20, [x4]",
|
|
"eor x27, x20, x6",
|
|
"adds x26, x20, x6",
|
|
"cfinv",
|
|
"mov x6, x20"
|
|
]
|
|
},
|
|
"pmovmskb eax, mm0": {
|
|
"ExpectedInstructionCount": 11,
|
|
"Comment": "0x0f 0xd7",
|
|
"ExpectedArm64ASM": [
|
|
"strb wzr, [x28, #1051]",
|
|
"mov w20, #0xffff",
|
|
"strb w20, [x28, #1202]",
|
|
"ldr d2, [x28, #1056]",
|
|
"ldr d3, [x28, #3408]",
|
|
"cmlt v2.16b, v2.16b, #0",
|
|
"and v2.8b, v2.8b, v3.8b",
|
|
"addp v2.16b, v2.16b, v2.16b",
|
|
"addp v2.8b, v2.8b, v2.8b",
|
|
"addp v2.8b, v2.8b, v2.8b",
|
|
"umov w4, v2.h[0]"
|
|
]
|
|
},
|
|
"maskmovq mm0, mm1": {
|
|
"ExpectedInstructionCount": 9,
|
|
"Comment": "0x0f 0xf7",
|
|
"ExpectedArm64ASM": [
|
|
"strb wzr, [x28, #1051]",
|
|
"mov w20, #0xffff",
|
|
"strb w20, [x28, #1202]",
|
|
"ldr d2, [x28, #1072]",
|
|
"cmlt v2.16b, v2.16b, #0",
|
|
"ldr d3, [x28, #1056]",
|
|
"ldr d4, [x11]",
|
|
"bsl v2.8b, v3.8b, v4.8b",
|
|
"str d2, [x11]"
|
|
]
|
|
}
|
|
}
|
|
}
|