FEX-Emu--FEX/unittests/InstructionCountCI/FlagM/Primary.json

{
  "Features": {
    "Bitness": 64,
    "EnabledHostFeatures": [
      "FLAGM",
      "FLAGM2"
    ],
    "DisabledHostFeatures": [
      "SVE128",
      "SVE256",
      "AFP"
    ],
    "BinaryCacheVersion": 12
  },
  "Instructions": {
    "add bl, cl": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x00",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "lsl w0, w6, #24",
        "cmn w0, w7, lsl #24",
        "add w26, w6, w7",
        "bfxil x6, x26, #0, #8",
        "cfinv"
      ]
    },
    "add bx, cx": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x01",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "lsl w0, w6, #16",
        "cmn w0, w7, lsl #16",
        "add w26, w6, w7",
        "bfxil x6, x26, #0, #16",
        "cfinv"
      ]
    },
    "add ebx, ecx": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x01",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "adds w26, w6, w7",
        "cfinv",
        "mov x6, x26"
      ]
    },
    "add rbx, rcx": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x01",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "adds x26, x6, x7",
        "cfinv",
        "mov x6, x26"
      ]
    },
    "db 0x02, 0xcb": {
      "ExpectedInstructionCount": 6,
      "Comment": [
        "0x02",
        "add bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "lsl w0, w7, #24",
        "cmn w0, w6, lsl #24",
        "add w26, w7, w6",
        "bfxil x7, x26, #0, #8",
        "cfinv"
      ]
    },
    "db 0x66, 0x03, 0xcb": {
      "ExpectedInstructionCount": 6,
      "Comment": [
        "0x03",
        "add bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "lsl w0, w7, #16",
        "cmn w0, w6, lsl #16",
        "add w26, w7, w6",
        "bfxil x7, x26, #0, #16",
        "cfinv"
      ]
    },
    "db 0x03, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x03",
        "add ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "adds w26, w7, w6",
        "cfinv",
        "mov x7, x26"
      ]
    },
    "db 0x48, 0x03, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x03",
        "add rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "adds x26, x7, x6",
        "cfinv",
        "mov x7, x26"
      ]
    },
    "add al, 1": {
      "ExpectedInstructionCount": 9,
      "Comment": "0x04",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "lsl w0, w4, #24",
        "cmn w0, w20, lsl #24",
        "add w26, w4, #0x1 (1)",
        "mov x20, x4",
        "bfxil x20, x26, #0, #8",
        "cfinv",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "add ax, 1": {
      "ExpectedInstructionCount": 9,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "lsl w0, w4, #16",
        "cmn w0, w20, lsl #16",
        "add w26, w4, #0x1 (1)",
        "mov x20, x4",
        "bfxil x20, x26, #0, #16",
        "cfinv",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "add eax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "adds w26, w4, #0x1 (1)",
        "cfinv",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "add rax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "adds x26, x4, #0x1 (1)",
        "cfinv",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "add al, -1": {
      "ExpectedInstructionCount": 7,
      "Comment": "0x04",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "mvn w27, w4",
        "lsl w0, w4, #24",
        "cmn w0, w20, lsl #24",
        "add w26, w4, #0xff (255)",
        "bfxil x4, x26, #0, #8",
        "cfinv"
      ]
    },
    "add ax, -1": {
      "ExpectedInstructionCount": 7,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "mov w20, #0xffff",
        "mvn w27, w4",
        "lsl w0, w4, #16",
        "cmn w0, w20, lsl #16",
        "add w26, w4, w20",
        "bfxil x4, x26, #0, #16",
        "cfinv"
      ]
    },
    "add eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "subs w26, w4, #0x1 (1)",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "add rax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x05",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "subs x26, x4, #0x1 (1)",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "or bl, bh": {
      "ExpectedInstructionCount": 5,
      "Comment": "",
      "ExpectedArm64ASM": [
        "lsr w20, w6, #8",
        "orr w26, w6, w20",
        "cmn wzr, w26, lsl #24",
        "bfxil x6, x26, #0, #8",
        "cfinv"
      ]
    },
    "or bl, cl": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x08",
      "ExpectedArm64ASM": [
        "orr w26, w6, w7",
        "cmn wzr, w26, lsl #24",
        "bfxil x6, x26, #0, #8",
        "cfinv"
      ]
    },
    "or bx, cx": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x09",
      "ExpectedArm64ASM": [
        "orr w26, w6, w7",
        "cmn wzr, w26, lsl #16",
        "bfxil x6, x26, #0, #16",
        "cfinv"
      ]
    },
    "or ebx, ecx": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x09",
      "ExpectedArm64ASM": [
        "orr w6, w6, w7",
        "subs w26, w6, #0x0 (0)"
      ]
    },
    "or rbx, rcx": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x09",
      "ExpectedArm64ASM": [
        "orr x6, x6, x7",
        "subs x26, x6, #0x0 (0)"
      ]
    },
    "db 0x0A, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x0A",
        "or bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "orr w26, w7, w6",
        "cmn wzr, w26, lsl #24",
        "bfxil x7, x26, #0, #8",
        "cfinv"
      ]
    },
    "db 0x66, 0x0B, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x0B",
        "or bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "orr w26, w7, w6",
        "cmn wzr, w26, lsl #16",
        "bfxil x7, x26, #0, #16",
        "cfinv"
      ]
    },
    "db 0x0B, 0xcb": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0x0B",
        "or ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "orr w7, w7, w6",
        "subs w26, w7, #0x0 (0)"
      ]
    },
    "db 0x48, 0x0B, 0xcb": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0x0B",
        "or rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "orr x7, x7, x6",
        "subs x26, x7, #0x0 (0)"
      ]
    },
    "or al, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x0C",
      "ExpectedArm64ASM": [
        "orr x26, x4, #0x1",
        "cmn wzr, w26, lsl #24",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "or ax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "orr x26, x4, #0x1",
        "cmn wzr, w26, lsl #16",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "or eax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "orr w4, w4, #0x1",
        "subs w26, w4, #0x0 (0)"
      ]
    },
    "or rax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "orr x4, x4, #0x1",
        "subs x26, x4, #0x0 (0)"
      ]
    },
    "or al, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x0C",
      "ExpectedArm64ASM": [
        "orr x26, x4, #0xff",
        "cmn wzr, w26, lsl #24",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "or ax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "orr x26, x4, #0xffff",
        "cmn wzr, w26, lsl #16",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "or eax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "orr w4, w4, w20",
        "subs w26, w4, #0x0 (0)"
      ]
    },
    "or rax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x0D",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "orr x4, x4, x20",
        "subs x26, x4, #0x0 (0)"
      ]
    },
    "adc bl, cl": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x10",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "uxtb x20, w7",
        "cinc w21, w20, lo",
        "add w22, w6, w21",
        "uxtb w26, w22",
        "cmp w26, w21",
        "cset x21, hs",
        "cmn wzr, w26, lsl #24",
        "rmif x21, #63, #nzCv",
        "eor w20, w6, w20",
        "eor w21, w26, w6",
        "bic w20, w21, w20",
        "rmif x20, #7, #nzcV",
        "bfxil x6, x26, #0, #8"
      ]
    },
    "adc bx, cx": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x11",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "uxth x20, w7",
        "cinc w21, w20, lo",
        "add w22, w6, w21",
        "uxth w26, w22",
        "cmp w26, w21",
        "cset x21, hs",
        "cmn wzr, w26, lsl #16",
        "rmif x21, #63, #nzCv",
        "eor w20, w6, w20",
        "eor w21, w26, w6",
        "bic w20, w21, w20",
        "rmif x20, #15, #nzcV",
        "bfxil x6, x26, #0, #16"
      ]
    },
    "adc ebx, ecx": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x11",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "cfinv",
        "adcs w26, w6, w7",
        "cfinv",
        "mov x6, x26"
      ]
    },
    "adc rbx, rcx": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x11",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "cfinv",
        "adcs x26, x6, x7",
        "cfinv",
        "mov x6, x26"
      ]
    },
    "db 0x12, 0xcb": {
      "ExpectedInstructionCount": 14,
      "Comment": [
        "0x12",
        "adc bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "uxtb x20, w6",
        "cinc w21, w20, lo",
        "add w22, w7, w21",
        "uxtb w26, w22",
        "cmp w26, w21",
        "cset x21, hs",
        "cmn wzr, w26, lsl #24",
        "rmif x21, #63, #nzCv",
        "eor w20, w7, w20",
        "eor w21, w26, w7",
        "bic w20, w21, w20",
        "rmif x20, #7, #nzcV",
        "bfxil x7, x26, #0, #8"
      ]
    },
    "db 0x66, 0x13, 0xcb": {
      "ExpectedInstructionCount": 14,
      "Comment": [
        "0x13",
        "adc bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "uxth x20, w6",
        "cinc w21, w20, lo",
        "add w22, w7, w21",
        "uxth w26, w22",
        "cmp w26, w21",
        "cset x21, hs",
        "cmn wzr, w26, lsl #16",
        "rmif x21, #63, #nzCv",
        "eor w20, w7, w20",
        "eor w21, w26, w7",
        "bic w20, w21, w20",
        "rmif x20, #15, #nzcV",
        "bfxil x7, x26, #0, #16"
      ]
    },
    "db 0x13, 0xcb": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x13",
        "adc ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "cfinv",
        "adcs w26, w7, w6",
        "cfinv",
        "mov x7, x26"
      ]
    },
    "db 0x48, 0x13, 0xcb": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x13",
        "adc rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "cfinv",
        "adcs x26, x7, x6",
        "cfinv",
        "mov x7, x26"
      ]
    },
    "adc al, 1": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x14",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "cinc w20, w20, lo",
        "add w21, w4, w20",
        "uxtb w26, w21",
        "cmp w26, w20",
        "cset x20, hs",
        "cmn wzr, w26, lsl #24",
        "rmif x20, #63, #nzCv",
        "bic w20, w26, w4",
        "rmif x20, #7, #nzcV",
        "mov x20, x4",
        "bfxil x20, x26, #0, #8",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "adc ax, 1": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "cinc w20, w20, lo",
        "add w21, w4, w20",
        "uxth w26, w21",
        "cmp w26, w20",
        "cset x20, hs",
        "cmn wzr, w26, lsl #16",
        "rmif x20, #63, #nzCv",
        "bic w20, w26, w4",
        "rmif x20, #15, #nzcV",
        "mov x20, x4",
        "bfxil x20, x26, #0, #16",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "adc eax, 1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "cfinv",
        "adcs w26, w4, w20",
        "cfinv",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "adc rax, 1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "cfinv",
        "adcs x26, x4, x20",
        "cfinv",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "adc al, -1": {
      "ExpectedInstructionCount": 12,
      "Comment": "0x14",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "mvn w27, w4",
        "cinc w20, w20, lo",
        "add w21, w4, w20",
        "uxtb w26, w21",
        "cmp w26, w20",
        "cset x20, hs",
        "cmn wzr, w26, lsl #24",
        "rmif x20, #63, #nzCv",
        "bic w20, w4, w26",
        "rmif x20, #7, #nzcV",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "adc ax, -1": {
      "ExpectedInstructionCount": 12,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mov w20, #0xffff",
        "mvn w27, w4",
        "cinc w20, w20, lo",
        "add w21, w4, w20",
        "uxth w26, w21",
        "cmp w26, w20",
        "cset x20, hs",
        "cmn wzr, w26, lsl #16",
        "rmif x20, #63, #nzCv",
        "bic w20, w4, w26",
        "rmif x20, #15, #nzcV",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "adc eax, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "cfinv",
        "adcs w26, w4, w20",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "adc rax, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x15",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "mvn w27, w4",
        "cfinv",
        "adcs x26, x4, x20",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "sbb bl, cl": {
      "ExpectedInstructionCount": 15,
      "Comment": "0x18",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "uxtb w20, w6",
        "uxtb x21, w7",
        "cinc w22, w21, lo",
        "sub w23, w20, w22",
        "uxtb w26, w23",
        "cmp w20, w22",
        "cset x22, hs",
        "cmn wzr, w26, lsl #24",
        "rmif x22, #63, #nzCv",
        "eor w21, w20, w21",
        "eor w20, w26, w20",
        "and w20, w20, w21",
        "rmif x20, #7, #nzcV",
        "bfxil x6, x26, #0, #8"
      ]
    },
    "sbb bx, cx": {
      "ExpectedInstructionCount": 15,
      "Comment": "0x19",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "uxth w20, w6",
        "uxth x21, w7",
        "cinc w22, w21, lo",
        "sub w23, w20, w22",
        "uxth w26, w23",
        "cmp w20, w22",
        "cset x22, hs",
        "cmn wzr, w26, lsl #16",
        "rmif x22, #63, #nzCv",
        "eor w21, w20, w21",
        "eor w20, w26, w20",
        "and w20, w20, w21",
        "rmif x20, #15, #nzcV",
        "bfxil x6, x26, #0, #16"
      ]
    },
    "sbb ebx, ecx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x19",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "sbcs w26, w6, w7",
        "mov x6, x26"
      ]
    },
    "sbb rbx, rcx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x19",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "sbcs x26, x6, x7",
        "mov x6, x26"
      ]
    },
    "db 0x1A, 0xcb": {
      "ExpectedInstructionCount": 15,
      "Comment": [
        "0x1A",
        "sbb bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "uxtb w20, w7",
        "uxtb x21, w6",
        "cinc w22, w21, lo",
        "sub w23, w20, w22",
        "uxtb w26, w23",
        "cmp w20, w22",
        "cset x22, hs",
        "cmn wzr, w26, lsl #24",
        "rmif x22, #63, #nzCv",
        "eor w21, w20, w21",
        "eor w20, w26, w20",
        "and w20, w20, w21",
        "rmif x20, #7, #nzcV",
        "bfxil x7, x26, #0, #8"
      ]
    },
    "db 0x66, 0x1B, 0xcb": {
      "ExpectedInstructionCount": 15,
      "Comment": [
        "0x1B",
        "sbb bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "uxth w20, w7",
        "uxth x21, w6",
        "cinc w22, w21, lo",
        "sub w23, w20, w22",
        "uxth w26, w23",
        "cmp w20, w22",
        "cset x22, hs",
        "cmn wzr, w26, lsl #16",
        "rmif x22, #63, #nzCv",
        "eor w21, w20, w21",
        "eor w20, w26, w20",
        "and w20, w20, w21",
        "rmif x20, #15, #nzcV",
        "bfxil x7, x26, #0, #16"
      ]
    },
    "db 0x1B, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x1B",
        "sbb ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "sbcs w26, w7, w6",
        "mov x7, x26"
      ]
    },
    "db 0x48, 0x1B, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x1B",
        "sbb rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "sbcs x26, x7, x6",
        "mov x7, x26"
      ]
    },
    "sbb al, 1": {
      "ExpectedInstructionCount": 15,
      "Comment": "0x1C",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "uxtb w21, w4",
        "cinc w20, w20, lo",
        "sub w22, w21, w20",
        "uxtb w26, w22",
        "cmp w21, w20",
        "cset x20, hs",
        "cmn wzr, w26, lsl #24",
        "rmif x20, #63, #nzCv",
        "bic w20, w21, w26",
        "rmif x20, #7, #nzcV",
        "mov x20, x4",
        "bfxil x20, x26, #0, #8",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "sbb ax, 1": {
      "ExpectedInstructionCount": 15,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "uxth w21, w4",
        "cinc w20, w20, lo",
        "sub w22, w21, w20",
        "uxth w26, w22",
        "cmp w21, w20",
        "cset x20, hs",
        "cmn wzr, w26, lsl #16",
        "rmif x20, #63, #nzCv",
        "bic w20, w21, w26",
        "rmif x20, #15, #nzcV",
        "mov x20, x4",
        "bfxil x20, x26, #0, #16",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "sbb eax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "sbcs w26, w4, w20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sbb rax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "sbcs x26, x4, x20",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sbb al, -1": {
      "ExpectedInstructionCount": 13,
      "Comment": "0x1C",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "mvn w27, w4",
        "uxtb w21, w4",
        "cinc w20, w20, lo",
        "sub w22, w21, w20",
        "uxtb w26, w22",
        "cmp w21, w20",
        "cset x20, hs",
        "cmn wzr, w26, lsl #24",
        "rmif x20, #63, #nzCv",
        "bic w20, w26, w21",
        "rmif x20, #7, #nzcV",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "sbb ax, -1": {
      "ExpectedInstructionCount": 13,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffff",
        "mvn w27, w4",
        "uxth w21, w4",
        "cinc w20, w20, lo",
        "sub w22, w21, w20",
        "uxth w26, w22",
        "cmp w21, w20",
        "cset x20, hs",
        "cmn wzr, w26, lsl #16",
        "rmif x20, #63, #nzCv",
        "bic w20, w26, w21",
        "rmif x20, #15, #nzcV",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "sbb eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "mvn w27, w4",
        "sbcs w26, w4, w20",
        "mov x4, x26"
      ]
    },
    "sbb rax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x1D",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "mvn w27, w4",
        "sbcs x26, x4, x20",
        "mov x4, x26"
      ]
    },
    "and bl, cl": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x20",
      "ExpectedArm64ASM": [
        "and w26, w6, w7",
        "cmn wzr, w26, lsl #24",
        "bfxil x6, x26, #0, #8",
        "cfinv"
      ]
    },
    "and bx, cx": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x21",
      "ExpectedArm64ASM": [
        "and w26, w6, w7",
        "cmn wzr, w26, lsl #16",
        "bfxil x6, x26, #0, #16",
        "cfinv"
      ]
    },
    "and ebx, ecx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x21",
      "ExpectedArm64ASM": [
        "ands w26, w6, w7",
        "cfinv",
        "mov x6, x26"
      ]
    },
    "and rbx, rcx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x21",
      "ExpectedArm64ASM": [
        "ands x26, x6, x7",
        "cfinv",
        "mov x6, x26"
      ]
    },
    "db 0x22, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x22",
        "and bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "and w26, w7, w6",
        "cmn wzr, w26, lsl #24",
        "bfxil x7, x26, #0, #8",
        "cfinv"
      ]
    },
    "db 0x66, 0x23, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x23",
        "and bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "and w26, w7, w6",
        "cmn wzr, w26, lsl #16",
        "bfxil x7, x26, #0, #16",
        "cfinv"
      ]
    },
    "db 0x23, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x23",
        "and ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "ands w26, w7, w6",
        "cfinv",
        "mov x7, x26"
      ]
    },
    "db 0x48, 0x23, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x23",
        "and rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "ands x26, x7, x6",
        "cfinv",
        "mov x7, x26"
      ]
    },
    "and al, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x24",
      "ExpectedArm64ASM": [
        "and x26, x4, #0xffffffffffffff01",
        "cmn wzr, w26, lsl #24",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "and ax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "and x26, x4, #0xffffffffffff0001",
        "cmn wzr, w26, lsl #16",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "and eax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "ands w26, w4, #0x1",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "and rax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "ands x26, x4, #0x1",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "and al, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x24",
      "ExpectedArm64ASM": [
        "cmn wzr, w4, lsl #24",
        "cfinv",
        "mov x26, x4"
      ]
    },
    "and ax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "cmn wzr, w4, lsl #16",
        "cfinv",
        "mov x26, x4"
      ]
    },
    "and eax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "mov w20, #0xffffffff",
        "ands w26, w4, w20",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "and rax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x25",
      "ExpectedArm64ASM": [
        "mov x20, #0xffffffffffffffff",
        "ands x26, x4, x20",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "sub bl, cl": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x28",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "lsl w0, w6, #24",
        "cmp w0, w7, lsl #24",
        "sub w26, w6, w7",
        "bfxil x6, x26, #0, #8"
      ]
    },
    "sub bx, cx": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x29",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "lsl w0, w6, #16",
        "cmp w0, w7, lsl #16",
        "sub w26, w6, w7",
        "bfxil x6, x26, #0, #16"
      ]
    },
    "sub ebx, ecx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x29",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "subs w26, w6, w7",
        "mov x6, x26"
      ]
    },
    "sub rbx, rcx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x29",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "subs x26, x6, x7",
        "mov x6, x26"
      ]
    },
    "db 0x2A, 0xcb": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x2A",
        "sub bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "lsl w0, w7, #24",
        "cmp w0, w6, lsl #24",
        "sub w26, w7, w6",
        "bfxil x7, x26, #0, #8"
      ]
    },
    "db 0x66, 0x2B, 0xcb": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x2B",
        "sub bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "lsl w0, w7, #16",
        "cmp w0, w6, lsl #16",
        "sub w26, w7, w6",
        "bfxil x7, x26, #0, #16"
      ]
    },
    "db 0x2B, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x2B",
        "sub ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "subs w26, w7, w6",
        "mov x7, x26"
      ]
    },
    "db 0x48, 0x2B, 0xcb": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x2B",
        "sub rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "subs x26, x7, x6",
        "mov x7, x26"
      ]
    },
    "sub al, 1": {
      "ExpectedInstructionCount": 8,
      "Comment": "0x2C",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0x1 (1)",
        "mov x20, x4",
        "bfxil x20, x26, #0, #8",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "sub ax, 1": {
      "ExpectedInstructionCount": 8,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, #0x1 (1)",
        "mov x20, x4",
        "bfxil x20, x26, #0, #16",
        "mov x27, x4",
        "mov x4, x20"
      ]
    },
    "sub eax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "subs w26, w4, #0x1 (1)",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sub rax, 1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "subs x26, x4, #0x1 (1)",
        "mov x27, x4",
        "mov x4, x26"
      ]
    },
    "sub al, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x2C",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "mvn w27, w4",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0xff (255)",
        "bfxil x4, x26, #0, #8"
      ]
    },
    "sub ax, -1": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffff",
        "mvn w27, w4",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "bfxil x4, x26, #0, #16"
      ]
    },
    "sub eax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "adds w26, w4, #0x1 (1)",
        "mov x4, x26"
      ]
    },
    "sub rax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x2D",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "adds x26, x4, #0x1 (1)",
        "mov x4, x26"
      ]
    },
    "xor bl, cl": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x30",
      "ExpectedArm64ASM": [
        "eor w26, w6, w7",
        "cmn wzr, w26, lsl #24",
        "bfxil x6, x26, #0, #8",
        "cfinv"
      ]
    },
    "xor bx, cx": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x31",
      "ExpectedArm64ASM": [
        "eor w26, w6, w7",
        "cmn wzr, w26, lsl #16",
        "bfxil x6, x26, #0, #16",
        "cfinv"
      ]
    },
    "xor ebx, ecx": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x31",
      "ExpectedArm64ASM": [
        "eor w6, w6, w7",
        "subs w26, w6, #0x0 (0)"
      ]
    },
    "xor rbx, rcx": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x31",
      "ExpectedArm64ASM": [
        "eor x6, x6, x7",
        "subs x26, x6, #0x0 (0)"
      ]
    },
    "db 0x32, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x32",
        "xor bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w26, w7, w6",
        "cmn wzr, w26, lsl #24",
        "bfxil x7, x26, #0, #8",
        "cfinv"
      ]
    },
    "db 0x66, 0x33, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x33",
        "xor bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w26, w7, w6",
        "cmn wzr, w26, lsl #16",
        "bfxil x7, x26, #0, #16",
        "cfinv"
      ]
    },
    "db 0x33, 0xcb": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0x33",
        "xor ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor w7, w7, w6",
        "subs w26, w7, #0x0 (0)"
      ]
    },
    "db 0x48, 0x33, 0xcb": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0x33",
        "xor rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x7, x7, x6",
        "subs x26, x7, #0x0 (0)"
      ]
    },
    "xor al, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x34",
      "ExpectedArm64ASM": [
        "eor x26, x4, #0x1",
        "cmn wzr, w26, lsl #24",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "xor ax, 1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "eor x26, x4, #0x1",
        "cmn wzr, w26, lsl #16",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "xor eax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "eor w4, w4, #0x1",
        "subs w26, w4, #0x0 (0)"
      ]
    },
    "xor rax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "eor x4, x4, #0x1",
        "subs x26, x4, #0x0 (0)"
      ]
    },
    "cmp bl, cl": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x38",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "lsl w0, w6, #24",
        "cmp w0, w7, lsl #24",
        "sub w26, w6, w7"
      ]
    },
    "xor al, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x34",
      "ExpectedArm64ASM": [
        "eor x26, x4, #0xff",
        "cmn wzr, w26, lsl #24",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "xor ax, -1": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "eor x26, x4, #0xffff",
        "cmn wzr, w26, lsl #16",
        "cfinv",
        "mov x4, x26"
      ]
    },
    "xor eax, -1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "mvn w4, w4",
        "subs w26, w4, #0x0 (0)"
      ]
    },
    "xor rax, -1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x35",
      "ExpectedArm64ASM": [
        "mvn x4, x4",
        "subs x26, x4, #0x0 (0)"
      ]
    },
    "cmp bx, cx": {
      "ExpectedInstructionCount": 4,
      "Comment": "0x39",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "lsl w0, w6, #16",
        "cmp w0, w7, lsl #16",
        "sub w26, w6, w7"
      ]
    },
    "cmp ebx, ecx": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x39",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "subs w26, w6, w7"
      ]
    },
    "cmp rbx, rcx": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x39",
      "ExpectedArm64ASM": [
        "eor x27, x6, x7",
        "subs x26, x6, x7"
      ]
    },
    "db 0x3A, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x3A",
        "cmp bl, cl but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "lsl w0, w7, #24",
        "cmp w0, w6, lsl #24",
        "sub w26, w7, w6"
      ]
    },
    "db 0x66, 0x3B, 0xcb": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x3B",
        "cmp bx, cx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "lsl w0, w7, #16",
        "cmp w0, w6, lsl #16",
        "sub w26, w7, w6"
      ]
    },
    "db 0x3B, 0xcb": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0x3B",
        "cmp ebx, ecx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "subs w26, w7, w6"
      ]
    },
    "db 0x48, 0x3B, 0xcb": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0x3B",
        "cmp rbx, rcx but modrm.rm as source"
      ],
      "ExpectedArm64ASM": [
        "eor x27, x7, x6",
        "subs x26, x7, x6"
      ]
    },
    "cmp al, 1": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x3C",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0x1 (1)",
        "mov x27, x4"
      ]
    },
    "cmp ax, 1": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, #0x1 (1)",
        "mov x27, x4"
      ]
    },
    "cmp eax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "subs w26, w4, #0x1 (1)",
        "mov x27, x4"
      ]
    },
    "cmp rax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "subs x26, x4, #0x1 (1)",
        "mov x27, x4"
      ]
    },
    "cmp al, -1": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x3C",
      "ExpectedArm64ASM": [
        "mov w20, #0xff",
        "mvn w27, w4",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, #0xff (255)"
      ]
    },
    "cmp ax, -1": {
      "ExpectedInstructionCount": 5,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "mov w20, #0xffff",
        "mvn w27, w4",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20"
      ]
    },
    "cmp eax, -1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "adds w26, w4, #0x1 (1)"
      ]
    },
    "cmp rax, -1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x3D",
      "ExpectedArm64ASM": [
        "mvn w27, w4",
        "adds x26, x4, #0x1 (1)"
      ]
    },
    "imul ax, bx, 257": {
      "ExpectedInstructionCount": 8,
      "Comment": "0x69",
      "ExpectedArm64ASM": [
        "mov w20, #0x101",
        "sxth x21, w6",
        "mul x20, x21, x20",
        "sbfx x21, x20, #16, #16",
        "bfxil x4, x20, #0, #16",
        "sbfx x20, x20, #15, #1",
        "cmp x21, x20",
        "ccmp xzr, #0, #nzcV, eq"
      ]
    },
    "imul eax, ebx, 257": {
      "ExpectedInstructionCount": 7,
      "Comment": "0x69",
      "ExpectedArm64ASM": [
        "mov w20, #0x101",
        "smull x21, w6, w20",
        "asr x21, x21, #32",
        "mul w4, w6, w20",
        "sbfx x20, x4, #31, #1",
        "cmp x21, x20",
        "ccmp xzr, #0, #nzcV, eq"
      ]
    },
    "imul rax, rbx, 257": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x69",
      "ExpectedArm64ASM": [
        "mov w20, #0x101",
        "smulh x21, x6, x20",
        "mul x4, x6, x20",
        "asr x20, x4, #63",
        "cmp x21, x20",
        "ccmp xzr, #0, #nzcV, eq"
      ]
    },
    "imul ax, bx, 3": {
      "ExpectedInstructionCount": 8,
      "Comment": "0x6b",
      "ExpectedArm64ASM": [
        "mov w20, #0x3",
        "sxth x21, w6",
        "mul x20, x21, x20",
        "sbfx x21, x20, #16, #16",
        "bfxil x4, x20, #0, #16",
        "sbfx x20, x20, #15, #1",
        "cmp x21, x20",
        "ccmp xzr, #0, #nzcV, eq"
      ]
    },
    "imul eax, ebx, 3": {
      "ExpectedInstructionCount": 7,
      "Comment": "0x6b",
      "ExpectedArm64ASM": [
        "mov w20, #0x3",
        "smull x21, w6, w20",
        "asr x21, x21, #32",
        "mul w4, w6, w20",
        "sbfx x20, x4, #31, #1",
        "cmp x21, x20",
        "ccmp xzr, #0, #nzcV, eq"
      ]
    },
    "imul rax, rbx, 3": {
      "ExpectedInstructionCount": 6,
      "Comment": "0x6b",
      "ExpectedArm64ASM": [
        "mov w20, #0x3",
        "smulh x21, x6, x20",
        "mul x4, x6, x20",
        "asr x20, x4, #63",
        "cmp x21, x20",
        "ccmp xzr, #0, #nzcV, eq"
      ]
    },
    "test al, bl": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x84",
      "ExpectedArm64ASM": [
        "and w26, w4, w6",
        "cmn wzr, w26, lsl #24",
        "cfinv"
      ]
    },
    "test ax, bx": {
      "ExpectedInstructionCount": 3,
      "Comment": "0x84",
      "ExpectedArm64ASM": [
        "and w26, w4, w6",
        "cmn wzr, w26, lsl #16",
        "cfinv"
      ]
    },
    "test eax, ebx": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x84",
      "ExpectedArm64ASM": [
        "ands w26, w4, w6",
        "cfinv"
      ]
    },
    "test rax, rbx": {
      "ExpectedInstructionCount": 2,
      "Comment": "0x84",
      "ExpectedArm64ASM": [
        "ands x26, x4, x6",
        "cfinv"
      ]
    },
    "o16 pushf": {
      "ExpectedInstructionCount": 39,
      "Comment": "0x9c",
      "ExpectedArm64ASM": [
        "cset x20, lo",
        "eor x21, x27, x26",
        "ubfx w21, w21, #4, #1",
        "orr x20, x20, x21, lsl #4",
        "ldrb w21, [x28, #1016]",
        "orr x20, x20, x21, lsl #8",
        "ldrb w21, [x28, #1017]",
        "orr x20, x20, x21, lsl #9",
        "ldrsb x21, [x28, #1018]",
        "lsr x21, x21, #63",
        "orr x20, x20, x21, lsl #10",
        "cset x21, vs",
        "orr x20, x20, x21, lsl #11",
        "ldrb w21, [x28, #1020]",
        "orr x20, x20, x21, lsl #12",
        "ldrb w21, [x28, #1022]",
        "orr x20, x20, x21, lsl #14",
        "ldrb w21, [x28, #1024]",
        "orr x20, x20, x21, lsl #16",
        "ldrb w21, [x28, #1025]",
        "orr x20, x20, x21, lsl #17",
        "ldrb w21, [x28, #1026]",
        "orr x20, x20, x21, lsl #18",
        "ldrb w21, [x28, #1027]",
        "orr x20, x20, x21, lsl #19",
        "ldrb w21, [x28, #1028]",
        "orr x20, x20, x21, lsl #20",
        "ldrb w21, [x28, #1029]",
        "orr x20, x20, x21, lsl #21",
        "eor w0, w26, w26, lsr #4",
        "eor w0, w0, w0, lsr #2",
        "eor w21, w0, w0, lsr #1",
        "orr x21, x21, #0xfffffffffffffffe",
        "orn x20, x20, x21, ror #62",
        "mrs x21, nzcv",
        "and x21, x21, #0xc0000000",
        "orr x20, x20, x21, lsr #24",
        "orr x20, x20, #0x2",
        "strh w20, [x8, #-2]!"
      ]
    },
    "pushfq": {
      "ExpectedInstructionCount": 39,
      "Comment": "0x9c",
      "ExpectedArm64ASM": [
        "cset x20, lo",
        "eor x21, x27, x26",
        "ubfx w21, w21, #4, #1",
        "orr x20, x20, x21, lsl #4",
        "ldrb w21, [x28, #1016]",
        "orr x20, x20, x21, lsl #8",
        "ldrb w21, [x28, #1017]",
        "orr x20, x20, x21, lsl #9",
        "ldrsb x21, [x28, #1018]",
        "lsr x21, x21, #63",
        "orr x20, x20, x21, lsl #10",
        "cset x21, vs",
        "orr x20, x20, x21, lsl #11",
        "ldrb w21, [x28, #1020]",
        "orr x20, x20, x21, lsl #12",
        "ldrb w21, [x28, #1022]",
        "orr x20, x20, x21, lsl #14",
        "ldrb w21, [x28, #1024]",
        "orr x20, x20, x21, lsl #16",
        "ldrb w21, [x28, #1025]",
        "orr x20, x20, x21, lsl #17",
        "ldrb w21, [x28, #1026]",
        "orr x20, x20, x21, lsl #18",
        "ldrb w21, [x28, #1027]",
        "orr x20, x20, x21, lsl #19",
        "ldrb w21, [x28, #1028]",
        "orr x20, x20, x21, lsl #20",
        "ldrb w21, [x28, #1029]",
        "orr x20, x20, x21, lsl #21",
        "eor w0, w26, w26, lsr #4",
        "eor w0, w0, w0, lsr #2",
        "eor w21, w0, w0, lsr #1",
        "orr x21, x21, #0xfffffffffffffffe",
        "orn x20, x20, x21, ror #62",
        "mrs x21, nzcv",
        "and x21, x21, #0xc0000000",
        "orr x20, x20, x21, lsr #24",
        "orr x20, x20, #0x2",
        "str x20, [x8, #-8]!"
      ]
    },
    "popf": {
      "ExpectedInstructionCount": 40,
      "Comment": "0x9d",
      "ExpectedArm64ASM": [
        "ldr x20, [x8], #8",
        "mov w21, #0x202",
        "orr x27, x20, x21",
        "mvn w20, w27",
        "rmif x20, #63, #nzCv",
        "ubfx w26, w20, #2, #1",
        "rmif x27, #4, #nZcv",
        "rmif x27, #4, #Nzcv",
        "ubfx w20, w27, #8, #1",
        "ldrb w21, [x28, #1016]",
        "and w21, w21, #0xfffffffe",
        "mov w22, #0x1",
        "mrs x23, nzcv",
        "cmp x20, #0x0 (0)",
        "csel x20, x21, x22, eq",
        "strb w20, [x28, #1016]",
        "ubfx w20, w27, #9, #1",
        "strb w20, [x28, #1017]",
        "ubfx w20, w27, #10, #1",
        "sub x20, x22, x20, lsl #1",
        "msr nzcv, x23",
        "rmif x27, #11, #nzcV",
        "ubfx w21, w27, #12, #1",
        "strb w21, [x28, #1020]",
        "ubfx w21, w27, #14, #1",
        "strb w21, [x28, #1022]",
        "ubfx w21, w27, #16, #1",
        "strb w21, [x28, #1024]",
        "ubfx w21, w27, #17, #1",
        "strb w21, [x28, #1025]",
        "ubfx w21, w27, #18, #1",
        "strb w21, [x28, #1026]",
        "ubfx w21, w27, #19, #1",
        "strb w21, [x28, #1027]",
        "ubfx w21, w27, #20, #1",
        "strb w21, [x28, #1028]",
        "ubfx w21, w27, #21, #1",
        "strb w21, [x28, #1029]",
        "mov w21, #0x10001",
        "strb w20, [x28, #1018]"
      ]
    },
    "sahf": {
      "ExpectedInstructionCount": 9,
      "Comment": "0x9e",
      "ExpectedArm64ASM": [
        "ubfx w20, w4, #8, #8",
        "mov w21, #0x28",
        "bic x20, x20, x21",
        "orr x27, x20, #0x2",
        "mvn w20, w27",
        "rmif x20, #63, #nzCv",
        "ubfx w26, w20, #2, #1",
        "rmif x27, #4, #nZcv",
        "rmif x27, #4, #Nzcv"
      ]
    },
    "lahf": {
      "ExpectedInstructionCount": 14,
      "Comment": "0x9f",
      "ExpectedArm64ASM": [
        "cset x20, lo",
        "eor x21, x27, x26",
        "ubfx w21, w21, #4, #1",
        "orr x20, x20, x21, lsl #4",
        "eor w0, w26, w26, lsr #4",
        "eor w0, w0, w0, lsr #2",
        "eor w21, w0, w0, lsr #1",
        "orr x21, x21, #0xfffffffffffffffe",
        "orn x20, x20, x21, ror #62",
        "mrs x21, nzcv",
        "and x21, x21, #0xc0000000",
        "orr x20, x20, x21, lsr #24",
        "orr x20, x20, #0x2",
        "bfi x4, x20, #8, #8"
      ]
    },
    "cmpsb": {
      "ExpectedInstructionCount": 9,
      "Comment": [
        "0xa6"
      ],
      "ExpectedArm64ASM": [
        "ldrb w20, [x11]",
        "ldrb w21, [x10]",
        "eor x27, x21, x20",
        "lsl w0, w21, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w21, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20",
        "add x10, x10, x20"
      ]
    },
    "cmpsw": {
      "ExpectedInstructionCount": 9,
      "Comment": [
        "0xa7"
      ],
      "ExpectedArm64ASM": [
        "ldrh w20, [x11]",
        "ldrh w21, [x10]",
        "eor x27, x21, x20",
        "lsl w0, w21, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w21, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #1",
        "add x10, x10, x20, lsl #1"
      ]
    },
    "cmpsd": {
      "ExpectedInstructionCount": 7,
      "Comment": [
        "0xa7"
      ],
      "ExpectedArm64ASM": [
        "ldr w20, [x11]",
        "ldr w21, [x10]",
        "eor x27, x21, x20",
        "subs w26, w21, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #2",
        "add x10, x10, x20, lsl #2"
      ]
    },
    "cmpsq": {
      "ExpectedInstructionCount": 7,
      "Comment": [
        "0xa7"
      ],
      "ExpectedArm64ASM": [
        "ldr x20, [x11]",
        "ldr x21, [x10]",
        "eor x27, x21, x20",
        "subs x26, x21, x20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #3",
        "add x10, x10, x20, lsl #3"
      ]
    },
    "repz cmpsb": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa6",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x64",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "add x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "sub x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor x20, x27, x26",
        "lsl w0, w27, #24",
        "cmp w0, w26, lsl #24",
        "sub w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repz cmpsw": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x64",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "add x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "sub x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor x20, x27, x26",
        "lsl w0, w27, #16",
        "cmp w0, w26, lsl #16",
        "sub w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repz cmpsd": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x5c",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "add x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "sub x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor x20, x27, x26",
        "subs w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repz cmpsq": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x5c",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "add x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "b #+0x20",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "sub x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nzcv, ne",
        "b.eq #-0x18",
        "eor x20, x27, x26",
        "subs x26, x27, x26",
        "mov x27, x20"
      ]
    },
    "repnz cmpsb": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa6",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x64",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "add x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldrb w26, [x11]",
        "ldrb w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "sub x10, x10, #0x1 (1)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor x20, x27, x26",
        "lsl w0, w27, #24",
        "cmp w0, w26, lsl #24",
        "sub w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repnz cmpsw": {
      "ExpectedInstructionCount": 25,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x64",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "add x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldrh w26, [x11]",
        "ldrh w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "sub x10, x10, #0x2 (2)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor x20, x27, x26",
        "lsl w0, w27, #16",
        "cmp w0, w26, lsl #16",
        "sub w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repnz cmpsd": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x5c",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "add x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldr w26, [x11]",
        "ldr w27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "sub x10, x10, #0x4 (4)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor x20, x27, x26",
        "subs w26, w27, w26",
        "mov x27, x20"
      ]
    },
    "repnz cmpsq": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xa7",
      "ExpectedArm64ASM": [
        "cbz x7, #+0x5c",
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "add x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "b #+0x20",
        "ldr x26, [x11]",
        "ldr x27, [x10]",
        "subs x7, x7, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "sub x10, x10, #0x8 (8)",
        "ccmp x27, x26, #nZcv, ne",
        "b.ne #-0x18",
        "eor x20, x27, x26",
        "subs x26, x27, x26",
        "mov x27, x20"
      ]
    },
    "test al, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0xa8",
      "ExpectedArm64ASM": [
        "and w26, w4, #0x1",
        "cmp w26, #0x0 (0)"
      ]
    },
    "test ax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "and w26, w4, #0x1",
        "cmp w26, #0x0 (0)"
      ]
    },
    "test eax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "ands w26, w4, #0x1",
        "cfinv"
      ]
    },
    "test rax, 1": {
      "ExpectedInstructionCount": 2,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "ands x26, x4, #0x1",
        "cfinv"
      ]
    },
    "test al, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0xa8",
      "ExpectedArm64ASM": [
        "cmn wzr, w4, lsl #24",
        "cfinv",
        "mov x26, x4"
      ]
    },
    "test ax, -1": {
      "ExpectedInstructionCount": 3,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "cmn wzr, w4, lsl #16",
        "cfinv",
        "mov x26, x4"
      ]
    },
    "test eax, -1": {
      "ExpectedInstructionCount": 1,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "subs w26, w4, #0x0 (0)"
      ]
    },
    "test rax, -1": {
      "ExpectedInstructionCount": 1,
      "Comment": "0xa9",
      "ExpectedArm64ASM": [
        "subs x26, x4, #0x0 (0)"
      ]
    },
    "scasb": {
      "ExpectedInstructionCount": 7,
      "Comment": "0xae",
      "ExpectedArm64ASM": [
        "ldrb w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20"
      ]
    },
    "scasw": {
      "ExpectedInstructionCount": 7,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrh w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #1"
      ]
    },
    "scasd": {
      "ExpectedInstructionCount": 5,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldr w20, [x11]",
        "eor x27, x4, x20",
        "subs w26, w4, w20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #2"
      ]
    },
    "scasq": {
      "ExpectedInstructionCount": 5,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldr x20, [x11]",
        "eor x27, x4, x20",
        "subs x26, x4, x20",
        "ldrsb x20, [x28, #1018]",
        "add x11, x11, x20, lsl #3"
      ]
    },
    "repz scasb": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xae",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x2c",
        "cbz x7, #+0x24",
        "ldrb w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "b.eq #-0x20",
        "b #+0x28",
        "cbz x7, #+0x24",
        "ldrb w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "b.eq #-0x20"
      ]
    },
    "repz scasw": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x2c",
        "cbz x7, #+0x24",
        "ldrh w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "b.eq #-0x20",
        "b #+0x28",
        "cbz x7, #+0x24",
        "ldrh w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "b.eq #-0x20"
      ]
    },
    "repz scasd": {
      "ExpectedInstructionCount": 19,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "cbz x7, #+0x1c",
        "ldr w20, [x11]",
        "eor x27, x4, x20",
        "subs w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "b.eq #-0x18",
        "b #+0x20",
        "cbz x7, #+0x1c",
        "ldr w20, [x11]",
        "eor x27, x4, x20",
        "subs w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "b.eq #-0x18"
      ]
    },
    "repz scasq": {
      "ExpectedInstructionCount": 19,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "cbz x7, #+0x1c",
        "ldr x20, [x11]",
        "eor x27, x4, x20",
        "subs x26, x4, x20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "b.eq #-0x18",
        "b #+0x20",
        "cbz x7, #+0x1c",
        "ldr x20, [x11]",
        "eor x27, x4, x20",
        "subs x26, x4, x20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "b.eq #-0x18"
      ]
    },
    "repnz scasb": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xae",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x2c",
        "cbz x7, #+0x24",
        "ldrb w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x1 (1)",
        "b.ne #-0x20",
        "b #+0x28",
        "cbz x7, #+0x24",
        "ldrb w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #24",
        "cmp w0, w20, lsl #24",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x1 (1)",
        "b.ne #-0x20"
      ]
    },
    "repnz scasw": {
      "ExpectedInstructionCount": 23,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x2c",
        "cbz x7, #+0x24",
        "ldrh w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x2 (2)",
        "b.ne #-0x20",
        "b #+0x28",
        "cbz x7, #+0x24",
        "ldrh w20, [x11]",
        "eor x27, x4, x20",
        "lsl w0, w4, #16",
        "cmp w0, w20, lsl #16",
        "sub w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x2 (2)",
        "b.ne #-0x20"
      ]
    },
    "repnz scasd": {
      "ExpectedInstructionCount": 19,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "cbz x7, #+0x1c",
        "ldr w20, [x11]",
        "eor x27, x4, x20",
        "subs w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x4 (4)",
        "b.ne #-0x18",
        "b #+0x20",
        "cbz x7, #+0x1c",
        "ldr w20, [x11]",
        "eor x27, x4, x20",
        "subs w26, w4, w20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x4 (4)",
        "b.ne #-0x18"
      ]
    },
    "repnz scasq": {
      "ExpectedInstructionCount": 19,
      "Comment": "0xaf",
      "ExpectedArm64ASM": [
        "ldrsb x20, [x28, #1018]",
        "lsr x20, x20, #63",
        "cbz x20, #+0x8",
        "b #+0x24",
        "cbz x7, #+0x1c",
        "ldr x20, [x11]",
        "eor x27, x4, x20",
        "subs x26, x4, x20",
        "sub x7, x7, #0x1 (1)",
        "add x11, x11, #0x8 (8)",
        "b.ne #-0x18",
        "b #+0x20",
        "cbz x7, #+0x1c",
        "ldr x20, [x11]",
        "eor x27, x4, x20",
        "subs x26, x4, x20",
        "sub x7, x7, #0x1 (1)",
        "sub x11, x11, #0x8 (8)",
        "b.ne #-0x18"
      ]
    },
    "cmc": {
      "ExpectedInstructionCount": 1,
      "Comment": "0xf5",
      "ExpectedArm64ASM": [
        "cfinv"
      ]
    },
    "clc": {
      "ExpectedInstructionCount": 2,
      "Comment": "0xf8",
      "ExpectedArm64ASM": [
        "mov w20, #0x1",
        "rmif x20, #63, #nzCv"
      ]
    },
    "stc": {
      "ExpectedInstructionCount": 1,
      "Comment": "0xf9",
      "ExpectedArm64ASM": [
        "rmif xzr, #63, #nzCv"
      ]
    }
  }
}