FEX-Emu--FEX/unittests/InstructionCountCI/Crypto/H0F38.json

{
  "Features": {
    "Bitness": 64,
    "EnabledHostFeatures": [
      "CRYPTO"
    ],
    "DisabledHostFeatures": [
      "SVE128",
      "SVE256",
      "AFP"
    ],
    "BinaryCacheVersion": 12
  },
  "Instructions": {
    "sha1nexte xmm0, xmm1": {
      "ExpectedInstructionCount": 6,
      "Comment": [
        "0x66 0x0f 0x38 0xc8"
      ],
      "ExpectedArm64ASM": [
        "dup v2.4s, v16.s[3]",
        "sha1h s2, s2",
        "dup v2.4s, v2.s[0]",
        "add v2.4s, v17.4s, v2.4s",
        "mov v16.16b, v17.16b",
        "mov v16.s[3], v2.s[3]"
      ]
    },
    "sha1msg2 xmm0, xmm1": {
      "ExpectedInstructionCount": 6,
      "Comment": [
        "0x66 0x0f 0x38 0xca"
      ],
      "ExpectedArm64ASM": [
        "ldr x0, [x28, #2736]",
        "ldr q2, [x0, #432]",
        "tbl v3.16b, {v16.16b}, v2.16b",
        "tbl v4.16b, {v17.16b}, v2.16b",
        "sha1su1 v3.4s, v4.4s",
        "tbl v16.16b, {v3.16b}, v2.16b"
      ]
    },
    "sha256rnds2 xmm0, xmm1": {
      "ExpectedInstructionCount": 10,
      "Comment": [
        "0x66 0x0f 0x38 0xcb"
      ],
      "ExpectedArm64ASM": [
        "zip2 v2.2d, v17.2d, v16.2d",
        "rev64 v2.4s, v2.4s",
        "zip1 v3.2d, v17.2d, v16.2d",
        "rev64 v3.4s, v3.4s",
        "dup v4.2d, v16.d[0]",
        "mov v5.16b, v2.16b",
        "sha256h q5, q3, v4.4s",
        "sha256h2 q3, q2, v4.4s",
        "zip2 v2.2d, v3.2d, v5.2d",
        "rev64 v16.4s, v2.4s"
      ]
    },
    "sha256msg1 xmm0, xmm1": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0x66 0x0f 0x38 0xcc"
      ],
      "ExpectedArm64ASM": [
        "sha256su0 v16.4s, v17.4s"
      ]
    },
    "sha256msg2 xmm0, xmm1": {
      "ExpectedInstructionCount": 5,
      "Comment": [
        "0x66 0x0f 0x38 0xcd"
      ],
      "ExpectedArm64ASM": [
        "ext v2.16b, v16.16b, v16.16b, #12",
        "dup v3.4s, v16.s[3]",
        "zip2 v3.2d, v3.2d, v17.2d",
        "movi v16.2d, #0x0",
        "sha256su1 v16.4s, v2.4s, v3.4s"
      ]
    },
    "aesimc xmm0, xmm1": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0x66 0x0f 0x38 0xdb"
      ],
      "ExpectedArm64ASM": [
        "aesimc v16.16b, v17.16b"
      ]
    },
    "aesenc xmm0, xmm1": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x66 0x0f 0x38 0xdc"
      ],
      "ExpectedArm64ASM": [
        "movi v2.2d, #0x0",
        "aese v16.16b, v2.16b",
        "aesmc v16.16b, v16.16b",
        "eor v16.16b, v16.16b, v17.16b"
      ]
    },
    "aesenclast xmm0, xmm1": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x66 0x0f 0x38 0xdd"
      ],
      "ExpectedArm64ASM": [
        "movi v2.2d, #0x0",
        "aese v16.16b, v2.16b",
        "eor v16.16b, v16.16b, v17.16b"
      ]
    },
    "aesdec xmm0, xmm1": {
      "ExpectedInstructionCount": 4,
      "Comment": [
        "0x66 0x0f 0x38 0xde"
      ],
      "ExpectedArm64ASM": [
        "movi v2.2d, #0x0",
        "aesd v16.16b, v2.16b",
        "aesimc v16.16b, v16.16b",
        "eor v16.16b, v16.16b, v17.16b"
      ]
    },
    "aesdeclast xmm0, xmm1": {
      "ExpectedInstructionCount": 3,
      "Comment": [
        "0x66 0x0f 0x38 0xdf"
      ],
      "ExpectedArm64ASM": [
        "movi v2.2d, #0x0",
        "aesd v16.16b, v2.16b",
        "eor v16.16b, v16.16b, v17.16b"
      ]
    },
    "crc32 eax, bl": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x38 0xf0"
      ],
      "ExpectedArm64ASM": [
        "crc32cb w4, w4, w6"
      ]
    },
    "crc32 eax, bh": {
      "ExpectedInstructionCount": 2,
      "Comment": [
        "0xf2 0x0f 0x38 0xf0"
      ],
      "ExpectedArm64ASM": [
        "lsr w20, w6, #8",
        "crc32cb w4, w4, w20"
      ]
    },
    "crc32 eax, bx": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x38 0xf1"
      ],
      "ExpectedArm64ASM": [
        "crc32ch w4, w4, w6"
      ]
    },
    "crc32 eax, ebx": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x38 0xf1"
      ],
      "ExpectedArm64ASM": [
        "crc32cw w4, w4, w6"
      ]
    },
    "crc32 rax, bl": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x38 0xf0"
      ],
      "ExpectedArm64ASM": [
        "crc32cb w4, w4, w6"
      ]
    },
    "crc32 rax, rbx": {
      "ExpectedInstructionCount": 1,
      "Comment": [
        "0xf2 0x0f 0x38 0xf1"
      ],
      "ExpectedArm64ASM": [
        "crc32cx w4, w4, x6"
      ]
    }
  }
}