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FEX-Emu--FEX/unittests/InstructionCountCI/AVX128/VEX_map2_SVE128.json
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Simon Scherer fd64ea54fe InstcountCI: Update
2026-09-04 07:32:09 +02:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [
"SVE128"
],
"DisabledHostFeatures": [
"AFP",
"FLAGM",
"FLAGM2",
"SVE256"
],
"BinaryCacheVersion": 12
},
"Instructions": {
"vmovntdqa xmm0, [rax]": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0x2a 128-bit"
],
"ExpectedArm64ASM": [
"ldnt1b {z16.b}, p6/z, [x4]",
"stp xzr, xzr, [x28, #192]"
]
},
"vmovntdqa ymm0, [rax]": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x2a 256-bit"
],
"ExpectedArm64ASM": [
"ldnt1b {z16.b}, p6/z, [x4]",
"ldnt1b {z2.b}, p6/z, [x4, #1, mul vl]",
"str q2, [x28, #192]"
]
},
"vmaskmovps xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 2 0b01 0x2c 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z17.s, #0",
"ld1w {z16.s}, p0/z, [x4]",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #192]"
]
},
"vmaskmovps ymm0, ymm1, [rax]": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x2c 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z17.s, #0",
"ld1w {z16.s}, p0/z, [x4]",
"cmplt p0.s, p6/z, z2.s, #0",
"ld1w {z2.s}, p0/z, [x4, #1, mul vl]",
"msr nzcv, x20",
"str q2, [x28, #192]"
]
},
"vmaskmovpd xmm0, xmm1, [rax]": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 2 0b01 0x2d 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z17.d, #0",
"ld1d {z16.d}, p0/z, [x4]",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #192]"
]
},
"vmaskmovpd ymm0, ymm1, [rax]": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x2d 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z17.d, #0",
"ld1d {z16.d}, p0/z, [x4]",
"cmplt p0.d, p6/z, z2.d, #0",
"ld1d {z2.d}, p0/z, [x4, #1, mul vl]",
"msr nzcv, x20",
"str q2, [x28, #192]"
]
},
"vmaskmovps [rax], xmm0, xmm1": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0x2e 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z16.s, #0",
"st1w {z17.s}, p0, [x4]",
"msr nzcv, x20"
]
},
"vmaskmovps [rax], ymm0, ymm1": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x2e 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z16.s, #0",
"st1w {z17.s}, p0, [x4]",
"cmplt p0.s, p6/z, z2.s, #0",
"st1w {z3.s}, p0, [x4, #1, mul vl]",
"msr nzcv, x20"
]
},
"vmaskmovpd [rax], xmm0, xmm1": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0x2f 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z16.d, #0",
"st1d {z17.d}, p0, [x4]",
"msr nzcv, x20"
]
},
"vmaskmovpd [rax], ymm0, ymm1": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x2f 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z16.d, #0",
"st1d {z17.d}, p0, [x4]",
"cmplt p0.d, p6/z, z2.d, #0",
"st1d {z3.d}, p0, [x4, #1, mul vl]",
"msr nzcv, x20"
]
},
"vpgatherdd xmm0, [xmm1*1 + rax], xmm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"ld1w {z0.s}, p0/z, [x4, z17.s, sxtw]",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdd xmm0, [xmm1*2 + rax], xmm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sshll2 v2.2d, v17.4s, #1",
"sshll v3.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdd xmm0, [xmm1*4 + rax], xmm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"ld1w {z0.s}, p0/z, [x4, z17.s, sxtw #2]",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdd xmm0, [xmm1*8 + rax], xmm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sshll2 v2.2d, v17.4s, #3",
"sshll v3.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdd ymm0, [ymm1*1 + rax], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"ld1w {z0.s}, p0/z, [x4, z17.s, sxtw]",
"mov z16.s, p0/m, z0.s",
"cmplt p0.s, p6/z, z4.s, #0",
"ld1w {z0.s}, p0/z, [x4, z3.s, sxtw]",
"mov z2.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdd ymm0, [ymm1*2 + rax], ymm2": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"sshll2 v5.2d, v17.4s, #1",
"sshll v6.2d, v17.2s, #1",
"sshll2 v7.2d, v3.4s, #1",
"sshll v3.2d, v3.2s, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z6.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z5.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"cmplt p0.s, p6/z, z4.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z7.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z2.s, p0/m, z0.s",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdd ymm0, [ymm1*4 + rax], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"ld1w {z0.s}, p0/z, [x4, z17.s, sxtw #2]",
"mov z16.s, p0/m, z0.s",
"cmplt p0.s, p6/z, z4.s, #0",
"ld1w {z0.s}, p0/z, [x4, z3.s, sxtw #2]",
"mov z2.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdd ymm0, [ymm1*8 + rax], ymm2": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"sshll2 v5.2d, v17.4s, #3",
"sshll v6.2d, v17.2s, #3",
"sshll2 v7.2d, v3.4s, #3",
"sshll v3.2d, v3.2s, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z6.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z5.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"cmplt p0.s, p6/z, z4.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z7.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z2.s, p0/m, z0.s",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdq xmm0, [xmm1*1 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sxtl v2.2d, v17.2s",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdq xmm0, [xmm1*2 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdq xmm0, [xmm1*4 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdq xmm0, [xmm1*8 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdq ymm0, [xmm1*1 + rax], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sxtl2 v4.2d, v17.4s",
"sxtl v5.2d, v17.2s",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [x4, z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdq ymm0, [xmm1*2 + rax], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #1",
"sshll v5.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [x4, z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdq ymm0, [xmm1*4 + rax], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #2",
"sshll v5.2d, v17.2s, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [x4, z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdq ymm0, [xmm1*8 + rax], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #3",
"sshll v5.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [x4, z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherqd xmm0, [xmm1*1 + rax], xmm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z17.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [xmm1*2 + rax], xmm2": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z2.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [xmm1*4 + rax], xmm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z17.d, lsl #2]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [xmm1*8 + rax], xmm2": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z2.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [ymm1*1 + rax], xmm2": {
"ExpectedInstructionCount": 13,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z17.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [ymm1*2 + rax], xmm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"shl v3.2d, v17.2d, #1",
"shl v2.2d, v2.2d, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [ymm1*4 + rax], xmm2": {
"ExpectedInstructionCount": 13,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z17.d, lsl #2]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d, lsl #2]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [ymm1*8 + rax], xmm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"shl v3.2d, v17.2d, #3",
"shl v2.2d, v2.2d, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqq xmm0, [xmm1*1 + rax], xmm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z17.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqq xmm0, [xmm1*2 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqq xmm0, [xmm1*4 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqq xmm0, [xmm1*8 + rax], xmm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z17.d, lsl #3]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqq ymm0, [ymm1*1 + rax], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z17.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [x4, z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherqq ymm0, [ymm1*2 + rax], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"shl v5.2d, v17.2d, #1",
"shl v3.2d, v3.2d, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [x4, z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherqq ymm0, [ymm1*4 + rax], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"shl v5.2d, v17.2d, #2",
"shl v3.2d, v3.2d, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [x4, z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherqq ymm0, [ymm1*8 + rax], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z17.d, lsl #3]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [x4, z3.d, lsl #3]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdps xmm0, [xmm1*1 + rax], xmm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"ld1w {z0.s}, p0/z, [x4, z17.s, sxtw]",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdps xmm0, [xmm1*2 + rax], xmm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sshll2 v2.2d, v17.4s, #1",
"sshll v3.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdps xmm0, [xmm1*4 + rax], xmm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"ld1w {z0.s}, p0/z, [x4, z17.s, sxtw #2]",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdps xmm0, [xmm1*8 + rax], xmm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sshll2 v2.2d, v17.4s, #3",
"sshll v3.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdps ymm0, [ymm1*1 + rax], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"ld1w {z0.s}, p0/z, [x4, z17.s, sxtw]",
"mov z16.s, p0/m, z0.s",
"cmplt p0.s, p6/z, z4.s, #0",
"ld1w {z0.s}, p0/z, [x4, z3.s, sxtw]",
"mov z2.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdps ymm0, [ymm1*2 + rax], ymm2": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"sshll2 v5.2d, v17.4s, #1",
"sshll v6.2d, v17.2s, #1",
"sshll2 v7.2d, v3.4s, #1",
"sshll v3.2d, v3.2s, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z6.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z5.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"cmplt p0.s, p6/z, z4.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z7.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z2.s, p0/m, z0.s",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdps ymm0, [ymm1*4 + rax], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"ld1w {z0.s}, p0/z, [x4, z17.s, sxtw #2]",
"mov z16.s, p0/m, z0.s",
"cmplt p0.s, p6/z, z4.s, #0",
"ld1w {z0.s}, p0/z, [x4, z3.s, sxtw #2]",
"mov z2.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdps ymm0, [ymm1*8 + rax], ymm2": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"sshll2 v5.2d, v17.4s, #3",
"sshll v6.2d, v17.2s, #3",
"sshll2 v7.2d, v3.4s, #3",
"sshll v3.2d, v3.2s, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z6.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z5.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"cmplt p0.s, p6/z, z4.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z7.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z2.s, p0/m, z0.s",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdpd xmm0, [xmm1*1 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sxtl v2.2d, v17.2s",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdpd xmm0, [xmm1*2 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdpd xmm0, [xmm1*4 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdpd xmm0, [xmm1*8 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdpd ymm0, [xmm1*1 + rax], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sxtl2 v4.2d, v17.4s",
"sxtl v5.2d, v17.2s",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [x4, z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdpd ymm0, [xmm1*2 + rax], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #1",
"sshll v5.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [x4, z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdpd ymm0, [xmm1*4 + rax], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #2",
"sshll v5.2d, v17.2s, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [x4, z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdpd ymm0, [xmm1*8 + rax], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #3",
"sshll v5.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [x4, z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherqps xmm0, [xmm1*1 + rax], xmm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z17.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [xmm1*2 + rax], xmm2": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z2.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [xmm1*4 + rax], xmm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z17.d, lsl #2]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [xmm1*8 + rax], xmm2": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z2.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [ymm1*1 + rax], xmm2": {
"ExpectedInstructionCount": 13,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z17.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [ymm1*2 + rax], xmm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"shl v3.2d, v17.2d, #1",
"shl v2.2d, v2.2d, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [ymm1*4 + rax], xmm2": {
"ExpectedInstructionCount": 13,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z17.d, lsl #2]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d, lsl #2]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [ymm1*8 + rax], xmm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"shl v3.2d, v17.2d, #3",
"shl v2.2d, v2.2d, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [x4, z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [x4, z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqpd xmm0, [xmm1*1 + rax], xmm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z17.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqpd xmm0, [xmm1*2 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqpd xmm0, [xmm1*4 + rax], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqpd xmm0, [xmm1*8 + rax], xmm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z17.d, lsl #3]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqpd ymm0, [ymm1*1 + rax], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z17.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [x4, z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherqpd ymm0, [ymm1*2 + rax], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"shl v5.2d, v17.2d, #1",
"shl v3.2d, v3.2d, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [x4, z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherqpd ymm0, [ymm1*4 + rax], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"shl v5.2d, v17.2d, #2",
"shl v3.2d, v3.2d, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [x4, z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherqpd ymm0, [ymm1*8 + rax], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [x4, z17.d, lsl #3]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [x4, z3.d, lsl #3]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdd xmm0, [xmm1*2], xmm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sshll2 v2.2d, v17.4s, #1",
"sshll v3.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdd xmm0, [xmm1*4], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"mov w0, #0x0",
"ld1w {z0.s}, p0/z, [x0, z17.s, sxtw #2]",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdd xmm0, [xmm1*8], xmm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sshll2 v2.2d, v17.4s, #3",
"sshll v3.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdd ymm0, [ymm1*1], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"ld1w {z0.s}, p0/z, [z17.s]",
"mov z16.s, p0/m, z0.s",
"cmplt p0.s, p6/z, z4.s, #0",
"ld1w {z0.s}, p0/z, [z3.s]",
"mov z2.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdd ymm0, [ymm1*2], ymm2": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"sshll2 v5.2d, v17.4s, #1",
"sshll v6.2d, v17.2s, #1",
"sshll2 v7.2d, v3.4s, #1",
"sshll v3.2d, v3.2s, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z6.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z5.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"cmplt p0.s, p6/z, z4.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z7.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z2.s, p0/m, z0.s",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdd ymm0, [ymm1*4], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"mov w0, #0x0",
"ld1w {z0.s}, p0/z, [x0, z17.s, sxtw #2]",
"mov z16.s, p0/m, z0.s",
"cmplt p0.s, p6/z, z4.s, #0",
"mov w0, #0x0",
"ld1w {z0.s}, p0/z, [x0, z3.s, sxtw #2]",
"mov z2.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdd ymm0, [ymm1*8], ymm2": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"sshll2 v5.2d, v17.4s, #3",
"sshll v6.2d, v17.2s, #3",
"sshll2 v7.2d, v3.4s, #3",
"sshll v3.2d, v3.2s, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z6.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z5.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"cmplt p0.s, p6/z, z4.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z7.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z2.s, p0/m, z0.s",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdq xmm0, [xmm1*1], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sxtl v2.2d, v17.2s",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdq xmm0, [xmm1*2], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdq xmm0, [xmm1*4], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdq xmm0, [xmm1*8], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x90 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherdq ymm0, [xmm1*1], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sxtl2 v4.2d, v17.4s",
"sxtl v5.2d, v17.2s",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdq ymm0, [xmm1*2], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #1",
"sshll v5.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdq ymm0, [xmm1*4], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #2",
"sshll v5.2d, v17.2s, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherdq ymm0, [xmm1*8], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x90 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #3",
"sshll v5.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherqd xmm0, [xmm1*1], xmm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z17.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [xmm1*2], xmm2": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z2.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [xmm1*4], xmm2": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #2",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z2.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [xmm1*8], xmm2": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z2.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [ymm1*1], xmm2": {
"ExpectedInstructionCount": 13,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z17.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [ymm1*2], xmm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"shl v3.2d, v17.2d, #1",
"shl v2.2d, v2.2d, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [ymm1*4], xmm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"shl v3.2d, v17.2d, #2",
"shl v2.2d, v2.2d, #2",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqd xmm0, [ymm1*8], xmm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"shl v3.2d, v17.2d, #3",
"shl v2.2d, v2.2d, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqq xmm0, [xmm1*1], xmm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z17.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqq xmm0, [xmm1*2], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqq xmm0, [xmm1*4], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqq xmm0, [xmm1*8], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x91 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"mov w0, #0x0",
"ld1d {z0.d}, p0/z, [x0, z17.d, lsl #3]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vpgatherqq ymm0, [ymm1*1], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z17.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherqq ymm0, [ymm1*2], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"shl v5.2d, v17.2d, #1",
"shl v3.2d, v3.2d, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherqq ymm0, [ymm1*4], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"shl v5.2d, v17.2d, #2",
"shl v3.2d, v3.2d, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vpgatherqq ymm0, [ymm1*8], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x91 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"mov w0, #0x0",
"ld1d {z0.d}, p0/z, [x0, z17.d, lsl #3]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"mov w0, #0x0",
"ld1d {z0.d}, p0/z, [x0, z3.d, lsl #3]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdps xmm0, [xmm1*1], xmm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"ld1w {z0.s}, p0/z, [z17.s]",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdps xmm0, [xmm1*2], xmm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sshll2 v2.2d, v17.4s, #1",
"sshll v3.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdps xmm0, [xmm1*4], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"mov w0, #0x0",
"ld1w {z0.s}, p0/z, [x0, z17.s, sxtw #2]",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdps xmm0, [xmm1*8], xmm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sshll2 v2.2d, v17.4s, #3",
"sshll v3.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdps ymm0, [ymm1*1], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"ld1w {z0.s}, p0/z, [z17.s]",
"mov z16.s, p0/m, z0.s",
"cmplt p0.s, p6/z, z4.s, #0",
"ld1w {z0.s}, p0/z, [z3.s]",
"mov z2.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdps ymm0, [ymm1*2], ymm2": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"sshll2 v5.2d, v17.4s, #1",
"sshll v6.2d, v17.2s, #1",
"sshll2 v7.2d, v3.4s, #1",
"sshll v3.2d, v3.2s, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z6.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z5.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"cmplt p0.s, p6/z, z4.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z7.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z2.s, p0/m, z0.s",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdps ymm0, [ymm1*4], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"mov w0, #0x0",
"ld1w {z0.s}, p0/z, [x0, z17.s, sxtw #2]",
"mov z16.s, p0/m, z0.s",
"cmplt p0.s, p6/z, z4.s, #0",
"mov w0, #0x0",
"ld1w {z0.s}, p0/z, [x0, z3.s, sxtw #2]",
"mov z2.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdps ymm0, [ymm1*8], ymm2": {
"ExpectedInstructionCount": 26,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"sshll2 v5.2d, v17.4s, #3",
"sshll v6.2d, v17.2s, #3",
"sshll2 v7.2d, v3.4s, #3",
"sshll v3.2d, v3.2s, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z6.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z5.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"cmplt p0.s, p6/z, z4.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z7.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z2.s, p0/m, z0.s",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdpd xmm0, [xmm1*1], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sxtl v2.2d, v17.2s",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdpd xmm0, [xmm1*2], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdpd xmm0, [xmm1*4], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdpd xmm0, [xmm1*8], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x92 128-bit"
],
"ExpectedArm64ASM": [
"sshll v2.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherdpd ymm0, [xmm1*1], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sxtl2 v4.2d, v17.4s",
"sxtl v5.2d, v17.2s",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdpd ymm0, [xmm1*2], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #1",
"sshll v5.2d, v17.2s, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdpd ymm0, [xmm1*4], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #2",
"sshll v5.2d, v17.2s, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherdpd ymm0, [xmm1*8], ymm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x92 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #224]",
"sshll2 v4.2d, v17.4s, #3",
"sshll v5.2d, v17.2s, #3",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z3.d, #0",
"ld1d {z0.d}, p0/z, [z4.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherqps xmm0, [xmm1*1], xmm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z17.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [xmm1*2], xmm2": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z2.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [xmm1*4], xmm2": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #2",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z2.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [xmm1*8], xmm2": {
"ExpectedInstructionCount": 12,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z2.d]",
"xtn v0.2s, v0.2d",
"sel z2.s, p0, z0.s, z16.s",
"movi v18.2d, #0x0",
"zip1 v16.2d, v2.2d, v18.2d",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [ymm1*1], xmm2": {
"ExpectedInstructionCount": 13,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z17.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [ymm1*2], xmm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"shl v3.2d, v17.2d, #1",
"shl v2.2d, v2.2d, #1",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [ymm1*4], xmm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"shl v3.2d, v17.2d, #2",
"shl v2.2d, v2.2d, #2",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqps xmm0, [ymm1*8], xmm2": {
"ExpectedInstructionCount": 15,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #208]",
"shl v3.2d, v17.2d, #3",
"shl v2.2d, v2.2d, #3",
"mrs x20, nzcv",
"cmplt p0.s, p6/z, z18.s, #0",
"punpklo p1.h, p0.b",
"ld1w {z0.d}, p1/z, [z3.d]",
"punpkhi p1.h, p0.b",
"ld1w {z1.d}, p1/z, [z2.d]",
"uzp1 v0.4s, v0.4s, v1.4s",
"mov z16.s, p0/m, z0.s",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqpd xmm0, [xmm1*1], xmm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z17.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqpd xmm0, [xmm1*2], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqpd xmm0, [xmm1*4], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"shl v2.2d, v17.2d, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z2.d]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqpd xmm0, [xmm1*8], xmm2": {
"ExpectedInstructionCount": 9,
"Comment": [
"Map 2 0b01 0x93 128-bit"
],
"ExpectedArm64ASM": [
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"mov w0, #0x0",
"ld1d {z0.d}, p0/z, [x0, z17.d, lsl #3]",
"mov z16.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"stp xzr, xzr, [x28, #192]"
]
},
"vgatherqpd ymm0, [ymm1*1], ymm2": {
"ExpectedInstructionCount": 14,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z17.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherqpd ymm0, [ymm1*2], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"shl v5.2d, v17.2d, #1",
"shl v3.2d, v3.2d, #1",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherqpd ymm0, [ymm1*4], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"shl v5.2d, v17.2d, #2",
"shl v3.2d, v3.2d, #2",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"ld1d {z0.d}, p0/z, [z5.d]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"ld1d {z0.d}, p0/z, [z3.d]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vgatherqpd ymm0, [ymm1*8], ymm2": {
"ExpectedInstructionCount": 16,
"Comment": [
"Map 2 0b01 0x93 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mrs x20, nzcv",
"cmplt p0.d, p6/z, z18.d, #0",
"mov w0, #0x0",
"ld1d {z0.d}, p0/z, [x0, z17.d, lsl #3]",
"mov z16.d, p0/m, z0.d",
"cmplt p0.d, p6/z, z4.d, #0",
"mov w0, #0x0",
"ld1d {z0.d}, p0/z, [x0, z3.d, lsl #3]",
"mov z2.d, p0/m, z0.d",
"movi v18.2d, #0x0",
"msr nzcv, x20",
"stp xzr, xzr, [x28, #224]",
"str q2, [x28, #192]"
]
},
"vfmaddsub132ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3152]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v16.4s, v18.4s",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmaddsub132ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0x96 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3152]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v16.4s, v18.4s",
"mov v16.16b, v0.16b",
"eor v3.16b, v3.16b, v5.16b",
"fmla v3.4s, v2.4s, v4.4s",
"str q3, [x28, #192]"
]
},
"vfmaddsub132pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0x96 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3184]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v16.2d, v18.2d",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmaddsub132pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0x96 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3184]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v16.2d, v18.2d",
"mov v16.16b, v0.16b",
"eor v3.16b, v3.16b, v5.16b",
"fmla v3.2d, v2.2d, v4.2d",
"str q3, [x28, #192]"
]
},
"vfmsubadd132ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3216]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v16.4s, v18.4s",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsubadd132ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0x97 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3216]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v16.4s, v18.4s",
"mov v16.16b, v0.16b",
"eor v3.16b, v3.16b, v5.16b",
"fmla v3.4s, v2.4s, v4.4s",
"str q3, [x28, #192]"
]
},
"vfmsubadd132pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0x97 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3248]",
"eor v2.16b, v17.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v16.2d, v18.2d",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsubadd132pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0x97 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3248]",
"eor v6.16b, v17.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v16.2d, v18.2d",
"mov v16.16b, v0.16b",
"eor v3.16b, v3.16b, v5.16b",
"fmla v3.2d, v2.2d, v4.2d",
"str q3, [x28, #192]"
]
},
"vfmadd132ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0x98 128-bit"
],
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"fmla v0.4s, v16.4s, v18.4s",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmadd132ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x98 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov v0.16b, v17.16b",
"fmla v0.4s, v16.4s, v18.4s",
"mov v16.16b, v0.16b",
"fmla v3.4s, v2.4s, v4.4s",
"str q3, [x28, #192]"
]
},
"vfmadd132pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0x98 128-bit"
],
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"fmla v0.2d, v16.2d, v18.2d",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmadd132pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x98 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov v0.16b, v17.16b",
"fmla v0.2d, v16.2d, v18.2d",
"mov v16.16b, v0.16b",
"fmla v3.2d, v2.2d, v4.2d",
"str q3, [x28, #192]"
]
},
"vfmadd132ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x99 128-bit"
],
"ExpectedArm64ASM": [
"fmadd s0, s16, s18, s17",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmadd132sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x99 128-bit"
],
"ExpectedArm64ASM": [
"fmadd d0, d16, d18, d17",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub132ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0x9a 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, z17.d",
"fnmls z0.s, p6/m, z16.s, z18.s",
"mov z16.d, z0.d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub132ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x9a 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov z0.d, z17.d",
"fnmls z0.s, p6/m, z16.s, z18.s",
"mov z16.d, z0.d",
"fnmls z3.s, p6/m, z2.s, z4.s",
"str q3, [x28, #192]"
]
},
"vfmsub132pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0x9a 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, z17.d",
"fnmls z0.d, p6/m, z16.d, z18.d",
"mov z16.d, z0.d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub132pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x9a 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov z0.d, z17.d",
"fnmls z0.d, p6/m, z16.d, z18.d",
"mov z16.d, z0.d",
"fnmls z3.d, p6/m, z2.d, z4.d",
"str q3, [x28, #192]"
]
},
"vfmsub132ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9b 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub s0, s16, s18, s17",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub132sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9b 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub d0, d16, d18, d17",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd132ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0x9c 128-bit"
],
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"fmls v0.4s, v16.4s, v18.4s",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd132ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x9c 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov v0.16b, v17.16b",
"fmls v0.4s, v16.4s, v18.4s",
"mov v16.16b, v0.16b",
"fmls v3.4s, v2.4s, v4.4s",
"str q3, [x28, #192]"
]
},
"vfnmadd132pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0x9c 128-bit"
],
"ExpectedArm64ASM": [
"mov v0.16b, v17.16b",
"fmls v0.2d, v16.2d, v18.2d",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd132pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x9c 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov v0.16b, v17.16b",
"fmls v0.2d, v16.2d, v18.2d",
"mov v16.16b, v0.16b",
"fmls v3.2d, v2.2d, v4.2d",
"str q3, [x28, #192]"
]
},
"vfnmadd132ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9d 128-bit"
],
"ExpectedArm64ASM": [
"fmsub s0, s16, s18, s17",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd132sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9d 128-bit"
],
"ExpectedArm64ASM": [
"fmsub d0, d16, d18, d17",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub132ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0x9e 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, z17.d",
"fnmla z0.s, p6/m, z16.s, z18.s",
"mov z16.d, z0.d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub132ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x9e 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov z0.d, z17.d",
"fnmla z0.s, p6/m, z16.s, z18.s",
"mov z16.d, z0.d",
"fnmla z3.s, p6/m, z2.s, z4.s",
"str q3, [x28, #192]"
]
},
"vfnmsub132pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0x9e 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, z17.d",
"fnmla z0.d, p6/m, z16.d, z18.d",
"mov z16.d, z0.d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub132pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0x9e 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov z0.d, z17.d",
"fnmla z0.d, p6/m, z16.d, z18.d",
"mov z16.d, z0.d",
"fnmla z3.d, p6/m, z2.d, z4.d",
"str q3, [x28, #192]"
]
},
"vfnmsub132ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9f 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd s0, s16, s18, s17",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub132sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0x9f 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd d0, d16, d18, d17",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmadd213ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0xa8 128-bit"
],
"ExpectedArm64ASM": [
"mov v0.16b, v18.16b",
"fmla v0.4s, v17.4s, v16.4s",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmadd213ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0xa8 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov v0.16b, v18.16b",
"fmla v0.4s, v17.4s, v16.4s",
"mov v16.16b, v0.16b",
"fmla v4.4s, v3.4s, v2.4s",
"str q4, [x28, #192]"
]
},
"vfmadd213pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0xa8 128-bit"
],
"ExpectedArm64ASM": [
"mov v0.16b, v18.16b",
"fmla v0.2d, v17.2d, v16.2d",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmadd213pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0xa8 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov v0.16b, v18.16b",
"fmla v0.2d, v17.2d, v16.2d",
"mov v16.16b, v0.16b",
"fmla v4.2d, v3.2d, v2.2d",
"str q4, [x28, #192]"
]
},
"vfmadd213ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xa9 128-bit"
],
"ExpectedArm64ASM": [
"fmadd s0, s17, s16, s18",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmadd213sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xa9 128-bit"
],
"ExpectedArm64ASM": [
"fmadd d0, d17, d16, d18",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub213ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0xaa 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, z18.d",
"fnmls z0.s, p6/m, z17.s, z16.s",
"mov z16.d, z0.d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub213ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0xaa 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov z0.d, z18.d",
"fnmls z0.s, p6/m, z17.s, z16.s",
"mov z16.d, z0.d",
"fnmls z4.s, p6/m, z3.s, z2.s",
"str q4, [x28, #192]"
]
},
"vfmsub213pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0xaa 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, z18.d",
"fnmls z0.d, p6/m, z17.d, z16.d",
"mov z16.d, z0.d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub213pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0xaa 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov z0.d, z18.d",
"fnmls z0.d, p6/m, z17.d, z16.d",
"mov z16.d, z0.d",
"fnmls z4.d, p6/m, z3.d, z2.d",
"str q4, [x28, #192]"
]
},
"vfmsub213ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xab 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub s0, s17, s16, s18",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub213sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xab 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub d0, d17, d16, d18",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd213ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0xac 128-bit"
],
"ExpectedArm64ASM": [
"mov v0.16b, v18.16b",
"fmls v0.4s, v17.4s, v16.4s",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd213ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0xac 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov v0.16b, v18.16b",
"fmls v0.4s, v17.4s, v16.4s",
"mov v16.16b, v0.16b",
"fmls v4.4s, v3.4s, v2.4s",
"str q4, [x28, #192]"
]
},
"vfnmadd213pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0xac 128-bit"
],
"ExpectedArm64ASM": [
"mov v0.16b, v18.16b",
"fmls v0.2d, v17.2d, v16.2d",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd213pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0xac 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov v0.16b, v18.16b",
"fmls v0.2d, v17.2d, v16.2d",
"mov v16.16b, v0.16b",
"fmls v4.2d, v3.2d, v2.2d",
"str q4, [x28, #192]"
]
},
"vfnmadd213ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xad 128-bit"
],
"ExpectedArm64ASM": [
"fmsub s0, s17, s16, s18",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd213sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xad 128-bit"
],
"ExpectedArm64ASM": [
"fmsub d0, d17, d16, d18",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub213ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0xae 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, z18.d",
"fnmla z0.s, p6/m, z17.s, z16.s",
"mov z16.d, z0.d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub213ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0xae 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov z0.d, z18.d",
"fnmla z0.s, p6/m, z17.s, z16.s",
"mov z16.d, z0.d",
"fnmla z4.s, p6/m, z3.s, z2.s",
"str q4, [x28, #192]"
]
},
"vfnmsub213pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 4,
"Comment": [
"Map 2 0b01 0xae 128-bit"
],
"ExpectedArm64ASM": [
"mov z0.d, z18.d",
"fnmla z0.d, p6/m, z17.d, z16.d",
"mov z16.d, z0.d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub213pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 8,
"Comment": [
"Map 2 0b01 0xae 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"mov z0.d, z18.d",
"fnmla z0.d, p6/m, z17.d, z16.d",
"mov z16.d, z0.d",
"fnmla z4.d, p6/m, z3.d, z2.d",
"str q4, [x28, #192]"
]
},
"vfnmsub213ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xaf 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd s0, s17, s16, s18",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub213sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xaf 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd d0, d17, d16, d18",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmadd231ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xb8 128-bit"
],
"ExpectedArm64ASM": [
"fmla v16.4s, v17.4s, v18.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmadd231ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xb8 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"fmla v16.4s, v17.4s, v18.4s",
"fmla v2.4s, v3.4s, v4.4s",
"str q2, [x28, #192]"
]
},
"vfmadd231pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xb8 128-bit"
],
"ExpectedArm64ASM": [
"fmla v16.2d, v17.2d, v18.2d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmadd231pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xb8 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"fmla v16.2d, v17.2d, v18.2d",
"fmla v2.2d, v3.2d, v4.2d",
"str q2, [x28, #192]"
]
},
"vfmadd231ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xb9 128-bit"
],
"ExpectedArm64ASM": [
"fmadd s0, s17, s18, s16",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmadd231sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xb9 128-bit"
],
"ExpectedArm64ASM": [
"fmadd d0, d17, d18, d16",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub231ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xba 128-bit"
],
"ExpectedArm64ASM": [
"fnmls z16.s, p6/m, z17.s, z18.s",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub231ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xba 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"fnmls z16.s, p6/m, z17.s, z18.s",
"fnmls z2.s, p6/m, z3.s, z4.s",
"str q2, [x28, #192]"
]
},
"vfmsub231pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xba 128-bit"
],
"ExpectedArm64ASM": [
"fnmls z16.d, p6/m, z17.d, z18.d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub231pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xba 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"fnmls z16.d, p6/m, z17.d, z18.d",
"fnmls z2.d, p6/m, z3.d, z4.d",
"str q2, [x28, #192]"
]
},
"vfmsub231ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xbb 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub s0, s17, s18, s16",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsub231sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xbb 128-bit"
],
"ExpectedArm64ASM": [
"fnmsub d0, d17, d18, d16",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd231ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xbc 128-bit"
],
"ExpectedArm64ASM": [
"fmls v16.4s, v17.4s, v18.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd231ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xbc 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"fmls v16.4s, v17.4s, v18.4s",
"fmls v2.4s, v3.4s, v4.4s",
"str q2, [x28, #192]"
]
},
"vfnmadd231pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xbc 128-bit"
],
"ExpectedArm64ASM": [
"fmls v16.2d, v17.2d, v18.2d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd231pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xbc 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"fmls v16.2d, v17.2d, v18.2d",
"fmls v2.2d, v3.2d, v4.2d",
"str q2, [x28, #192]"
]
},
"vfnmadd231ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xbd 128-bit"
],
"ExpectedArm64ASM": [
"fmsub s0, s17, s18, s16",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmadd231sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xbd 128-bit"
],
"ExpectedArm64ASM": [
"fmsub d0, d17, d18, d16",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub231ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xbe 128-bit"
],
"ExpectedArm64ASM": [
"fnmla z16.s, p6/m, z17.s, z18.s",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub231ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xbe 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"fnmla z16.s, p6/m, z17.s, z18.s",
"fnmla z2.s, p6/m, z3.s, z4.s",
"str q2, [x28, #192]"
]
},
"vfnmsub231pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 2,
"Comment": [
"Map 2 0b01 0xbe 128-bit"
],
"ExpectedArm64ASM": [
"fnmla z16.d, p6/m, z17.d, z18.d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub231pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xbe 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"fnmla z16.d, p6/m, z17.d, z18.d",
"fnmla z2.d, p6/m, z3.d, z4.d",
"str q2, [x28, #192]"
]
},
"vfnmsub231ss xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xbf 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd s0, s17, s18, s16",
"mov v16.s[0], v0.s[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfnmsub231sd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 3,
"Comment": [
"Map 2 0b01 0xbf 128-bit"
],
"ExpectedArm64ASM": [
"fnmadd d0, d17, d18, d16",
"mov v16.d[0], v0.d[0]",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmaddsub213ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3152]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v17.4s, v16.4s",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmaddsub213ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0xa6 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3152]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v17.4s, v16.4s",
"mov v16.16b, v0.16b",
"eor v4.16b, v4.16b, v5.16b",
"fmla v4.4s, v3.4s, v2.4s",
"str q4, [x28, #192]"
]
},
"vfmaddsub213pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xa6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3184]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v17.2d, v16.2d",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmaddsub213pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0xa6 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3184]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v17.2d, v16.2d",
"mov v16.16b, v0.16b",
"eor v4.16b, v4.16b, v5.16b",
"fmla v4.2d, v3.2d, v2.2d",
"str q4, [x28, #192]"
]
},
"vfmsubadd213ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3216]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.4s, v17.4s, v16.4s",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsubadd213ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0xa7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3216]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.4s, v17.4s, v16.4s",
"mov v16.16b, v0.16b",
"eor v4.16b, v4.16b, v5.16b",
"fmla v4.4s, v3.4s, v2.4s",
"str q4, [x28, #192]"
]
},
"vfmsubadd213pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 6,
"Comment": [
"Map 2 0b01 0xa7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3248]",
"eor v2.16b, v18.16b, v2.16b",
"mov v0.16b, v2.16b",
"fmla v0.2d, v17.2d, v16.2d",
"mov v16.16b, v0.16b",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsubadd213pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 11,
"Comment": [
"Map 2 0b01 0xa7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3248]",
"eor v6.16b, v18.16b, v5.16b",
"mov v0.16b, v6.16b",
"fmla v0.2d, v17.2d, v16.2d",
"mov v16.16b, v0.16b",
"eor v4.16b, v4.16b, v5.16b",
"fmla v4.2d, v3.2d, v2.2d",
"str q4, [x28, #192]"
]
},
"vfmaddsub231ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3152]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.4s, v17.4s, v18.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmaddsub231ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 10,
"Comment": [
"Map 2 0b01 0xb6 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3152]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.4s, v17.4s, v18.4s",
"eor v2.16b, v2.16b, v5.16b",
"fmla v2.4s, v3.4s, v4.4s",
"str q2, [x28, #192]"
]
},
"vfmaddsub231pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 2 0b01 0xb6 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3184]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.2d, v17.2d, v18.2d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmaddsub231pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 10,
"Comment": [
"Map 2 0b01 0xb6 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3184]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.2d, v17.2d, v18.2d",
"eor v2.16b, v2.16b, v5.16b",
"fmla v2.2d, v3.2d, v4.2d",
"str q2, [x28, #192]"
]
},
"vfmsubadd231ps xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3216]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.4s, v17.4s, v18.4s",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsubadd231ps ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 10,
"Comment": [
"Map 2 0b01 0xb7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3216]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.4s, v17.4s, v18.4s",
"eor v2.16b, v2.16b, v5.16b",
"fmla v2.4s, v3.4s, v4.4s",
"str q2, [x28, #192]"
]
},
"vfmsubadd231pd xmm0, xmm1, xmm2": {
"ExpectedInstructionCount": 5,
"Comment": [
"Map 2 0b01 0xb7 128-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #3248]",
"eor v2.16b, v16.16b, v2.16b",
"mov v16.16b, v2.16b",
"fmla v16.2d, v17.2d, v18.2d",
"stp xzr, xzr, [x28, #192]"
]
},
"vfmsubadd231pd ymm0, ymm1, ymm2": {
"ExpectedInstructionCount": 10,
"Comment": [
"Map 2 0b01 0xb7 256-bit"
],
"ExpectedArm64ASM": [
"ldr q2, [x28, #192]",
"ldr q3, [x28, #208]",
"ldr q4, [x28, #224]",
"ldr q5, [x28, #3248]",
"eor v6.16b, v16.16b, v5.16b",
"mov v16.16b, v6.16b",
"fmla v16.2d, v17.2d, v18.2d",
"eor v2.16b, v2.16b, v5.16b",
"fmla v2.2d, v3.2d, v4.2d",
"str q2, [x28, #192]"
]
}
}
}
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