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cf6b21564c225ea2a584a3025b76a63cef740183
FEX-Emu--FEX/unittests/InstructionCountCI/Primary_32Bit.json
T
Alyssa Rosenzweig cf6b21564c InstCountCI: disable flagm explicitly more 
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2023-11-09 09:40:51 -04:00

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{
"Features": {
"Bitness": 32,
"EnabledHostFeatures": [],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"FlagM",
"FlagM2"
]
},
"Instructions": {
"push es": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0x06",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #136]",
"str w20, [x8, #-4]!"
]
},
"pop es": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "0x07",
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #136]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #152]"
]
},
"push cs": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0x0e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #138]",
"str w20, [x8, #-4]!"
]
},
"push ss": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0x16",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #140]",
"str w20, [x8, #-4]!"
]
},
"pop ss": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "0x17",
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #140]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #160]"
]
},
"push ds": {
"ExpectedInstructionCount": 2,
"Optimal": "Yes",
"Comment": "0x1e",
"ExpectedArm64ASM": [
"ldrh w20, [x28, #142]",
"str w20, [x8, #-4]!"
]
},
"pop ds": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "0x1f",
"ExpectedArm64ASM": [
"ldr w20, [x8]",
"add x8, x8, #0x4 (4)",
"strh w20, [x28, #142]",
"ubfx w20, w20, #3, #13",
"add x0, x28, x20, lsl #2",
"ldr w20, [x0, #880]",
"str w20, [x28, #164]"
]
},
"daa": {
"ExpectedInstructionCount": 57,
"Optimal": "No",
"Comment": "0x27",
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx w21, w20, #29, #1",
"ldrb w22, [x28, #708]",
"ldrb w23, [x28, #706]",
"eor w22, w22, w23",
"ubfx w22, w22, #4, #1",
"uxtb w23, w4",
"and w20, w20, #0xdfffffff",
"str w20, [x28, #728]",
"and x20, x23, #0xf",
"cmp x20, #0x9 (9)",
"cset x20, hi",
"orr x20, x22, x20",
"cbnz x20, #+0x10",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"b #+0x28",
"add x20, x23, #0x6 (6)",
"bfxil w4, w20, #0, #8",
"ldr w20, [x28, #728]",
"ubfx w22, w20, #29, #1",
"orr x22, x21, x22",
"bfi w20, w22, #29, #1",
"mov w22, #0x10",
"strb w22, [x28, #708]",
"str w20, [x28, #728]",
"cmp x23, #0x99 (153)",
"cset x20, hi",
"orr x20, x21, x20",
"cbnz x20, #+0x14",
"ldr w20, [x28, #728]",
"and w20, w20, #0xdfffffff",
"str w20, [x28, #728]",
"b #+0x1c",
"uxtb w20, w4",
"add x20, x20, #0x60 (96)",
"bfxil w4, w20, #0, #8",
"ldr w20, [x28, #728]",
"orr w20, w20, #0x20000000",
"str w20, [x28, #728]",
"uxtb w20, w4",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"strb w20, [x28, #706]",
"ldrb w22, [x28, #708]",
"eor w20, w22, w20",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
},
"das": {
"ExpectedInstructionCount": 57,
"Optimal": "No",
"Comment": "0x2f",
"ExpectedArm64ASM": [
"ldr w20, [x28, #728]",
"ubfx w21, w20, #29, #1",
"ldrb w22, [x28, #708]",
"ldrb w23, [x28, #706]",
"eor w22, w22, w23",
"ubfx w22, w22, #4, #1",
"uxtb w23, w4",
"and w20, w20, #0xdfffffff",
"str w20, [x28, #728]",
"and x20, x23, #0xf",
"cmp x20, #0x9 (9)",
"cset x20, hi",
"orr x20, x22, x20",
"cbnz x20, #+0x10",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"b #+0x28",
"sub x20, x23, #0x6 (6)",
"bfxil w4, w20, #0, #8",
"ldr w20, [x28, #728]",
"ubfx w22, w20, #29, #1",
"orr x22, x21, x22",
"bfi w20, w22, #29, #1",
"mov w22, #0x10",
"strb w22, [x28, #708]",
"str w20, [x28, #728]",
"cmp x23, #0x99 (153)",
"cset x20, hi",
"orr x20, x21, x20",
"cbnz x20, #+0x14",
"ldr w20, [x28, #728]",
"and w20, w20, #0xdfffffff",
"str w20, [x28, #728]",
"b #+0x1c",
"uxtb w20, w4",
"sub x20, x20, #0x60 (96)",
"bfxil w4, w20, #0, #8",
"ldr w20, [x28, #728]",
"orr w20, w20, #0x20000000",
"str w20, [x28, #728]",
"uxtb w20, w4",
"and x21, x20, #0x80",
"cmp x21, #0x0 (0)",
"cset x21, hs",
"ldr w22, [x28, #728]",
"mov w0, w22",
"bfi w0, w21, #31, #1",
"mov w21, w0",
"and x22, x20, #0xff",
"cmp x22, #0x0 (0)",
"cset x22, eq",
"bfi w21, w22, #30, #1",
"strb w20, [x28, #706]",
"ldrb w22, [x28, #708]",
"eor w20, w22, w20",
"strb w20, [x28, #708]",
"str w21, [x28, #728]"
]
},
"aaa": {
"ExpectedInstructionCount": 26,
"Optimal": "No",
"Comment": "0x37",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"ldrb w21, [x28, #706]",
"eor w20, w20, w21",
"ubfx w20, w20, #4, #1",
"uxtb w21, w4",
"uxth w22, w4",
"and x21, x21, #0xf",
"cmp x21, #0x9 (9)",
"cset x21, hi",
"orr x20, x20, x21",
"cbnz x20, #+0x20",
"mov w20, #0xff0f",
"and x20, x22, x20",
"bfxil w4, w20, #0, #16",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"str w20, [x28, #728]",
"b #+0x24",
"add x20, x22, #0x106 (262)",
"mov w21, #0xff0f",
"and x20, x20, x21",
"bfxil w4, w20, #0, #16",
"mov w20, #0x20000000",
"mov w21, #0x10",
"strb w21, [x28, #708]",
"str w20, [x28, #728]"
]
},
"aas": {
"ExpectedInstructionCount": 27,
"Optimal": "No",
"Comment": "0x3f",
"ExpectedArm64ASM": [
"ldrb w20, [x28, #708]",
"ldrb w21, [x28, #706]",
"eor w20, w20, w21",
"ubfx w20, w20, #4, #1",
"uxtb w21, w4",
"uxth w22, w4",
"and x21, x21, #0xf",
"cmp x21, #0x9 (9)",
"cset x21, hi",
"orr x20, x20, x21",
"cbnz x20, #+0x20",
"mov w20, #0xff0f",
"and x20, x22, x20",
"bfxil w4, w20, #0, #16",
"mov w20, #0x0",
"strb w20, [x28, #708]",
"str w20, [x28, #728]",
"b #+0x28",
"sub x20, x22, #0x6 (6)",
"sub x20, x20, #0x100 (256)",
"mov w21, #0xff0f",
"and x20, x20, x21",
"bfxil w4, w20, #0, #16",
"mov w20, #0x20000000",
"mov w21, #0x10",
"strb w21, [x28, #708]",
"str w20, [x28, #728]"
]
},
"inc ax": {
"ExpectedInstructionCount": 15,
"Optimal": "No",
"Comment": "0x40",
"ExpectedArm64ASM": [
"uxth w20, w4",
"add w21, w20, #0x1 (1)",
"bfxil w4, w21, #0, #16",
"strb w20, [x28, #708]",
"strb w21, [x28, #706]",
"ldr w22, [x28, #728]",
"ubfx w22, w22, #29, #1",
"lsl w23, w21, #16",
"tst w23, w23",
"mrs x23, nzcv",
"bic w20, w21, w20",
"ubfx w20, w20, #15, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"str w20, [x28, #728]"
]
},
"inc eax": {
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x40",
"ExpectedArm64ASM": [
"mov w20, w4",
"add w4, w20, #0x1 (1)",
"strb w20, [x28, #708]",
"strb w4, [x28, #706]",
"ldr w21, [x28, #728]",
"ubfx w21, w21, #29, #1",
"cmn w20, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"str w20, [x28, #728]"
]
},
"dec ax": {
"ExpectedInstructionCount": 15,
"Optimal": "No",
"Comment": "0x48",
"ExpectedArm64ASM": [
"uxth w20, w4",
"sub w21, w20, #0x1 (1)",
"bfxil w4, w21, #0, #16",
"strb w20, [x28, #708]",
"strb w21, [x28, #706]",
"ldr w22, [x28, #728]",
"ubfx w22, w22, #29, #1",
"lsl w23, w21, #16",
"tst w23, w23",
"mrs x23, nzcv",
"bic w20, w20, w21",
"ubfx w20, w20, #15, #1",
"orr w20, w23, w20, lsl #28",
"orr w20, w20, w22, lsl #29",
"str w20, [x28, #728]"
]
},
"push ax": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x50",
"ExpectedArm64ASM": [
"strh w4, [x8, #-2]!"
]
},
"push eax": {
"ExpectedInstructionCount": 1,
"Optimal": "Yes",
"Comment": "0x50",
"ExpectedArm64ASM": [
"str w4, [x8, #-4]!"
]
},
"dec eax": {
"ExpectedInstructionCount": 10,
"Optimal": "No",
"Comment": "0x48",
"ExpectedArm64ASM": [
"mov w20, w4",
"sub w4, w20, #0x1 (1)",
"strb w20, [x28, #708]",
"strb w4, [x28, #706]",
"ldr w21, [x28, #728]",
"ubfx w21, w21, #29, #1",
"cmp w20, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"str w20, [x28, #728]"
]
},
"pusha": {
"ExpectedInstructionCount": 10,
"Optimal": "Yes",
"Comment": "0x60",
"ExpectedArm64ASM": [
"mov w20, w8",
"str w4, [x20, #-4]!",
"str w5, [x20, #-4]!",
"str w6, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w8, [x20, #-4]!",
"str w9, [x20, #-4]!",
"str w10, [x20, #-4]!",
"mov w8, w20",
"str w11, [x8, #-4]!"
]
},
"pushad": {
"ExpectedInstructionCount": 10,
"Optimal": "Yes",
"Comment": "0x60",
"ExpectedArm64ASM": [
"mov w20, w8",
"str w4, [x20, #-4]!",
"str w5, [x20, #-4]!",
"str w6, [x20, #-4]!",
"str w7, [x20, #-4]!",
"str w8, [x20, #-4]!",
"str w9, [x20, #-4]!",
"str w10, [x20, #-4]!",
"mov w8, w20",
"str w11, [x8, #-4]!"
]
},
"popa": {
"ExpectedInstructionCount": 14,
"Optimal": "No",
"Comment": "0x61",
"ExpectedArm64ASM": [
"ldr w11, [x8]",
"add x20, x8, #0x4 (4)",
"ldr w10, [x8, #4]",
"add x21, x20, #0x4 (4)",
"ldr w9, [x20, #4]",
"add x20, x21, #0x8 (8)",
"ldr w7, [x21, #8]",
"add x21, x20, #0x4 (4)",
"ldr w6, [x20, #4]",
"add x20, x21, #0x4 (4)",
"ldr w5, [x21, #4]",
"add x21, x20, #0x4 (4)",
"ldr w4, [x20, #4]",
"add x8, x21, #0x4 (4)"
]
},
"popad": {
"ExpectedInstructionCount": 14,
"Optimal": "No",
"Comment": "0x61",
"ExpectedArm64ASM": [
"ldr w11, [x8]",
"add x20, x8, #0x4 (4)",
"ldr w10, [x8, #4]",
"add x21, x20, #0x4 (4)",
"ldr w9, [x20, #4]",
"add x20, x21, #0x8 (8)",
"ldr w7, [x21, #8]",
"add x21, x20, #0x4 (4)",
"ldr w6, [x20, #4]",
"add x20, x21, #0x4 (4)",
"ldr w5, [x21, #4]",
"add x21, x20, #0x4 (4)",
"ldr w4, [x20, #4]",
"add x8, x21, #0x4 (4)"
]
},
"aam": {
"ExpectedInstructionCount": 14,
"Optimal": "No",
"Comment": "0xd4",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"mov w21, #0xa",
"udiv x22, x20, x21",
"udiv x2, x20, x21",
"msub x20, x2, x21, x20",
"lsl x21, x22, #8",
"add x20, x21, x20",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"lsl w21, w20, #24",
"tst w21, w21",
"mrs x21, nzcv",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"aad": {
"ExpectedInstructionCount": 14,
"Optimal": "No",
"Comment": "0xd5",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxth w21, w4",
"lsr w21, w21, #8",
"mov w22, #0xa",
"mul x21, x21, x22",
"add x20, x20, x21",
"and x20, x20, #0xff",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"lsl w21, w20, #24",
"tst w21, w21",
"mrs x21, nzcv",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"db 0xd4, 0x40": {
"ExpectedInstructionCount": 14,
"Optimal": "No",
"Comment": [
"aam with a different immediate byte base",
"0xd4"
],
"ExpectedArm64ASM": [
"uxtb w20, w4",
"mov w21, #0x40",
"udiv x22, x20, x21",
"udiv x2, x20, x21",
"msub x20, x2, x21, x20",
"lsl x21, x22, #8",
"add x20, x21, x20",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"lsl w21, w20, #24",
"tst w21, w21",
"mrs x21, nzcv",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"db 0xd5, 0x40": {
"ExpectedInstructionCount": 13,
"Optimal": "No",
"Comment": [
"aad with a different immediate byte base",
"0xd5"
],
"ExpectedArm64ASM": [
"uxtb w20, w4",
"uxth w21, w4",
"lsr w21, w21, #8",
"lsl x21, x21, #6",
"add x20, x20, x21",
"and x20, x20, #0xff",
"bfxil w4, w20, #0, #16",
"uxtb w20, w4",
"lsl w21, w20, #24",
"tst w21, w21",
"mrs x21, nzcv",
"strb w20, [x28, #706]",
"str w21, [x28, #728]"
]
},
"salc": {
"ExpectedInstructionCount": 7,
"Optimal": "No",
"Comment": "0xd6",
"ExpectedArm64ASM": [
"uxtb w20, w4",
"ldr w21, [x28, #728]",
"ubfx w21, w21, #29, #1",
"add w20, w20, w21",
"uxtb w21, w4",
"sub w20, w21, w20",
"bfxil w4, w20, #0, #8"
]
}
}
}
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