mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-06 17:00:19 +02:00
Alyssa Rosenzweig
ce8e6e5c0c
clang generates this. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
3093 lines
135 KiB
JSON
3093 lines
135 KiB
JSON
{
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"Docs": [
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"IRTypes define types that can be used directly in the IR.",
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"These will translate to the underlying C types when stored in the op data",
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"",
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"SSA types are special cased",
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" SSA = untyped",
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" GPR = GPR class type",
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" FPR = FPR class type",
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"Declaring the SSA types correctly will allow validation passes to ensure the op is getting passed correct arguments",
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"",
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"Arguments must always follow a particular order. <Type>:<Prefix><Name>",
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"Type must always be an IRType",
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"Prefix currently can be one of the following: #, $",
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" #: This is a temporary argument that is in the IR Emitter arguments",
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" - This will not be stored in the resulting IR op data structure",
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" $: This is a value that will be stored inside of the IR op data structure",
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" - If it is type SSA, GPR, or FPR then it is an SSA type",
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" - These will get added to the SSA argument union to ensure RA happens",
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"",
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"IR op definition follows the structure of <SSA Type> = <IROp> <Arguments>",
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"",
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"Eg:",
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"IR op with no result and no arguments",
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" CallbackReturn",
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"",
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"IR op with result and no arguments",
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" GPR = ProcessorID",
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"",
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"IR op with no result and non-SSA argument",
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" Fence FenceType:$Type",
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"",
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"IR op with no result and SSA arguments",
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" SetRoundingMode GPR:$Mode",
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"",
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"IR op with result and SSA arguments",
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" GPR = Add GPR:$Src1, GPR:$Src2",
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"",
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"## Op members ##",
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"* Desc",
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" * List of text for documenting this IR op.",
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"* OpClass",
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" * Textual class to group IR ops by type",
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"* DestClass",
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" * SSA class of the return when the return type is `SSA`",
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" * Not used if the destination type is one of {GPR, FPR}",
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"* DestSize",
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" * The size of the destination type",
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"* EmitValidation",
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" * List of validations to emit for the IR emitter",
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" * These are validations that can't be automatically inferred and need to be hand-written",
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""
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],
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"Defines": [
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"constexpr uint8_t COND_EQ = 0",
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"constexpr uint8_t COND_NEQ = 1",
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"constexpr uint8_t COND_UGE = 2",
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"constexpr uint8_t COND_ULT = 3",
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"constexpr uint8_t COND_MI = 4",
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"constexpr uint8_t COND_PL = 5",
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"constexpr uint8_t COND_VS = 6",
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"constexpr uint8_t COND_VC = 7",
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"constexpr uint8_t COND_UGT = 8",
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"constexpr uint8_t COND_ULE = 9",
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"constexpr uint8_t COND_SGE = 10",
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"constexpr uint8_t COND_SLT = 11",
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"constexpr uint8_t COND_SGT = 12",
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"constexpr uint8_t COND_SLE = 13",
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"constexpr uint8_t COND_TSTZ = 14 /* bit test zero */",
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"constexpr uint8_t COND_TSTNZ = 15 /* bit test nonzero */",
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"constexpr uint8_t COND_FLU = 16 /* float less or unordred */",
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"constexpr uint8_t COND_FGE = 17 /* float greater or equal */",
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"constexpr uint8_t COND_FLEU = 18 /* float less or equal or unordred */",
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"constexpr uint8_t COND_FGT = 19 /* float greater */",
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"constexpr uint8_t COND_FU = 20 /* float unordred */",
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"constexpr uint8_t COND_FNU = 21 /* float not unordred */",
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"constexpr uint8_t COND_AL = 32 /* always */",
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"constexpr FEXCore::IR::RegisterClassType GPRClass {0}",
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"constexpr FEXCore::IR::RegisterClassType GPRFixedClass {1}",
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"constexpr FEXCore::IR::RegisterClassType FPRClass {2}",
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"constexpr FEXCore::IR::RegisterClassType FPRFixedClass {3}",
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"constexpr FEXCore::IR::RegisterClassType ComplexClass {5}",
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"constexpr FEXCore::IR::RegisterClassType InvalidClass {7}",
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"",
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"// Only up to 30 registers per register class",
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"constexpr uint8_t InvalidReg {31}",
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"",
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"constexpr FEXCore::IR::TypeDefinition i8 {TypeDefinition::Create(1, 0)}",
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"constexpr FEXCore::IR::TypeDefinition i16 {TypeDefinition::Create(2, 0)}",
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"constexpr FEXCore::IR::TypeDefinition i32 {TypeDefinition::Create(4, 0)}",
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"constexpr FEXCore::IR::TypeDefinition i64 {TypeDefinition::Create(8, 0)}",
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"constexpr FEXCore::IR::TypeDefinition i128 {TypeDefinition::Create(16, 0)}",
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"",
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"constexpr FEXCore::IR::TypeDefinition i8v8 {TypeDefinition::Create(1, 8)}",
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"constexpr FEXCore::IR::TypeDefinition i8v16 {TypeDefinition::Create(1, 16)}",
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"constexpr FEXCore::IR::TypeDefinition i16v4 {TypeDefinition::Create(2, 4)}",
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"constexpr FEXCore::IR::TypeDefinition i16v8 {TypeDefinition::Create(2, 8)}",
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"constexpr FEXCore::IR::TypeDefinition i32v2 {TypeDefinition::Create(4, 2)}",
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"constexpr FEXCore::IR::TypeDefinition i32v4 {TypeDefinition::Create(4, 4)}",
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"constexpr FEXCore::IR::TypeDefinition i64v2 {TypeDefinition::Create(8, 2)}",
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"",
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"constexpr uint8_t FCMP_FLAG_EQ = 0",
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"constexpr uint8_t FCMP_FLAG_LT = 1",
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"constexpr uint8_t FCMP_FLAG_UNORDERED = 2",
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"constexpr FEXCore::IR::FenceType Fence_Load {0}",
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"constexpr FEXCore::IR::FenceType Fence_Store {1}",
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"constexpr FEXCore::IR::FenceType Fence_LoadStore {2}",
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"constexpr uint8_t ROUND_MODE_NEAREST = 0",
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"constexpr uint8_t ROUND_MODE_NEGATIVE_INFINITY = 1",
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"constexpr uint8_t ROUND_MODE_POSITIVE_INFINITY = 2",
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"constexpr uint8_t ROUND_MODE_TOWARDS_ZERO = 3",
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"constexpr uint8_t ROUND_MODE_FLUSH_TO_ZERO = 1 << 2",
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"constexpr FEXCore::IR::RoundType Round_Nearest {ROUND_MODE_NEAREST}",
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"constexpr FEXCore::IR::RoundType Round_Negative_Infinity {ROUND_MODE_NEGATIVE_INFINITY}",
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"constexpr FEXCore::IR::RoundType Round_Positive_Infinity {ROUND_MODE_POSITIVE_INFINITY}",
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"constexpr FEXCore::IR::RoundType Round_Towards_Zero {ROUND_MODE_TOWARDS_ZERO} /* Truncate */",
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"constexpr FEXCore::IR::RoundType Round_Host {ROUND_MODE_TOWARDS_ZERO + 1}",
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"constexpr FEXCore::IR::MemOffsetType MEM_OFFSET_SXTX {0}",
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"constexpr FEXCore::IR::MemOffsetType MEM_OFFSET_UXTW {1}",
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"constexpr FEXCore::IR::MemOffsetType MEM_OFFSET_SXTW {2}",
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"struct BreakDefinition {",
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" uint16_t ErrorRegister;",
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" uint8_t Signal;",
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" uint8_t TrapNumber;",
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" uint8_t si_code;",
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"};"
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],
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"IRTypes" : {
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"i1": "bool",
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"i8": "int8_t",
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"i16": "int16_t",
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"i32": "int32_t",
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"i64": "int64_t",
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"u8": "uint8_t",
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"u16": "uint16_t",
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"u32": "uint32_t",
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"u64": "uint64_t",
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"OpSize": "FEXCore::IR::OpSize",
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"SSA": "OrderedNode*",
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"GPR": "OrderedNode*",
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"FPR": "OrderedNode*",
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"FenceType": "FenceType",
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"RegisterClass": "RegisterClassType",
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"CondClass": "CondClassType",
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"SyscallFlags": "FEXCore::IR::SyscallFlags",
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"SHA256Sum": "SHA256Sum",
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"MemOffsetType": "MemOffsetType",
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"BreakDefinition": "BreakDefinition",
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"RoundType": "RoundType",
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"FloatCompareOp": "FloatCompareOp",
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"NamedVectorConstant": "FEXCore::IR::NamedVectorConstant",
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"IndexNamedVectorConstant": "FEXCore::IR::IndexNamedVectorConstant",
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"ShiftType": "FEXCore::IR::ShiftType"
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},
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"Ops": {
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"Misc": {
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"Dummy": {
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"HasSideEffects": true,
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"SwitchGen": false,
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"JITDispatchOverride": "NoOp"
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},
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"IRHeader SSA:$Blocks, u64:$OriginalRIP, u32:$BlockCount, u32:$NumHostInstructions, i1:$HasX87{false}": {
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"SwitchGen": false,
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"JITDispatchOverride": "NoOp"
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},
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"CodeBlock SSA:$Begin, SSA:$Last": {
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"SwitchGen": false,
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"RAOverride": "0",
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"JITDispatchOverride": "NoOp"
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},
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"BeginBlock SSA:$BlockHeader": {
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"HasSideEffects": true,
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"SwitchGen": false,
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"RAOverride": "0",
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"JITDispatchOverride": "NoOp"
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},
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"InvalidateFlags u64:$Flags": {
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"HasSideEffects": true,
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"JITDispatchOverride": "NoOp"
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},
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"EndBlock SSA:$BlockHeader": {
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"HasSideEffects": true,
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"SwitchGen": false,
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"RAOverride": "0",
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"JITDispatchOverride": "NoOp"
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},
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"GuestOpcode u32:$GuestEntryOffset": {
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"Desc": ["Marks the beginning of a guest opcode"],
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"HasSideEffects": true
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},
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"GPR = ValidateCode u64:$CodeOriginalLow, u64:$CodeOriginalhigh, i64:$Offset, u8:$CodeLength": {
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"HasSideEffects": true,
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"HasDest": true,
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"ImplicitFlagClobber": true,
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"DestSize": "8"
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},
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"ThreadRemoveCodeEntry": {
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"HasSideEffects": true
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},
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"GPR = ProcessorID": {
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"Desc": ["Returns the processor ID correlating to the current running CPU",
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"This may be out of date by time this instruction is executed so care must be taken",
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"This same information can be gotten from syscall getcpu(&cpu, &node)",
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"uint32_t Res = (node << 12) | cpu;",
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"This means it has a limitation of 4096 CPU cores. Which is fine and matches x86 behaviour"
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],
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"DestSize": 8
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},
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"GPR = GetRoundingMode": {
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"Desc": ["Gets the current rounding mode options"
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],
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"DestSize": "4"
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},
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"SetRoundingMode GPR:$RoundMode, i1:$SetDAZ, GPR:$MXCSR": {
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"Desc": ["Sets the current rounding mode options for the thread"
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],
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"HasSideEffects": true
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},
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"GPR = PushRoundingMode u8:$RoundMode": {
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"Desc": ["Override the current rounding mode options for the thread, returning old FPCR"
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],
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"DestSize": "8",
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"HasSideEffects": true
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},
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"PopRoundingMode GPR:$FPCR": {
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"Desc": ["Resets rounding mode after PushRoundingMode operation"
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],
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"HasSideEffects": true
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},
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"Print SSA:$Value": {
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"HasSideEffects": true,
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"Desc": ["Debug operation that prints an SSA value to the console",
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"May only print 64bits of the value"]
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},
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"GPR = AllocateGPR i1:$ForPair": {
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"Desc": ["Silly pseudo-instruction to allocate a register for a future destination",
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"Note: if an instruction uses allocated destinations-as-sources,",
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"it cannot use a regular destination too. This ensures RA correctness.",
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"This is a kludge to deal with the IR's lack of multiple destinations",
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"If ForPair is set, RA will try to allocate the base of a register pair"],
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"DestSize": "8"
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},
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"FPR = AllocateFPR u8:#RegisterSize, u8:#ElementSize": {
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"Desc": ["Like AllocateGPR, but for FPR"],
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"DestSize": "RegisterSize",
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"NumElements": "RegisterSize / ElementSize"
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},
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"GPR = AllocateGPRAfter GPR:$After": {
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"Desc": ["Silly pseudo-instruction to allocate a register for a future destination",
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"This is a kludge to deal with the IR's lack of multiple destinations",
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"RA will attempt to allocate to the register after $After.",
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"It may not succeed."],
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"DestSize": "8"
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},
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"GPR = RDRAND i1:$GetReseeded": {
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"Desc": ["Uses the hardware random number generator to generate a 64bit number",
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"The boolean argument asks if we should be reading the reseeded number or not",
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"Reseeded RNG calculation is more expensive and will be heavier to use",
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"Returns the 64-bit number",
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"Sets the Z flag if the number is valid.",
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"RNG hardware is allowed to fail early and return. Software must always check this"
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],
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"HasSideEffects": true,
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"DestSize": "8"
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},
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"Yield": {
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"HasSideEffects": true,
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"Desc": ["This is a hint instruction that the CPU is likely to do a spin so it might want to pause to help out SMP",
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"Can be implemented as a NOP if necessary"]
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}
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},
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"Branch": {
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"Jump SSA:$TargetBlock": {
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"HasSideEffects": true,
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"RAOverride": "0"
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},
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"CondJump SSA:$Cmp1, SSA:$Cmp2, SSA:$TrueBlock, SSA:$FalseBlock, CondClass:$Cond{{COND_NEQ}}, u8:$CompareSize{0}, i1:$FromNZCV{false}": {
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"HasSideEffects": true,
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"RAOverride": "2"
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},
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"ExitFunction GPR:$NewRIP": {
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"Desc": ["Exits the current JIT function with a target RIP"
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],
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"HasSideEffects": true,
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"DestSize": "GetOpSize(NewRIP)"
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},
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"Break BreakDefinition:$Reason": {
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"HasSideEffects": true
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},
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"CallbackReturn": {
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"HasSideEffects": true
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},
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"GPR = Syscall GPR:$SyscallID, GPR:$Arg0, GPR:$Arg1, GPR:$Arg2, GPR:$Arg3, GPR:$Arg4, GPR:$Arg5, SyscallFlags:$Flags": {
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"HasSideEffects": true,
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"Desc": ["Dispatches a guest syscall through to the SyscallHandler class"
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],
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"DestSize": "8"
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},
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"GPR = InlineSyscall GPR:$Arg0, GPR:$Arg1, GPR:$Arg2, GPR:$Arg3, GPR:$Arg4, GPR:$Arg5, i32:$HostSyscallNumber, SyscallFlags:$Flags": {
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"HasSideEffects": true,
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"Desc": ["Dispatches a guest syscall directly to the host syscall interface,",
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"bypassing the SyscallHandler class used by Syscall.",
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"This has significantly less overhead than Syscall, which needs to save JIT state first.",
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"Can only be used for syscalls that match across architecture,",
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"such as gettid (matches on x86/x86-64/Arm64)."
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],
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"DestSize": "8"
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},
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"Thunk GPR:$ArgPtr, SHA256Sum:$ThunkNameHash": {
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"HasSideEffects": true
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},
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"GPR:$EAX, GPR:$EBX, GPR:$ECX, GPR:$EDX = CPUID GPR:$Function, GPR:$Leaf": {
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"Desc": ["Calls in to the CPUID handler function to return emulated CPUID"],
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"DestSize": "4",
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"HasSideEffects": true
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},
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"GPR:$EAX, GPR:$EDX = XGetBV GPR:$Function": {
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"Desc": ["Calls in to the XCR handler function to return emulated XCR"],
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"DestSize": "4",
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"HasSideEffects": true
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}
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},
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"Moves": {
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"GPR = Copy GPR:$Source": {
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"Desc": ["GPR copy, generated by RA to split live ranges"],
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"DestSize": "8"
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},
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"GPR = Swap1 GPR:$A, GPR:$B": {
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"Desc": ["GPR swap part 1, generated by RA. Returns value of first source.",
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"Destination must be second GPR."],
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"DestSize": "8"
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},
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"GPR = Swap2": {
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"Desc": ["GPR swap part 2, generated by RA. Returns source source.",
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"Must immediately succeed Swap1 with no intervening instructions",
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"Kludge to workaround single destination restriction on IR",
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"Hopefully temporary"],
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"DestSize": "8"
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}
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},
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"StaticRA": {
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"SSA = LoadRegister u32:$Reg, RegisterClass:$Class, u8:#Size": {
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"Desc": ["Loads a value from the given register",
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"Size must match the execution mode."],
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"DestSize": "Size"
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},
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"StoreRegister SSA:$Value, u32:$Reg, RegisterClass:$Class, u8:#Size": {
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"HasSideEffects": true,
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"Desc": ["Stores a value to a given register.",
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"Size must match the execution mode."],
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"DestSize": "Size",
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"EmitValidation": [
|
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"WalkFindRegClass($Value) == $Class"
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]
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}
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},
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"Memory": {
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"SSA = LoadContext u8:#ByteSize, RegisterClass:$Class, u32:$Offset": {
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"Desc": ["Loads a value from the context with offset",
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"Dest = Ctx[Offset]"
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],
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"DestSize": "ByteSize",
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"EmitValidation": [
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"($Class == GPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8)) || $Class == FPRClass",
|
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"($Class == FPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8 || #ByteSize == 16 || #ByteSize == 32)) || $Class == GPRClass",
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"!($Offset >= offsetof(Core::CPUState, gregs[0]) && $Offset < offsetof(Core::CPUState, gregs[16])) && \"Can't LoadContext to GPR\"",
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"!($Offset >= offsetof(Core::CPUState, xmm.avx.data[0]) && $Offset < offsetof(Core::CPUState, xmm.avx.data[16])) && \"Can't LoadContext to XMM\""
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]
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},
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"SSA:$Value1, SSA:$Value2 = LoadContextPair u8:#ByteSize, RegisterClass:$Class, u32:$Offset": {
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"Desc": ["Loads a pair of values from the context with offset",
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"Value0 = Ctx[Offset], Value1 = Ctx[Offset + ByteSize]"
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],
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"HasSideEffects": true,
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"DestSize": "ByteSize",
|
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"EmitValidation": [
|
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"($Class == GPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8)) || $Class == FPRClass",
|
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"($Class == FPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8 || #ByteSize == 16 || #ByteSize == 32)) || $Class == GPRClass",
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"!($Offset >= offsetof(Core::CPUState, gregs[0]) && $Offset < offsetof(Core::CPUState, gregs[16])) && \"Can't LoadContext to GPR\"",
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"!($Offset >= offsetof(Core::CPUState, xmm.avx.data[0]) && $Offset < offsetof(Core::CPUState, xmm.avx.data[16])) && \"Can't LoadContext to XMM\""
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]
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},
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"StoreContext u8:#ByteSize, RegisterClass:$Class, SSA:$Value, u32:$Offset": {
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"Desc": ["Stores a value to the context with offset",
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"Ctx[Offset] = Value",
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"Zero Extends if value's type is too small",
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"Truncates if value's type is too large"
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],
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"HasSideEffects": true,
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"DestSize": "ByteSize",
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"EmitValidation": [
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"WalkFindRegClass($Value) == $Class",
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"($Class == GPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8)) || $Class == FPRClass",
|
|
"($Class == FPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8 || #ByteSize == 16 || #ByteSize == 32)) || $Class == GPRClass",
|
|
"!($Offset >= offsetof(Core::CPUState, gregs[0]) && $Offset < offsetof(Core::CPUState, gregs[16])) && \"Can't StoreContext to GPR\"",
|
|
"!($Offset >= offsetof(Core::CPUState, xmm.avx.data[0]) && $Offset < offsetof(Core::CPUState, xmm.avx.data[16])) && \"Can't StoreContext to XMM\""
|
|
]
|
|
},
|
|
|
|
"StoreContextPair u8:#ByteSize, RegisterClass:$Class, SSA:$Value1, SSA:$Value2, u32:$Offset": {
|
|
"Desc": ["Stores a pair of values to the context with offset",
|
|
"Ctx[Offset] = Value1, Ctx[Offset + ByteSize] = Value2",
|
|
"Zero Extends if value's type is too small",
|
|
"Truncates if value's type is too large"
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "ByteSize",
|
|
"EmitValidation": [
|
|
"WalkFindRegClass($Value1) == $Class",
|
|
"WalkFindRegClass($Value2) == $Class",
|
|
"($Class == GPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8)) || $Class == FPRClass",
|
|
"($Class == FPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8 || #ByteSize == 16 || #ByteSize == 32)) || $Class == GPRClass",
|
|
"!($Offset >= offsetof(Core::CPUState, gregs[0]) && $Offset < offsetof(Core::CPUState, gregs[16])) && \"Can't StoreContext to GPR\"",
|
|
"!($Offset >= offsetof(Core::CPUState, xmm.avx.data[0]) && $Offset < offsetof(Core::CPUState, xmm.avx.data[16])) && \"Can't StoreContext to XMM\""
|
|
]
|
|
},
|
|
|
|
"SSA = LoadContextIndexed GPR:$Index, u8:#ByteSize, u32:$BaseOffset, u32:$Stride, RegisterClass:$Class": {
|
|
"Desc": ["Loads a value from the context with offset and indexed by SSA value",
|
|
"Dest = Ctx[BaseOffset + Index * Stride]"
|
|
],
|
|
"DestSize": "ByteSize",
|
|
"EmitValidation": [
|
|
"($Class == GPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8)) || $Class == FPRClass",
|
|
"($Class == FPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8 || #ByteSize == 16 || #ByteSize == 32)) || $Class == GPRClass",
|
|
"!($BaseOffset >= offsetof(Core::CPUState, gregs[0]) && $BaseOffset < offsetof(Core::CPUState, gregs[16])) && \"Can't LoadContextIndexed to GPR\"",
|
|
"!($BaseOffset >= offsetof(Core::CPUState, xmm.avx.data[0]) && $BaseOffset < offsetof(Core::CPUState, xmm.avx.data[16])) && \"Can't LoadContextIndexed to XMM\""
|
|
]
|
|
},
|
|
"StoreContextIndexed SSA:$Value, GPR:$Index, u8:#ByteSize, u32:$BaseOffset, u32:$Stride, RegisterClass:$Class": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Stores a value to the context with offset and indexed by SSA value",
|
|
"Ctx[BaseOffset + Index * Stride] = Value"
|
|
],
|
|
"DestSize": "ByteSize",
|
|
"EmitValidation": [
|
|
"WalkFindRegClass($Value) == $Class",
|
|
"($Class == GPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8)) || $Class == FPRClass",
|
|
"($Class == FPRClass && (#ByteSize == 1 || #ByteSize == 2 || #ByteSize == 4 || #ByteSize == 8 || #ByteSize == 16 || #ByteSize == 32)) || $Class == GPRClass",
|
|
"!($BaseOffset >= offsetof(Core::CPUState, gregs[0]) && $BaseOffset < offsetof(Core::CPUState, gregs[16])) && \"Can't StoreContextIndexed to GPR\"",
|
|
"!($BaseOffset >= offsetof(Core::CPUState, xmm.avx.data[0]) && $BaseOffset < offsetof(Core::CPUState, xmm.avx.data[16])) && \"Can't StoreContextIndexed to XMM\""
|
|
]
|
|
},
|
|
|
|
"SpillRegister SSA:$Value, u32:$Slot, RegisterClass:$Class": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Spills an SSA value to memory",
|
|
"Spill slots are register allocated and has live ranges calculated to handle slot calculation",
|
|
"```diff\n- !Don't use this op. It is for RA to handle spilling and filling!\n```"
|
|
],
|
|
"EmitValidation": [
|
|
"WalkFindRegClass($Value) == $Class"
|
|
]
|
|
},
|
|
|
|
"SSA = FillRegister SSA:$OriginalValue, u32:$Slot, RegisterClass:$Class": {
|
|
"Desc": ["Fills a register from a spill slot",
|
|
"Spill slots are register allocated and has live ranges calculated to handle slot calculation",
|
|
"```diff\n- !Don't use this op. It is for RA to handle spilling and filling!\n```",
|
|
"",
|
|
"The OriginalValue SSA arg points at the original SSA value spilled, and only exists for",
|
|
"RA validation purposes"
|
|
],
|
|
"EmitValidation": [
|
|
"WalkFindRegClass($OriginalValue) == $Class"
|
|
]
|
|
},
|
|
|
|
"GPR = LoadNZCV": {
|
|
"Desc": ["Loads value of NZCV register"],
|
|
"DestSize": "4"
|
|
},
|
|
|
|
"StoreNZCV GPR:$Value": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Stores value to NZCV register"],
|
|
"DestSize": "4"
|
|
},
|
|
|
|
"GPR = LoadDF": {
|
|
"Desc": ["Loads the decimal flag from the context object in -1/1",
|
|
"representation for easy consumption"
|
|
],
|
|
"DestSize": "8"
|
|
},
|
|
|
|
"SSA = LoadMem RegisterClass:$Class, u8:#Size, GPR:$Addr, GPR:$Offset, u8:$Align, MemOffsetType:$OffsetType, u8:$OffsetScale": {
|
|
"DestSize": "Size"
|
|
},
|
|
|
|
"SSA:$Value1, SSA:$Value2 = LoadMemPair RegisterClass:$Class, u8:#Size, GPR:$Addr, u32:$Offset": {
|
|
"Desc": ["Load a pair of values from memory."],
|
|
"DestSize": "Size",
|
|
"HasSideEffects": true
|
|
},
|
|
|
|
"StoreMem RegisterClass:$Class, u8:#Size, SSA:$Value, GPR:$Addr, GPR:$Offset, u8:$Align, MemOffsetType:$OffsetType, u8:$OffsetScale": {
|
|
"Desc": [ "Stores a value to memory.",
|
|
"Zero Extends if value's type is too small",
|
|
"Truncates if value's type is too large"
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"WalkFindRegClass($Value) == $Class"
|
|
]
|
|
},
|
|
|
|
"StoreMemPair RegisterClass:$Class, u8:#Size, SSA:$Value1, SSA:$Value2, GPR:$Addr, u32:$Offset": {
|
|
"Desc": [ "Stores a pair of values to memory.",
|
|
"Zero Extends if value's type is too small",
|
|
"Truncates if value's type is too large"
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"WalkFindRegClass($Value1) == $Class",
|
|
"WalkFindRegClass($Value2) == $Class"
|
|
]
|
|
},
|
|
|
|
"SSA = LoadMemTSO RegisterClass:$Class, u8:#Size, GPR:$Addr, GPR:$Offset, u8:$Align, MemOffsetType:$OffsetType, u8:$OffsetScale": {
|
|
"Desc": ["Does a x86 TSO compatible load from memory. Offset must be Invalid()."
|
|
],
|
|
"DestSize": "Size",
|
|
"DynamicDispatch": true
|
|
},
|
|
|
|
"StoreMemTSO RegisterClass:$Class, u8:#Size, SSA:$Value, GPR:$Addr, GPR:$Offset, u8:$Align, MemOffsetType:$OffsetType, u8:$OffsetScale": {
|
|
"Desc": ["Does a x86 TSO compatible store to memory. Offset must be Invalid()."
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"DynamicDispatch": true,
|
|
"EmitValidation": [
|
|
"WalkFindRegClass($Value) == $Class"
|
|
]
|
|
},
|
|
|
|
"FPR = VLoadVectorMasked u8:#RegisterSize, u8:#ElementSize, FPR:$Mask, GPR:$Addr, GPR:$Offset, MemOffsetType:$OffsetType, u8:$OffsetScale": {
|
|
"Desc": ["Does a masked load similar to VPMASKMOV/VMASKMOV where the upper bit of each element",
|
|
"determines whether or not that element will be loaded from memory"],
|
|
"ImplicitFlagClobber": true,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"VStoreVectorMasked u8:#RegisterSize, u8:#ElementSize, FPR:$Mask, FPR:$Data, GPR:$Addr, GPR:$Offset, MemOffsetType:$OffsetType, u8:$OffsetScale": {
|
|
"Desc": ["Does a masked store similar to VPMASKMOV/VMASKMOV where the upper bit of each element",
|
|
"determines whether or not that element will be stored to memory"],
|
|
"HasSideEffects": true,
|
|
"ImplicitFlagClobber": true,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VLoadVectorGatherMasked u8:#RegisterSize, u8:#ElementSize, FPR:$Incoming, FPR:$Mask, GPR:$AddrBase, FPR:$VectorIndexLow, FPR:$VectorIndexHigh, u8:$VectorIndexElementSize, u8:$OffsetScale, u8:$DataElementOffsetStart, u8:$IndexElementOffsetStart": {
|
|
"Desc": [
|
|
"Does a masked load similar to VPGATHERD* where the upper bit of each element",
|
|
"determines whether or not that element will be loaded from memory.",
|
|
"Most of VSIB encoding is passed directly through to the IR operation."
|
|
],
|
|
"TiedSource": 0,
|
|
"ImplicitFlagClobber": true,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"EmitValidation": [
|
|
"$VectorIndexElementSize == OpSize::i32Bit || $VectorIndexElementSize == OpSize::i64Bit"
|
|
]
|
|
},
|
|
"FPR = VLoadVectorGatherMaskedQPS u8:#RegisterSize, u8:#ElementSize, FPR:$Incoming, FPR:$MaskReg, GPR:$AddrBase, FPR:$VectorIndexLow, FPR:$VectorIndexHigh, u8:$OffsetScale": {
|
|
"Desc": [
|
|
"Does a masked load similar to VPGATHERQPS where the upper bit of each element",
|
|
"determines whether or not that element will be loaded from memory.",
|
|
"Most of VSIB encoding is passed directly through to the IR operation.",
|
|
"Only supports the case of 32-bit data element sizes from 64-bit addresses"
|
|
],
|
|
"TiedSource": 0,
|
|
"ImplicitFlagClobber": true,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"EmitValidation": [
|
|
"ElementSize == OpSize::i32Bit",
|
|
"RegisterSize != FEXCore::IR::OpSize::i256Bit && \"What does 256-bit mean in this context?\""
|
|
]
|
|
},
|
|
"FPR = VLoadVectorElement u8:#RegisterSize, u8:#ElementSize, FPR:$DstSrc, u8:$Index, GPR:$Addr": {
|
|
"Desc": ["Does a memory load to a single element of a vector.",
|
|
"Leaves the rest of the vector's data intact.",
|
|
"Matches arm64 ld1 semantics"],
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"VStoreVectorElement u8:#RegisterSize, u8:#ElementSize, FPR:$Value, u8:$Index, GPR:$Addr": {
|
|
"Desc": ["Does a memory store of a single element of a vector.",
|
|
"Matches arm64 st1 semantics"],
|
|
"HasSideEffects": true,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VBroadcastFromMem u8:#RegisterSize, u8:#ElementSize, GPR:$Address": {
|
|
"Desc": ["Broadcasts an ElementSize value from memory into each element of a vector."],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"GPR = Push u8:#Size, u8:$ValueSize, GPR:$Value, GPR:$Addr": {
|
|
"Desc": [
|
|
"Pushes a value to the address, returning the new pointer after incrementing.",
|
|
"The address is decremented by the value size while.",
|
|
"The return value size is the size of the current operating mode"
|
|
],
|
|
"TiedSource": 1,
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size"
|
|
},
|
|
"GPR = RMWHandle GPR:$Value": {
|
|
"Desc": [
|
|
"This is a special move that indicates the result will be poisoned by a non-SSA instruction writing to its result.",
|
|
"In effect, it serves to prevent invalid optimizations with non-SSA instructions."
|
|
],
|
|
"HasSideEffects": true,
|
|
"TiedSource": 0
|
|
},
|
|
"GPR:$Addr, GPR:$Value = Pop u8:$Size, GPR:$Addr": {
|
|
"Desc": [
|
|
"Pops a value from the address, updating the new pointer after incrementing.",
|
|
"The address is incremented by the size via an RMW source/destintaion."
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size"
|
|
},
|
|
"GPR = MemSet i1:$IsAtomic, u8:$Size, GPR:$Prefix, GPR:$Addr, GPR:$Value, GPR:$Length, GPR:$Direction": {
|
|
"Desc": ["Duplicates behaviour of x86 STOS repeat",
|
|
"Returns the final address that gets generated without the prefix appended."
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "8"
|
|
},
|
|
"GPR:$DstAddress, GPR:$SrcAddress = MemCpy i1:$IsAtomic, u8:$Size, GPR:$Dest, GPR:$Src, GPR:$Length, GPR:$Direction": {
|
|
"Desc": ["Duplicates behaviour of x86 MOVS repeat",
|
|
"Returns the final addresses after they have been incremented or decremented"
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "8"
|
|
},
|
|
"CacheLineClear GPR:$Addr, i1:$Serialize": {
|
|
"Desc": ["Does a 64 byte cacheline clear at the address specified",
|
|
"Only clears the data cachelines. Doesn't do any zeroing",
|
|
"Can skip serialization if requested."
|
|
],
|
|
"HasSideEffects": true
|
|
},
|
|
"CacheLineClean GPR:$Addr": {
|
|
"Desc": ["Does a 64 byte cacheline cleanat the address specified",
|
|
"Only cleans the data cachelines. Doesn't do any zeroing",
|
|
"Skips the invalidation step of the CacheLineClear operation"
|
|
],
|
|
"HasSideEffects": true
|
|
},
|
|
"CacheLineZero GPR:$Addr": {
|
|
"Desc": ["Does a 64 byte zero at the address specified",
|
|
"Writing zeroes to memory",
|
|
"It is specifically non-temporal and weakly ordered",
|
|
"This matches CLZero behaviour"
|
|
],
|
|
"HasSideEffects": true
|
|
},
|
|
"Fence FenceType:$Fence": {
|
|
"Desc": ["Does a memory fence operation of the desired type",
|
|
"Fence_Load: Ensures load memory operations are serialized",
|
|
"Fence_Store: Ensures store memory operations are serialized",
|
|
"Fence_LoadStore: Ensures loads and store memory operations are serialized",
|
|
"Ensures the memory operations are globally visible"
|
|
],
|
|
"HasSideEffects": true
|
|
},
|
|
"Prefetch i1:$ForStore, i1:$Stream, i8:$CacheLevel, GPR:$Addr, GPR:$Offset, MemOffsetType:$OffsetType, u8:$OffsetScale": {
|
|
"Desc": ["Does a cacheline prefetch operation"
|
|
],
|
|
"EmitValidation": [
|
|
"CacheLevel > 0 && CacheLevel < 4"
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "8"
|
|
},
|
|
"VStoreNonTemporal u8:#RegisterSize, FPR:$Value, GPR:$Addr, i8:$Offset": {
|
|
"Desc": ["Does a non-temporal memory store of a vector.",
|
|
"Matches arm64 SVE stnt1b semantics.",
|
|
"Specifically weak-memory model ordered to match x86 non-temporal stores."
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "RegisterSize",
|
|
"EmitValidation": [
|
|
"Offset % RegisterSize == 0",
|
|
"RegisterSize == FEXCore::IR::OpSize::i128Bit || RegisterSize == FEXCore::IR::OpSize::i256Bit"
|
|
]
|
|
},
|
|
"VStoreNonTemporalPair u8:#RegisterSize, FPR:$ValueLow, FPR:$ValueHigh, GPR:$Addr, i8:$Offset": {
|
|
"Desc": ["Does a non-temporal memory store of two vector registers.",
|
|
"Matches arm64 stnp semantics.",
|
|
"Specifically weak-memory model ordered to match x86 non-temporal stores."
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "RegisterSize",
|
|
"EmitValidation": [
|
|
"Offset % RegisterSize == 0",
|
|
"RegisterSize == FEXCore::IR::OpSize::i128Bit"
|
|
]
|
|
},
|
|
"FPR = VLoadNonTemporal u8:#RegisterSize, GPR:$Addr, i8:$Offset": {
|
|
"Desc": ["Does a non-temporal memory load of a vector.",
|
|
"Matches arm64 SVE ldnt1b semantics.",
|
|
"Specifically weak-memory model ordered to match x86 non-temporal stores."
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "RegisterSize",
|
|
"EmitValidation": [
|
|
"Offset % RegisterSize == 0",
|
|
"RegisterSize == FEXCore::IR::OpSize::i128Bit || RegisterSize == FEXCore::IR::OpSize::i256Bit"
|
|
]
|
|
}
|
|
},
|
|
"Atomic": {
|
|
"GPR = CAS OpSize:#Size, GPR:$Expected, GPR:$Desired, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Does a compare and swap of values to a memory location",
|
|
"This mostly matches the C++ atomic_compare_exchange_strong function",
|
|
"Dest = atomic_compare_exchange_strong(%Addr, %Expected, %Desired)",
|
|
"Depending on if the value in %Addr is Expected the results destination will be different",
|
|
"Behaves like the following but atomically",
|
|
"Dest = %Expected",
|
|
"if (deref(%Addr) != %Expected) Dest = deref(%Addr)"
|
|
],
|
|
|
|
"DestSize": "Size",
|
|
"ImplicitFlagClobber": true,
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR:$Lo, GPR:$Hi = CASPair OpSize:#Size, GPR:$ExpectedLo, GPR:$ExpectedHi, GPR:$DesiredLo, GPR:$DesiredHi, GPR:$Addr": {
|
|
"Desc": ["Does a compare and exchange with two pairs of values",
|
|
"ssa0 is the comparison value",
|
|
"ssa1 is the new value",
|
|
"ssa2 is the memory location",
|
|
"Returns the lower & upper halves of the value in memory."
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"AtomicAdd OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer add",
|
|
"IR layout must match Fetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"AtomicSub OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer sub",
|
|
"IR layout must match Fetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"AtomicAnd OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer and",
|
|
"IR layout must match Fetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"AtomicCLR OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer binary clear",
|
|
"IR layout must match Fetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"AtomicOr OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer or",
|
|
"IR layout must match Fetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"AtomicXor OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer xor",
|
|
"IR layout must match Fetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"AtomicNeg OpSize:#Size, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer two's complement negate",
|
|
"IR layout must match Fetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AtomicSwap OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer swap"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AtomicFetchAdd OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer fetch and add",
|
|
"Atomically fetches %Addr and adds %value to the memory location",
|
|
"Dest is the value prior to operating on the value in memory",
|
|
"IR layout must match NonFetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AtomicFetchSub OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer fetch and sub",
|
|
"Atomically fetches %Addr and subtracts %value to the memory location",
|
|
"Dest is the value prior to operating on the value in memory",
|
|
"IR layout must match NonFetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AtomicFetchAnd OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer fetch and binary and",
|
|
"Atomically fetches %Addr and binary ands %value to the memory location",
|
|
"Dest is the value prior to operating on the value in memory",
|
|
"IR layout must match NonFetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AtomicFetchCLR OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer fetch and binary clear",
|
|
"Atomically fetches %Addr and binary clears %value to the memory location",
|
|
"Dest is the value prior to operating on the value in memory",
|
|
"Matches ARM ldclral semantics",
|
|
"eg: Dest[Addr] &= ~Value",
|
|
"IR layout must match NonFetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AtomicFetchOr OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer fetch and binary or",
|
|
"Atomically fetches %Addr and binary ors %value to the memory location",
|
|
"Dest is the value prior to operating on the value in memory",
|
|
"IR layout must match NonFetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AtomicFetchXor OpSize:#Size, GPR:$Value, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer fetch and binary exclusive or",
|
|
"Atomically fetches %Addr and binary exclusive ors %value to the memory location",
|
|
"Dest is the value prior to operating on the value in memory",
|
|
"IR layout must match NonFetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AtomicFetchNeg OpSize:#Size, GPR:$Addr": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Atomic integer fetch and two's complement negate",
|
|
"Dest is the value prior to operating on the value in memory",
|
|
"IR layout must match NonFetch-variant, otherwise DCE IR optimization breaks!"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"TelemetrySetValue GPR:$Value, u8:$TelemetryValueIndex": {
|
|
"HasSideEffects": true,
|
|
"Desc": ["Set Telemetry value if the passed in 32-bit value isn't zero.",
|
|
"Only useful for 32-bit applications."
|
|
],
|
|
"ImplicitFlagClobber": true,
|
|
"DestSize": "8"
|
|
}
|
|
},
|
|
"ALU": {
|
|
"GPR = EntrypointOffset OpSize:#Size, i64:$Offset": {
|
|
"Desc": ["Returns the <entrypoint> + Offset address",
|
|
"When the size is 4 bytes then 32-bit overflow and underflow needs to work"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
|
|
"InlineEntrypointOffset OpSize:#Size, i64:$Offset": {
|
|
"Desc": ["Returns the <entrypoint> + Offset address",
|
|
"When the size is 4 bytes then 32-bit overflow and underflow needs to work"
|
|
],
|
|
"HasSideEffects": true,
|
|
"RAOverride": "0",
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
|
|
"GPR = Constant i64:$Constant": {
|
|
"Desc": ["Generates a 64bit constant inside of a GPR",
|
|
"Unsupported to create a constant in FPR"
|
|
],
|
|
"DestSize": "8"
|
|
},
|
|
|
|
"InlineConstant i64:$Constant": {
|
|
"Desc": ["Generates a 64bit constant to be used directly, non-FPR"],
|
|
"HasSideEffects": true,
|
|
"RAOverride": "0",
|
|
"DestSize": "8"
|
|
},
|
|
|
|
"GPR = CycleCounter": {
|
|
"Desc": ["Returns the host 64bit cycle counter",
|
|
"Useful when emulating rdtsc",
|
|
"Be careful, the frequency of this counter changes based on host",
|
|
"On AArch64 make sure to query the CNTFRQ_EL0 system register to get the frequency",
|
|
"On x86-64 make sure to query CPUID fn8000_0008[EDX_8] for constant TSC",
|
|
"x86-64 constant frequency lives in MSR_PLATFORM_INFO. Which is only available to kernel",
|
|
"Part of the ART frequency equation can be pulled from CPUID fn0000_0015[EBX & EAX]",
|
|
"But it's missing the ART multiplier still?"
|
|
],
|
|
"DestSize": "8"
|
|
},
|
|
|
|
"GPR = Neg OpSize:#Size, GPR:$Src, CondClass:$Cond{{COND_AL}}": {
|
|
"Desc": ["Integer negation, with optional predication",
|
|
"Dest = Cond ? -Src : Src",
|
|
"Will truncate to 64 or 32bits"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Not OpSize:#Size, GPR:$Src": {
|
|
"Desc": ["Integer binary not",
|
|
"op:",
|
|
"Dest = ~Src"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Popcount OpSize:#Size, GPR:$Src": {
|
|
"Desc": ["Population count of source register",
|
|
"Returns the number of bits set"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = FindLSB OpSize:#Size, GPR:$Src": {
|
|
"Desc": ["Find least-significant-bit set",
|
|
"Returns the index of the least significant bit set",
|
|
"In the case of zero returns ~0U"
|
|
],
|
|
"DestSize": "Size",
|
|
"ImplicitFlagClobber": true,
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = FindMSB OpSize:#Size, GPR:$Src": {
|
|
"Desc": ["Find most-significant-bit set",
|
|
"Returns the index of the most significant bit set",
|
|
"In the case of zero returns ~0U"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = FindTrailingZeroes OpSize:#Size, GPR:$Src": {
|
|
"Desc": ["Counts the number of trailing zero bits in a GPR",
|
|
"Returns the number of bits that are zero trailing",
|
|
"In the case of zero returns the size in bits of the input"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = CountLeadingZeroes OpSize:#Size, GPR:$Src": {
|
|
"Desc": ["Counts the number of leading zero bits in a GPR",
|
|
"Returns the number of bits that are zero leading",
|
|
"In the case of zero returns the size in bits of the input"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Rev OpSize:#Size, GPR:$Src": {
|
|
"Desc": ["Reverses the byte order of the register",
|
|
"Specifically 8bit byte swap size. (Not 16bit or 32bit word swapping)"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Add OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": [ "Integer Add",
|
|
"Will truncate to 64 or 32bits"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Adc OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": [ "Integer Add with carry",
|
|
"Will truncate to 64 or 32bits"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Sbb OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": [ "Integer Subtract with carry/borrow",
|
|
"Will truncate to 64 or 32bits"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AddShift OpSize:#Size, GPR:$Src1, GPR:$Src2, ShiftType:$Shift{ShiftType::LSL}, u8:$ShiftAmount{0}": {
|
|
"Desc": [ "Integer Add with shifted register",
|
|
"Will truncate to 64 or 32bits",
|
|
"Dest = Src1 + (Src2 << ShiftAmount)"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit",
|
|
"Shift != ShiftType::ROR"
|
|
]
|
|
},
|
|
"GPR = AddWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": [ "Integer add. Truncates and sets NZCV per AddNZCV"],
|
|
"DestSize": "Size",
|
|
"HasSideEffects": true,
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"AddNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Set NZCV for the sum of two GPRs"],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size"
|
|
},
|
|
"SetSmallNZV OpSize:#Size, GPR:$Src": {
|
|
"Desc": ["Set NZV with a SETF instruction. Preserves CF."],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit"
|
|
]
|
|
},
|
|
"CarryInvert": {
|
|
"Desc": ["Invert carry flag in NZCV"],
|
|
"HasSideEffects": true
|
|
},
|
|
"AXFlag": {
|
|
"Desc": ["After an FCmp, converts NZCV flags from the Arm format to a mysterious eXternal format"],
|
|
"HasSideEffects": true
|
|
},
|
|
"RmifNZCV GPR:$Src, u8:$Rotate, u8:$Mask": {
|
|
"Desc": ["Rotate, mask, and insert into NZCV on FlagM platforms"],
|
|
"HasSideEffects": true
|
|
},
|
|
"CondAddNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2, CondClass:$Cond, u8:$FalseNZCV": {
|
|
"Desc": ["If condition is true, set NZCV per sum of GPRs, else force NZCV to a constant."],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"CondSubNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2, CondClass:$Cond, u8:$FalseNZCV": {
|
|
"Desc": ["If condition is true, set NZCV per difference of GPRs, else force NZCV to a constant."],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AdcWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Adds and set NZCV for the sum of two GPRs and carry-in given as NZCV"],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AdcZero OpSize:#Size, GPR:$Src1": {
|
|
"Desc": ["Adds GPR with inverted carry-in"],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AdcZeroWithFlags OpSize:#Size, GPR:$Src1": {
|
|
"Desc": ["Adds and set NZCV for the sum of GPR and inverted carry-in given as NZCV"],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = SbbWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Subtracts and set NZCV for the difference of two GPRs and carry-in given as NZCV"],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"AdcNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Set NZCV for the sum of two GPRs and carry-in given as NZCV"],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"SbbNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Set NZCV for the difference of two GPRs and carry-in given as NZCV"],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Sub OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": [ "Integer Sub",
|
|
"Will truncate to 64 or 32bits"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = SubShift OpSize:#Size, GPR:$Src1, GPR:$Src2, ShiftType:$Shift{ShiftType::LSL}, u8:$ShiftAmount{0}": {
|
|
"Desc": [ "Integer Sub with shifted register",
|
|
"Will truncate to 64 or 32bits"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit",
|
|
"Shift != ShiftType::ROR"
|
|
]
|
|
},
|
|
"GPR = SubWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": [ "Integer Sub. Truncates and sets NZCV per SubNZCV"],
|
|
"DestSize": "Size",
|
|
"HasSideEffects": true,
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"CmpPairZ OpSize:#Size, GPR:$Src1Lo, GPR:$Src1Hi, GPR:$Src2Lo, GPR:$Src2Hi": {
|
|
"Desc": ["Compares register pairs and sets Z accordingly, preserving N/Z/V.",
|
|
"This accelerates cmpxchg."],
|
|
"HasSideEffects": true,
|
|
"DestSize": "Size"
|
|
},
|
|
"SubNZCV OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Set NZCV for the difference of two GPRs. ",
|
|
"Carry flag uses arm64 definition, inverted x86.",
|
|
""],
|
|
"DestSize": "Size",
|
|
"HasSideEffects": true
|
|
},
|
|
"GPR = Or OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer binary or"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Orlshl OpSize:#Size, GPR:$Src1, GPR:$Src2, u8:$BitShift": {
|
|
"Desc": ["Integer binary or with logical shift left"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Orlshr OpSize:#Size, GPR:$Src1, GPR:$Src2, u8:$BitShift": {
|
|
"Desc": ["Integer binary or with logical shift right"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Ornror OpSize:#Size, GPR:$Src1, GPR:$Src2, u8:$BitShift": {
|
|
"Desc": ["Integer binary or with NOT on second source and rotation right"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Xor OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer binary exclusive or"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = XorShift OpSize:#Size, GPR:$Src1, GPR:$Src2, ShiftType:$Shift{ShiftType::LSL}, u8:$ShiftAmount{0}": {
|
|
"Desc": [ "Integer binary exclusive or with shifted register"],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = XornShift OpSize:#Size, GPR:$Src1, GPR:$Src2, ShiftType:$Shift{ShiftType::LSL}, u8:$ShiftAmount{0}": {
|
|
"Desc": [ "Integer binary exclusive or not with shifted register"],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = And OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer binary and"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = AndWithFlags OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer binary and"
|
|
],
|
|
"DestSize": "Size",
|
|
"TiedSource": 0,
|
|
"HasSideEffects": true
|
|
},
|
|
"GPR = Andn OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer binary AND NOT. Performs the equivalent of Src1 & ~Src2"],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"TestNZ OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Set NZCV for the binary AND of two GPRs, setting N and Z accordingly and zeroing C and V"],
|
|
"DestSize": "Size",
|
|
"HasSideEffects": true
|
|
},
|
|
"GPR = Lshl OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer logical shift left"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Lshr OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer logical shift right"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Ashr OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer arithmetic shift right"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = ShiftFlags OpSize:$Size, GPR:$Result, GPR:$Src1, ShiftType:$Shift, GPR:$Src2, GPR:$PFInput, i1:$InvertCF": {
|
|
"Desc": ["Set NZCV flags for specified variable integer shift with given result.",
|
|
"Returns updated raw PF."],
|
|
"HasSideEffects": true,
|
|
"DestSize": "8"
|
|
},
|
|
"RotateFlags OpSize:$Size, GPR:$Result, GPR:$Shift, i1:$Left": {
|
|
"Desc": ["Set NZCV flags for specified variable integer rotate with given result."],
|
|
"HasSideEffects": true
|
|
},
|
|
"GPR = Ror OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer rotate right"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Mul OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer signed multiplication"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = UMul OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer unsigned multiplication"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = UMull GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer unsigned multiplication long",
|
|
"Multiplies two 32-bit numbers, returning a 64-bit destination register."
|
|
],
|
|
"DestSize": "FEXCore::IR::OpSize::i64Bit"
|
|
},
|
|
"GPR = SMull GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer signed multiplication long",
|
|
"Multiplies two 32-bit numbers, returning a 64-bit destination register."
|
|
],
|
|
"DestSize": "FEXCore::IR::OpSize::i64Bit"
|
|
},
|
|
"GPR = Div OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer signed division"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = UDiv OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer unsigned division"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Rem OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer signed remainder"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = URem OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer unsigned remainder"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i8Bit || Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = MulH OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer signed multiply returning high results",
|
|
"op:",
|
|
"Tmp <size * 2> = Src1 * Src2;",
|
|
"Dest = Tmp >> (size * 8);"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = UMulH OpSize:#Size, GPR:$Src1, GPR:$Src2": {
|
|
"Desc": ["Integer unsigned multiply returning high results",
|
|
"op:",
|
|
"Tmp <size * 2> = Src1 * Src2;",
|
|
"Dest = Tmp >> (size * 8);"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Bfi OpSize:#Size, u8:$Width, u8:$lsb, GPR:$Dest, GPR:$Src": {
|
|
"Desc": ["Copies a bitfield from one GPR to another",
|
|
"The source bitfield is from Src[Width:0]",
|
|
"The bitfield is copied in to Dest[(Width + lsb):lsb]"
|
|
],
|
|
"DestSize": "Size",
|
|
"TiedSource": 0,
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Bfxil OpSize:#Size, u8:$Width, u8:$lsb, GPR:$Dest, GPR:$Src": {
|
|
"Desc": ["Copies a bitfield from one GPR to another",
|
|
"Inserting in to the low bits of the destination",
|
|
"The source bitfield is from Src[(Width + lsb):lsb]",
|
|
"The bitfield is copied in to Dest[Width:0]"
|
|
],
|
|
"DestSize": "Size",
|
|
"TiedSource": 0,
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Bfe OpSize:#Size, u8:$Width, u8:$lsb, GPR:$Src": {
|
|
"Desc": ["Extracts a bitfield from one GPR with zext",
|
|
"The source bitfield is from Src[Width:0]",
|
|
"The bitfield is then zero extended"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Sbfe OpSize:#Size, u8:$Width, u8:$lsb, GPR:$Src": {
|
|
"Desc": ["Extracts a bitfield from one GPR with sext",
|
|
"The source bitfield is from Src[Width:0]",
|
|
"The bitfield is then sign extended"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = NZCVSelect OpSize:#ResultSize, CondClass:$Cond, GPR:$TrueVal, GPR:$FalseVal": {
|
|
"Desc": ["Select based on value in NZCV flags",
|
|
"op:",
|
|
"Dest = Cond ? TrueVal : FalseVal"
|
|
],
|
|
"DestSize": "ResultSize",
|
|
"EmitValidation": [
|
|
"ResultSize == FEXCore::IR::OpSize::i32Bit || ResultSize == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = NZCVSelectIncrement OpSize:#ResultSize, CondClass:$Cond, GPR:$TrueVal, GPR:$FalseVal": {
|
|
"Desc": ["Select and increment based on value in NZCV flags",
|
|
"op:",
|
|
"Dest = Cond ? TrueVal : (FalseVal + 1)"
|
|
],
|
|
"DestSize": "ResultSize",
|
|
"EmitValidation": [
|
|
"ResultSize == FEXCore::IR::OpSize::i32Bit || ResultSize == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = Select OpSize:#ResultSize, OpSize:$CompareSize, CondClass:$Cond, SSA:$Cmp1, SSA:$Cmp2, GPR:$TrueVal, GPR:$FalseVal": {
|
|
"Desc": ["Ternary selection of GPRs",
|
|
"op:",
|
|
"Dest = Cmp1 <Cond> Cmp2 ? TrueVal : FalseVal"
|
|
],
|
|
"DestSize": "ResultSize",
|
|
"ImplicitFlagClobber": true,
|
|
"EmitValidation": [
|
|
"CompareSize == FEXCore::IR::OpSize::i32Bit || CompareSize == FEXCore::IR::OpSize::i64Bit || CompareSize == FEXCore::IR::OpSize::i128Bit",
|
|
"ResultSize == FEXCore::IR::OpSize::i32Bit || ResultSize == FEXCore::IR::OpSize::i64Bit",
|
|
"WalkFindRegClass($Cmp1) == WalkFindRegClass($Cmp2)"
|
|
]
|
|
},
|
|
"GPR = Extr OpSize:#Size, GPR:$Upper, GPR:$Lower, u8:$LSB": {
|
|
"Desc": ["Concats the two GPRs to create a value that is the size of the full two GPRs",
|
|
"It then extracts a bitfield width that size of a GPR from the LSB",
|
|
"Valid LSB range is 0-31 for 32bit and 0-63 for 64bit",
|
|
"<Size * 2> ConcatValue = $Upper:$Lower",
|
|
"Result = ConcatValue<LSB+Size - 1: LSB>"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = PDep OpSize:#Size, GPR:$Input, GPR:$Mask": {
|
|
"Desc": ["Performs a parallel bit deposit.",
|
|
"Takes the contiguous low-order bits and deposits them into",
|
|
"the destination at the locations specified by the Mask."
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
|
|
"GPR = PExt OpSize:#Size, GPR:$Input, GPR:$Mask": {
|
|
"Desc": ["Performs a parallel bit extract.",
|
|
"Each bit set in the mask will select the corresponding bit in the Input",
|
|
"and transfers them to the lower contiguous bits in the destination."
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
|
|
"GPR = LDiv OpSize:#Size, GPR:$Lower, GPR:$Upper, GPR:$Divisor": {
|
|
"Desc": ["Integer long unsigned division returning lower bits",
|
|
"The Lower and Upper registers will be concated together to generate a dividend twice the size",
|
|
"Then the divisor divides the temporary dividend and returns the results in the original sized register"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = LUDiv OpSize:#Size, GPR:$Lower, GPR:$Upper, GPR:$Divisor": {
|
|
"Desc": ["Integer long unsigned division returning lower bits",
|
|
"The Lower and Upper registers will be concated together to generate a dividend twice the size",
|
|
"Then the divisor divides the temporary dividend and returns the results in the original sized register"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = LRem OpSize:#Size, GPR:$Lower, GPR:$Upper, GPR:$Divisor": {
|
|
"Desc": ["Integer long signed remainder returning lower bits",
|
|
"The Lower and Upper registers will be concated together to generate a dividend twice the size",
|
|
"Then the divisor divides the temporary dividend and returns the remainder results in the original sized register"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
"GPR = LURem OpSize:#Size, GPR:$Lower, GPR:$Upper, GPR:$Divisor": {
|
|
"Desc": ["Integer long unsigned remainder returning lower bits",
|
|
"The Lower and Upper registers will be concated together to generate a dividend twice the size",
|
|
"Then the divisor divides the temporary dividend and returns the remainder results in the original sized register"
|
|
],
|
|
"DestSize": "Size",
|
|
"EmitValidation": [
|
|
"Size == FEXCore::IR::OpSize::i16Bit || Size == FEXCore::IR::OpSize::i32Bit || Size == FEXCore::IR::OpSize::i64Bit"
|
|
]
|
|
},
|
|
|
|
"Float to GPR": {"Ignore": 1},
|
|
"GPR = VExtractToGPR u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$Index": {
|
|
"Desc": ["Extracts an element from a vector and places it in a GPR",
|
|
"The element that is extracted from the vector is zero extended to the GPR size"
|
|
],
|
|
"DestSize": "ElementSize"
|
|
},
|
|
|
|
"GPR = Float_ToGPR_S u8:#DestElementSize, u8:$SrcElementSize, FPR:$Scalar": {
|
|
"Desc": ["Moves the scalar element to a GPR with conversion",
|
|
"Converts the 32bit or 64bit float to an signed integer",
|
|
"Rounding mode determined by host flag's rounding mode"
|
|
],
|
|
"DestSize": "DestElementSize"
|
|
},
|
|
|
|
"GPR = Float_ToGPR_ZS u8:#DestElementSize, u8:$SrcElementSize, FPR:$Scalar": {
|
|
"Desc": ["Moves the scalar element to a GPR with conversion",
|
|
"Converts the 32bit or 64bit float to an signed integer rounding towards zero (Truncating)"
|
|
],
|
|
"DestSize": "DestElementSize"
|
|
},
|
|
|
|
"FCmp u8:$ElementSize, FPR:$Scalar1, FPR:$Scalar2": {
|
|
"Desc": ["Does a scalar unordered compare and sets NZCV accordingly.",
|
|
"NZCV follows Arm conventions, a separate AXFLAG instruction is required for x86",
|
|
"Ordering flag result is true if either float input is NaN"
|
|
],
|
|
"HasSideEffects": true
|
|
}
|
|
},
|
|
"VectorScalar": {
|
|
"FPR = VFAddScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'add' between Vector1 and Vector2.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFSubScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'sub' between Vector1 and Vector2.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFMulScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'mul' between Vector1 and Vector2.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFDivScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'div' between Vector1 and Vector2.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFMinScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'min' between Vector1 and Vector2.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics.",
|
|
"Additionally matches x86 zero and NaN semantics",
|
|
"If both source operands are zero, return the second operand (in the case of negative and positive zero)",
|
|
"If either source operand is NaN then return the second operand."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"ImplicitFlagClobber": true
|
|
},
|
|
"FPR = VFMaxScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'max' between Vector1 and Vector2.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics.",
|
|
"Additionally matches x86 zero and NaN semantics",
|
|
"If both source operands are zero, return the second operand (in the case of negative and positive zero)",
|
|
"If either source operand is NaN then return the second operand."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"ImplicitFlagClobber": true
|
|
},
|
|
"FPR = VFSqrtScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'sqrt' on Vector2, inserting in to Vector1 and storing in to the destination.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFRSqrtScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'rsqrt' on Vector2, inserting in to Vector1 and storing in to the destination.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFRecpScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'recip' on Vector2, inserting in to Vector1 and storing in to the destination.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFToFScalarInsert OpSize:#RegisterSize, u8:#DstElementSize, u8:$SrcElementSize, FPR:$Vector1, FPR:$Vector2, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'cvt' between Vector1 and Vector2.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / DstElementSize"
|
|
},
|
|
"FPR = VSToFVectorInsert OpSize:#RegisterSize, u8:#DstElementSize, u8:$SrcElementSize, FPR:$Vector1, FPR:$Vector2, i8:$HasTwoElements, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a Vector 'scvt' between Vector1 and Vector2.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics.",
|
|
"HasTwoElements is slightly different than most of these scalar operations.",
|
|
"Handles the edge case of cvtpi2ps xmm0, mm0 which is two elements in the lower 64-bits"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / DstElementSize"
|
|
},
|
|
"FPR = VSToFGPRInsert OpSize:#RegisterSize, u8:#DstElementSize, u8:$SrcElementSize, FPR:$Vector, GPR:$Src, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'cvt' between Vector1 and GPR.",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / DstElementSize"
|
|
},
|
|
"FPR = VFToIScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, RoundType:$Round, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar round float to integral on Vector2, inserting in to Vector1 and storing in to the destination.",
|
|
"Rounding mode determined by argument",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFCMPScalarInsert OpSize:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, FloatCompareOp:$Op, i1:$ZeroUpperBits": {
|
|
"Desc": ["Does a scalar 'cmp' between Vector1 and Vecto2, inserting in to Vector1 and storing in to the destination.",
|
|
"Compare op determined by argument",
|
|
"Inserting the result in to the lower element of Vector1 and returning the results.",
|
|
"If ZeroUpperBits is set then in a 256-bit wide operation it will zero the upper 128-bits of the destination.",
|
|
"For 128-bit operation this matches SSE insert semantics.",
|
|
"For 256-bit operation with ZeroUpperBits, this matches AVX insert semantics."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFMLAScalarInsert u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": {
|
|
"Desc": [
|
|
"Dest = (Vector1 * Vector2) + Addend",
|
|
"This explicitly matches x86 FMA semantics because ARM semantics are mind-bending."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"TiedSource": 2
|
|
},
|
|
"FPR = VFMLSScalarInsert u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": {
|
|
"Desc": [
|
|
"Dest = (Vector1 * Vector2) - Addend",
|
|
"This explicitly matches x86 FMA semantics because ARM semantics are mind-bending."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"TiedSource": 2
|
|
},
|
|
"FPR = VFNMLAScalarInsert u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": {
|
|
"Desc": [
|
|
"Dest = (-Vector1 * Vector2) + Addend",
|
|
"This explicitly matches x86 FMA semantics because ARM semantics are mind-bending."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"TiedSource": 2
|
|
},
|
|
"FPR = VFNMLSScalarInsert u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": {
|
|
"Desc": [
|
|
"Dest = (-Vector1 * Vector2) - Addend",
|
|
"This explicitly matches x86 FMA semantics because ARM semantics are mind-bending."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"TiedSource": 2
|
|
}
|
|
},
|
|
"Vector": {
|
|
"FPR = VMov u8:#RegisterSize, FPR:$Source": {
|
|
"Desc" : ["Copy vector register",
|
|
"When Register size is smaller than Source register size,",
|
|
"this op is defined to truncate and zero extend"
|
|
],
|
|
"DestSize": "RegisterSize"
|
|
},
|
|
|
|
"FPR = VectorImm u8:#RegisterSize, u8:#ElementSize, u8:$Immediate, u8:$ShiftAmount{0}": {
|
|
"Desc": ["Generates a vector with each element containg the immediate zexted"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = LoadNamedVectorConstant u8:#RegisterSize, NamedVectorConstant:$Constant": {
|
|
"Desc": ["Load a named vector constant.",
|
|
"The list of vector constants can be found in <FEXCore/IR/IR.h>"
|
|
],
|
|
"DestSize": "RegisterSize"
|
|
},
|
|
"FPR = LoadNamedVectorIndexedConstant u8:#RegisterSize, IndexNamedVectorConstant:$Constant, u32:$Index": {
|
|
"Desc": ["Load a named vector constant from Indexable table.",
|
|
"Index needs to be aligned register size.",
|
|
"The list of indexable vector constants can be found in <FEXCore/IR/IR.h>"
|
|
],
|
|
"DestSize": "RegisterSize"
|
|
},
|
|
"FPR = VNeg u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VNot u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VAbs u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": ["Does an signed integer absolute"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VPopcount u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": ["Does a popcount for each element of the register"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VAddV u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": ["Does a horizontal vector add of elements across the source vector",
|
|
"Result is a zero extended scalar"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUMinV u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": ["Does a horizontal vector unsigned minimum of elements across the source vector",
|
|
"Result is a zero extended scalar"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUMaxV u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": ["Does a horizontal vector unsigned maximum of elements across the source vector",
|
|
"Result is a zero extended scalar"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFAbs u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VFNeg u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VFRecp u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VFSqrt u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VFRSqrt u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VCMPEQZ u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VCMPGTZ u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": ["Vector compare signed greater than",
|
|
"Each element is compared, if the result is true then the resulting element is ~0, else zero",
|
|
"Compares the vector against zero"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VCMPLTZ u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": ["Vector compare signed less than",
|
|
"Each element is compared, if the result is true then the resulting element is ~0, else zero",
|
|
"Compares the vector against zero"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VDupElement u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$Index": {
|
|
"Desc": ["Duplicates one element from the source register across the whole register"],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VShlI u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUShrI u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUShraI u8:#RegisterSize, u8:#ElementSize, FPR:$DestVector, FPR:$Vector, u8:$BitShift": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VSShrI u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VUShrNI u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": {
|
|
"TiedSource": 0,
|
|
"Desc": "Unsigned shifts right each element and then narrows to the next lower element size",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize >> 1)"
|
|
},
|
|
|
|
"FPR = VUShrNI2 u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper, u8:$BitShift": {
|
|
"TiedSource": 0,
|
|
"Desc": ["Unsigned shifts right each element and then narrows to the next lower element size",
|
|
"Inserts results in to the high elements of the first argument"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize >> 1)"
|
|
},
|
|
"FPR = VSXTL u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": "Sign extends elements from the source element size to the next size up",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VSXTL2 u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": ["Sign extends elements from the source element size to the next size up",
|
|
"Source elements come from the upper half of the register"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VSSHLL u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift{0}": {
|
|
"Desc": "Sign extends elements from the source element size to the next size up",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VSSHLL2 u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift{0}": {
|
|
"Desc": ["Sign extends elements from the source element size to the next size up",
|
|
"Source elements come from the upper half of the register"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VUXTL u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": "Zero extends elements from the source element size to the next size up",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VUXTL2 u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": ["Zero extends elements from the source element size to the next size up",
|
|
"Source elements come from the upper half of the register"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VSQXTN u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize >> 1)"
|
|
},
|
|
"FPR = VSQXTN2 u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize >> 1)"
|
|
},
|
|
"FPR = VSQXTNPair u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"Desc": ["Does both VSQXTN and VSQXTN2 in a combined operation."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize >> 1)"
|
|
},
|
|
"FPR = VSQXTUN u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize >> 1)"
|
|
},
|
|
"FPR = VSQXTUN2 u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize >> 1)"
|
|
},
|
|
"FPR = VSQXTUNPair u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"Desc": ["Does both VSQXTUN and VSQXTUN2 in a combined operation."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize >> 1)"
|
|
},
|
|
"FPR = VSRSHR u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": {
|
|
"Desc": ["Signed rounding shift right by immediate",
|
|
"Exactly matching Arm64 srshr semantics"
|
|
],
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VSQSHL u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, u8:$BitShift": {
|
|
"Desc": ["Signed satuating shift left by immediate",
|
|
"Exactly matching Arm64 sqshl semantics"
|
|
],
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VRev32 u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc" : ["Reverses elements in 32-bit halfwords",
|
|
"Available element size: 1byte, 2 byte"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VRev64 u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc" : ["Reverses elements in 64-bit halfwords",
|
|
"Available element size: 1byte, 2 byte, 4 byte"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VAdd u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VSub u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VAnd u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VAndn u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VOr u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VXor u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VUQAdd u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VUQSub u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VSQAdd u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VSQSub u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VAddP u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"Desc": "Does a horizontal pairwise add of elements across the two source vectors",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VURAvg u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"Desc": ["Does an unsigned rounded average", "dst_elem = (src1_elem + src2_elem + 1) >> 1"],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUMin u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUMax u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VSMin u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VSMax u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VZip u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VZip2 u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUnZip u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUnZip2 u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VTrn u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VTrn2 u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VFAdd u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFAddP u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"Desc": "Does a horizontal pairwise add of elements across the two source vectors with float element types",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFAddV u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": ["Does a horizontal float vector add of elements across the source vector",
|
|
"Result is a zero extended scalar"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFSub u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFMul u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFDiv u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VFMin u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFMax u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VMul u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUMull u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VSMull u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"Desc": [ "Does a signed integer multiply with extend.",
|
|
"ElementSize is the source size"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VUMull2 u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"Desc": "Multiplies the high elements with size extension",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VSMull2 u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"Desc": "Multiplies the high elements with size extension",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VUMulH u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"Desc": "Wide unsigned multiply returning the high results",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VSMulH u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"Desc": "Wide signed multiply returning the high results",
|
|
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUABDL u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"Desc": ["Unsigned Absolute Difference Long"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VUABDL2 u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"Desc": ["Unsigned Absolute Difference Long",
|
|
"Using the high elements of the source vectors"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)"
|
|
},
|
|
"FPR = VUShl u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftVector, i1:$RangeCheck": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUShr u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftVector, i1:$RangeCheck": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VSShr u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftVector, i1:$RangeCheck": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUShlS u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUShrS u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VSShrS u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUShrSWide u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VSShrSWide u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VUShlSWide u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, FPR:$ShiftScalar": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VInsElement u8:#RegisterSize, u8:#ElementSize, u8:$DestIdx, u8:$SrcIdx, FPR:$DestVector, FPR:$SrcVector": {
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VInsGPR u8:#RegisterSize, u8:#ElementSize, u8:$DestIdx, FPR:$DestVector, GPR:$Src": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VExtr u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper, u8:$Index": {
|
|
"Desc": ["Concats two vector registers together and extracts a full width register from the element index",
|
|
"Index is an element index. So it is offset by ElementSize argument",
|
|
"op:",
|
|
"TmpVector <RegisterSize *2> = concat(Upper:Lower)",
|
|
"Dest = TmpVector >> (ElementSize * Index * 8); // Or can be thought of `concat(&TmpVector[Index], i128)`"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VCMPEQ u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VCMPGT u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"Desc": ["Vector compare signed greater than",
|
|
"Each element is compared, if the result is true then the resulting element is ~0, else zero"
|
|
],
|
|
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFCMPEQ u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFCMPNEQ u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFCMPLT u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFCMPGT u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFCMPLE u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFCMPORD u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFCMPUNO u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VTBL1 u8:#RegisterSize, FPR:$VectorTable, FPR:$VectorIndices": {
|
|
"Desc": ["Does a vector table lookup from one register in to the destination",
|
|
"Lookup is byte sized per byte element.",
|
|
"Any index larger than what the registers provide will result in zero for that element",
|
|
"Table is always treated as a 128bit register",
|
|
"Indices matches destination size. Either 64bit or 128bit"
|
|
],
|
|
"DestSize": "RegisterSize"
|
|
},
|
|
"FPR = VTBL2 u8:#RegisterSize, FPR:$VectorTable1, FPR:$VectorTable2, FPR:$VectorIndices": {
|
|
"Desc": ["Does a vector table lookup from two registers in to the destination",
|
|
"Lookup is byte sized per byte element.",
|
|
"Any index larger than what the registers provide will result in zero for that element",
|
|
"Table is always treated as a two 128bit registers",
|
|
"Indices matches destination size. Either 64bit or 128bit",
|
|
"Careful about not using sequential table registers, will result in some moves if they aren't sequential."
|
|
],
|
|
"DestSize": "RegisterSize"
|
|
},
|
|
"FPR = VTBX1 u8:#RegisterSize, FPR:$VectorSrcDst, FPR:$VectorTable, FPR:$VectorIndices": {
|
|
"Desc": ["Does a vector table lookup from one register in to the destination",
|
|
"Lookup is byte sized per byte element.",
|
|
"Any index larger than what the registers provide will result in not modifying that element",
|
|
"Table is always treated as a 128bit register",
|
|
"Indices matches destination size. Either 64bit or 128bit"
|
|
],
|
|
"TiedSource": 0,
|
|
"DestSize": "RegisterSize"
|
|
},
|
|
"FPR = VBSL u8:#RegisterSize, FPR:$VectorMask, FPR:$VectorTrue, FPR:$VectorFalse": {
|
|
"Desc": ["Does a vector bitwise select.",
|
|
"If the bit in the field is 1 then the corresponding bit is pulled from VectorTrue",
|
|
"If the bit in the field is 0 then the corresponding bit is pulled from VectorFalse"
|
|
],
|
|
"DestSize": "RegisterSize"
|
|
},
|
|
|
|
"GPR = VPCMPESTRX FPR:$LHS, FPR:$RHS, GPR:$RAX, GPR:$RDX, u16:$Control": {
|
|
"Desc": ["Performs intermediate behavior analogous to the x86 PCMPESTRI/PCMPESTRM instruction",
|
|
"This will return the intermediate result of a PCMPESTR-type operation, but NOT the final",
|
|
"result. This must be derived from the intermediate result",
|
|
|
|
"NOTE: On top of returning the intermediate result, the returned value also combines the status",
|
|
"flags into the upper 16-bits of the 32-bit result, as these can also be derived over the",
|
|
"course of creating the intermediate result"
|
|
],
|
|
"DestSize": "4",
|
|
"JITDispatch": false
|
|
},
|
|
"GPR = VPCMPISTRX FPR:$LHS, FPR:$RHS, u8:$Control": {
|
|
"Desc": ["Performs intermediate behavior analogous to the x86 PCMPISTRI/PCMPISTRM instruction",
|
|
"This will return the intermediate result of a PCMPISTR-type operation, but NOT the final",
|
|
"result. This must be derived from the intermediate result",
|
|
|
|
"NOTE: On top of returning the intermediate result, the returned value also combines the status",
|
|
"flags into the upper 16-bits of the 32-bit result, as these can also be derived over the",
|
|
"course of creating the intermediate result"
|
|
],
|
|
"DestSize": "4",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = VFCADD u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, u16:$Rotate": {
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = VFMLA u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": {
|
|
"Desc": [
|
|
"Dest = (Vector1 * Vector2) + Addend",
|
|
"This explicitly matches x86 FMA semantics because ARM semantics are mind-bending."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"TiedSource": 2
|
|
},
|
|
"FPR = VFMLS u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": {
|
|
"Desc": [
|
|
"Dest = (Vector1 * Vector2) - Addend",
|
|
"This explicitly matches x86 FMA semantics because ARM semantics are mind-bending."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"TiedSource": 2
|
|
},
|
|
"FPR = VFNMLA u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": {
|
|
"Desc": [
|
|
"Dest = (-Vector1 * Vector2) + Addend",
|
|
"This explicitly matches x86 FMA semantics because ARM semantics are mind-bending."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"TiedSource": 2
|
|
},
|
|
"FPR = VFNMLS u8:#RegisterSize, u8:#ElementSize, FPR:$Vector1, FPR:$Vector2, FPR:$Addend": {
|
|
"Desc": [
|
|
"Dest = (-Vector1 * Vector2) - Addend",
|
|
"This explicitly matches x86 FMA semantics because ARM semantics are mind-bending."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize",
|
|
"TiedSource": 2
|
|
}
|
|
},
|
|
"Conv": {
|
|
"FPR = VCastFromGPR u8:#RegisterSize, u8:#ElementSize, GPR:$Src": {
|
|
"Desc": ["Moves a GPR to a Vector register with zero extension to full length of the register.",
|
|
"No conversion is done on the data as it moves register files"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = VDupFromGPR u8:#RegisterSize, u8:#ElementSize, GPR:$Src": {
|
|
"Desc": ["Broadcasts a value in a GPR into each ElementSize-sized element in a vector"],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
|
|
"FPR = Float_FromGPR_S u8:#DstElementSize, u8:$SrcElementSize, GPR:$Src": {
|
|
"Desc": ["Scalar op: Converts signed GPR to Scalar float",
|
|
"Zeroes the upper bits of the vector register"
|
|
],
|
|
"DestSize": "DstElementSize"
|
|
},
|
|
"FPR = Float_FToF u8:#DstElementSize, u8:$SrcElementSize, FPR:$Scalar": {
|
|
"Desc": ["Scalar op: Converts float from one size to another",
|
|
"Zeroes the upper bits of the vector register"
|
|
],
|
|
"DestSize": "DstElementSize"
|
|
},
|
|
|
|
"FPR = Vector_SToF u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": "Vector op: Converts signed integer to same size float",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = Vector_FToS u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": ["Vector op: Converts float to signed integer, rounding towards zero",
|
|
"Rounding mode determined by host rounding mode"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = Vector_FToZS u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": "Vector op: Converts float to signed integer, rounding towards zero",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = Vector_FToF u8:#RegisterSize, u8:#DestElementSize, FPR:$Vector, u8:$SrcElementSize": {
|
|
"Desc": "Vector op: Converts float from source element size to destination size (fp32<->fp64)",
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / DestElementSize"
|
|
},
|
|
|
|
"FPR = VFCVTL2 u8:#RegisterSize, u8:#ElementSize, FPR:$Vector": {
|
|
"Desc": [
|
|
"Vector op: Converts float from source element size to destination size (fp32->fp64)",
|
|
"Selecting from the high half of the register."
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize << 1)",
|
|
"EmitValidation": [
|
|
"RegisterSize != FEXCore::IR::OpSize::i256Bit && \"What does 256-bit mean in this context?\""
|
|
]
|
|
},
|
|
"FPR = VFCVTN2 u8:#RegisterSize, u8:#ElementSize, FPR:$VectorLower, FPR:$VectorUpper": {
|
|
"TiedSource": 0,
|
|
"Desc": [
|
|
"Vector op: Converts float from source element size and inserting in to the high bits.",
|
|
"Bottom half is untouched",
|
|
"Narrowing to the element size below what is passed in.",
|
|
"F64->F32, F32->F16"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / (ElementSize >> 1)",
|
|
"EmitValidation": [
|
|
"RegisterSize != FEXCore::IR::OpSize::i256Bit && \"What does 256-bit mean in this context?\""
|
|
]
|
|
},
|
|
"FPR = Vector_FToI u8:#RegisterSize, u8:#ElementSize, FPR:$Vector, RoundType:$Round": {
|
|
"Desc": ["Vector op: Rounds float to integral",
|
|
"Rounding mode determined by argument"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / ElementSize"
|
|
},
|
|
"FPR = Vector_F64ToI32 u8:#RegisterSize, FPR:$Vector, RoundType:$Round, i1:$EnsureZeroUpperHalf": {
|
|
"Desc": ["Vector op: Rounds 64-bit float to 32-bit integral with round mode",
|
|
"Matches CVTPD2DQ/CVTTPD2DQ behaviour"
|
|
],
|
|
"DestSize": "RegisterSize",
|
|
"NumElements": "RegisterSize / FEXCore::IR::OpSize::i32Bit"
|
|
}
|
|
},
|
|
"Crypto": {
|
|
"FPR = VAESImc FPR:$Vector": {
|
|
"Desc": "Does a stage of the inverse mix column transformation",
|
|
"DestSize": "16"
|
|
},
|
|
"FPR = VAESEnc u8:#RegisterSize, FPR:$State, FPR:$Key, FPR:$ZeroReg": {
|
|
"Desc": "Does a step of AES encryption",
|
|
"DestSize": "RegisterSize"
|
|
},
|
|
"FPR = VAESEncLast u8:#RegisterSize, FPR:$State, FPR:$Key, FPR:$ZeroReg": {
|
|
"Desc": "Does the last step of AES encryption",
|
|
"DestSize": "RegisterSize"
|
|
},
|
|
"FPR = VAESDec u8:#RegisterSize, FPR:$State, FPR:$Key, FPR:$ZeroReg": {
|
|
"Desc": "Does a step of AES decryption",
|
|
"DestSize": "RegisterSize"
|
|
},
|
|
"FPR = VAESDecLast u8:#RegisterSize, FPR:$State, FPR:$Key, FPR:$ZeroReg": {
|
|
"Desc": "Does the last step of AES decryption",
|
|
"DestSize": "RegisterSize"
|
|
},
|
|
"FPR = VAESKeyGenAssist FPR:$Src, FPR:$KeyGenTBLSwizzle, FPR:$ZeroReg, u8:$RCON": {
|
|
"Desc": "Assists in key generation",
|
|
"DestSize": "16"
|
|
},
|
|
"FPR = VSha1H FPR:$Src": {
|
|
"Desc": "Does vector scalar SHA1H instruction",
|
|
"DestSize": "FEXCore::IR::OpSize::i32Bit"
|
|
},
|
|
"FPR = VSha256U0 FPR:$Src1, FPR:$Src2": {
|
|
"Desc": "Does vector scalar VSha256U0 instruction",
|
|
"DestSize": "FEXCore::IR::OpSize::i128Bit"
|
|
},
|
|
"GPR = CRC32 GPR:$Src1, GPR:$Src2, u8:$SrcSize": {
|
|
"Desc": ["CRC32 using polynomial 0x1EDC6F41"
|
|
],
|
|
"DestSize": "4"
|
|
},
|
|
"FPR = PCLMUL u8:#RegisterSize, FPR:$Src1, FPR:$Src2, u8:$Selector": {
|
|
"Desc": [
|
|
"Performs carryless multiplication of 64-bit elements depending on the selector.",
|
|
"Selector = 0b00000000: Uses low 64-bit elements from both input vectors",
|
|
"Selector = 0b00000001: Uses high 64-bit element from Src1 and low 64-bit element from Src2",
|
|
"Selector = 0b00010000: Uses low 64-bit element from Src1 and high 64-bit element from Src2",
|
|
"Selector = 0b00010001: Uses high 64-bit elements from both input vectors"
|
|
],
|
|
"DestSize": "RegisterSize"
|
|
}
|
|
},
|
|
"F64": {
|
|
"FPR = F64ATAN FPR:$Src1, FPR:$Src2": {
|
|
"DestSize": "8",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F64FPREM FPR:$Src1, FPR:$Src2": {
|
|
"DestSize": "8",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F64FPREM1 FPR:$Src1, FPR:$Src2": {
|
|
"DestSize": "8",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F64SCALE FPR:$Src1, FPR:$Src2": {
|
|
"DestSize": "8",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F64F2XM1 FPR:$Src": {
|
|
"DestSize": "8",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F64FYL2X FPR:$Src, FPR:$Src2": {
|
|
"DestSize": "8",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F64TAN FPR:$Src": {
|
|
"DestSize": "8",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F64SIN FPR:$Src": {
|
|
"DestSize": "8",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F64COS FPR:$Src": {
|
|
"DestSize": "8",
|
|
"JITDispatch": false
|
|
}
|
|
},
|
|
"F80": {
|
|
"GPR = SyncStackToSlow": {
|
|
"Desc": [
|
|
"Synchronizes the virtual stack environment to the physical registers.",
|
|
"Returns the current stack top."
|
|
],
|
|
"X87": true,
|
|
"HasSideEffects": true,
|
|
"DestSize": 8
|
|
},
|
|
"StackForceSlow": {
|
|
"Desc": [
|
|
"Forces the slow path."
|
|
],
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"InitStack": {
|
|
"Desc": [
|
|
"Initializes the stack by marking all tags as invalid and setting top to zero."
|
|
],
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"IncStackTop": {
|
|
"Desc": [
|
|
"Increase stack top-pointer."
|
|
],
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"DecStackTop": {
|
|
"Desc": [
|
|
"Decrease stack top-pointer."
|
|
],
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"InvalidateStack u8:$StackLocation": {
|
|
"Desc": [
|
|
"Marks the value in TOP+$StackLocation as empty / invalid 0b11.",
|
|
"If the StackLocation is 0xff, we invalidate all locations."
|
|
],
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"PushStack FPR:$X80Src, SSA:$OriginalValue, u8:$LoadSize, i1:$Float": {
|
|
"Desc": [
|
|
"Pushes the provided X80Src source on to the x87 stack.",
|
|
"Tracks OriginalValue as the original value of X80Src.",
|
|
"Opsize is 128bit for F80 values, 64-bit for low precision.",
|
|
"LoadSize the original load size, i.e. of size of OriginalValue.",
|
|
"Float: 80-bit, 64-bit, 32-bit",
|
|
"Int: 64-bit, 32-bit, 16-bit"
|
|
],
|
|
"EmitValidation": [
|
|
"WalkFindRegClass($OriginalValue) == FPRClass || WalkFindRegClass($OriginalValue) == GPRClass"
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"CopyPushStack u8:$StackLocation": {
|
|
"Desc": [
|
|
"Pushes an element already on the stack onto the top."
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"StoreStackMemory GPR:$Addr, OpSize:$SourceSize, i1:$Float, u8:$StoreSize": {
|
|
"Desc": [
|
|
"Takes the top value off the x87 stack and stores it to memory.",
|
|
"SourceSize is 128bit for F80 values, 64-bit for low precision.",
|
|
"StoreSize is the store size for conversion:",
|
|
"Float: 80-bit, 64-bit, or 32-bit",
|
|
"Int: 64-bit, 32-bit, 16-bit"
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"StoreStackToStack u8:$StackLocation": {
|
|
"Desc": [
|
|
"Takes the top value off the x87 stack and stores it to stack location TOP+StackLocation",
|
|
"Float: 80-bit, 64-bit, or 32-bit",
|
|
"Int: 64-bit, 32-bit, 16-bit"
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"PopStackDestroy": {
|
|
"Desc": [
|
|
"Pops the top value off the stack but doesn't save it anywhere."
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"FPR = ReadStackValue u8:$StackLocation": {
|
|
"Desc": [
|
|
"Reads a value off the stack at the offset"
|
|
],
|
|
"DestSize": "16",
|
|
"X87": true
|
|
},
|
|
"GPR = StackValidTag u8:$StackLocation": {
|
|
"Desc": [
|
|
"Returns 1 if the value in location TOP+$StackLocation is valid, 0 otherwise."
|
|
],
|
|
"DestSize": 4,
|
|
"X87": true
|
|
},
|
|
"F80AddStack u8:$SrcStack1, u8:$SrcStack2": {
|
|
"Desc": [
|
|
"Adds two stack locations together, storing the result in to the first stack location"
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"F80AddValue u8:$SrcStack, FPR:$X80Src": {
|
|
"Desc": [
|
|
"Adds a operand value to a stack location. The result stored in to the stack location provided."
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"FPR = F80Add FPR:$X80Src1, FPR:$X80Src2": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80SubStack u8:$DstStack, u8:$SrcStack1, u8:$SrcStack2": {
|
|
"Desc": [
|
|
"Subtracts the value in stack location TOP+$SrcStack2 from the value in stack location TOP+$SrcStack1.",
|
|
"The result is stored in stack location TOP+$DstStack."
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"F80SubValue u8:$SrcStack, FPR:$X80Src": {
|
|
"Desc": [
|
|
"Subtracts the value $X80Src from the value in stack location TOP+$SrcStack.",
|
|
"The result is stored in stack location TOP."
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"F80SubRValue FPR:$X80Src, u8:$SrcStack": {
|
|
"Desc": [
|
|
"Subtracts the value in stack location TOP+$SrcStack from the value $X80Src.",
|
|
"The result is stored in stack location TOP."
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"FPR = F80Sub FPR:$X80Src1, FPR:$X80Src2": {
|
|
"Desc": [
|
|
"Subtracts the value in $X80Src1 from the value in $X80Src2.",
|
|
"The result is returned.",
|
|
"`FPR = X80Src2 - X80Src1`"
|
|
],
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80MulStack u8:$SrcStack1, u8:$SrcStack2": {
|
|
"Desc": [
|
|
"Multiplies two stack locations together, storing the result in to the first stack location"
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"F80MulValue u8:$SrcStack, FPR:$X80Src": {
|
|
"Desc": [
|
|
"Multiplies a operand value to a stack location. The result stored in to the stack location provided."
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"FPR = F80Mul FPR:$X80Src1, FPR:$X80Src2": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80DivStack u8:$DstStack, u8:$SrcStack1, u8:$SrcStack2": {
|
|
"Desc": [
|
|
"Divides the value in stack location TOP+$SrcStack1 by the value in stack location TOP+$SrcStack2.",
|
|
"The result is stored in stack location TOP+$DstStack.",
|
|
"`FPR|Stack[TOP+DstStack] = Stack[TOP+SrcStack1] / Stack[TOP+SrcStack2]`"
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"F80DivValue u8:$SrcStack, FPR:$X80Src": {
|
|
"Desc": [
|
|
"Divides the value in stack location TOP+$SrcStack by the value $X80Src.",
|
|
"The result is stored in stack location TOP and returned.",
|
|
"`FPR|Stack[TOP] = Stack[TOP+SrcStack] / X80Src`"
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"F80DivRValue FPR:$X80Src, u8:$SrcStack": {
|
|
"Desc": [
|
|
"Divides the value X80Src by the value in stack location TOP+$SrcStack.",
|
|
"The result is stored in stack location TOP.",
|
|
"`FPR|Stack[TOP] = X80Src / Stack[TOP+SrcStack]`"
|
|
],
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"FPR = F80Div FPR:$X80Src1, FPR:$X80Src2": {
|
|
"Desc": [
|
|
"Divides the value in $X80Src1 by the value in $X80Src2.",
|
|
"The result is returned.",
|
|
"`FPR = X80Src1 / X80Src2`"
|
|
],
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80StackXchange u8:$SrcStack": {
|
|
"Desc": [
|
|
"Exchanges the value at the top of the stack with the value at TOP+$SrcStack."
|
|
],
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80StackChangeSign": {
|
|
"Desc": [
|
|
"Complements the sign bit of the value at the top of the stack.",
|
|
"Returns the new value at the top of the stack."
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "16",
|
|
"X87": true
|
|
},
|
|
"FPR = F80StackAbs": {
|
|
"Desc": [
|
|
"Clears the sign bit of the value at the top of the stack.",
|
|
"Returns the new value at the top of the stack."
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "16",
|
|
"X87": true
|
|
},
|
|
"F80PTANStack": {
|
|
"Desc": [
|
|
"Computes the approximate tangent of the source operand in register ST(0), stores the result in ST(0), and pushes a 1.0 onto the FPU register stack."
|
|
],
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80ATANStack": {
|
|
"Desc": [
|
|
"Computes arctan(st1/st0) and stores it in st0. Then pops the stack."
|
|
],
|
|
"DestSize": "16",
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80ATAN FPR:$X80Src1, FPR:$X80Src2": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80FPREMStack": {
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80FPREM FPR:$X80Src1, FPR:$X80Src2": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80FPREM1Stack": {
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80FPREM1 FPR:$X80Src1, FPR:$X80Src2": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80SCALEStack": {
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80SCALE FPR:$X80Src1, FPR:$X80Src2": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F80CVT u8:#Size, FPR:$X80Src": {
|
|
"DestSize": "Size",
|
|
"JITDispatch": false
|
|
},
|
|
"GPR = F80CVTInt u8:#Size, FPR:$X80Src, i1:$Truncate": {
|
|
"DestSize": "Size",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F80CVTTo FPR:$X80Src, u8:$SrcSize": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F80CVTToInt GPR:$Src, u8:$SrcSize": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80RoundStack": {
|
|
"Desc": [
|
|
"Replaces the value at the top of the stack with its nearest integral value."
|
|
],
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80Round FPR:$X80Src": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80F2XM1Stack": {
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80F2XM1 FPR:$X80Src": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F80TAN FPR:$X80Src": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80SINStack": {
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80SIN FPR:$X80Src": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80COSStack": {
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80COS FPR:$X80Src": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80SINCOSStack": {
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"F80SQRTStack": {
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80SQRT FPR:$X80Src": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80XTRACTStack": {
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
},
|
|
"FPR = F80XTRACT_EXP FPR:$X80Src": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F80XTRACT_SIG FPR:$X80Src": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"GPR = F80StackTest u8:$SrcStack": {
|
|
"Desc": [
|
|
"Does comparison between value in stack at TOP + SrcStack"
|
|
],
|
|
"DestSize": "4",
|
|
"X87": true
|
|
},
|
|
"GPR = F80CmpStack u8:$SrcStack": {
|
|
"Desc": [
|
|
"Does a scalar unordered compare between the value at the top of the stack and the value in stack position TOP+$SrcStack and stores the flags in to a GPR",
|
|
"Ordering flag result is true if either float input is NaN"
|
|
],
|
|
"DestSize": "4",
|
|
"X87": true
|
|
},
|
|
"GPR = F80CmpValue FPR:$X80Src": {
|
|
"Desc": [
|
|
"Does a scalar unordered compare between the value at the top of the stack and $X80Src and stores the asked for flags in to a GPR",
|
|
"Ordering flag result is true if either float input is NaN"
|
|
],
|
|
"DestSize": "4",
|
|
"HasSideEffects": true,
|
|
"X87": true
|
|
},
|
|
"GPR = F80Cmp FPR:$X80Src1, FPR:$X80Src2": {
|
|
"Desc": ["Does a scalar unordered compare and stores the flags in to a GPR",
|
|
"Ordering flag result is true if either float input is NaN"
|
|
],
|
|
"DestSize": "4",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F80BCDLoad FPR:$X80Src": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F80BCDStore FPR:$X80Src": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"FPR = F80FYL2XStack": {
|
|
"Desc": [
|
|
"Computes ST1 * log2(ST0)",
|
|
"Stores the result in ST1, and pops the top of the stack.",
|
|
"Returns the new value at the top of the stack, i.e. the result of the operation."
|
|
],
|
|
"HasSideEffects": true,
|
|
"DestSize": "16",
|
|
"X87": true
|
|
},
|
|
"FPR = F80FYL2X FPR:$X80Src1, FPR:$X80Src2": {
|
|
"DestSize": "16",
|
|
"JITDispatch": false
|
|
},
|
|
"F80VBSLStack u8:#RegisterSize, FPR:$VectorMask, u8:$SrcStack1, u8:$SrcStack2": {
|
|
"Desc": [
|
|
"Does a vector bitwise select.",
|
|
"If the bit in the field is 1 then the corresponding bit is pulled from VectorTrue",
|
|
"If the bit in the field is 0 then the corresponding bit is pulled from VectorFalse",
|
|
"Writes the result to the top of the stack."
|
|
],
|
|
"X87": true,
|
|
"HasSideEffects": true
|
|
}
|
|
},
|
|
"Backend": {
|
|
"Last": {
|
|
"HasSideEffects": true
|
|
}
|
|
}
|
|
}
|
|
}
|