mirror of
https://github.com/FEX-Emu/FEX.git
synced 2026-10-08 13:00:18 +02:00
Ryan Houdek
2feae06209
This allows us to have RCPC loadstore operations with a 9-bit signed offset. This gives us a small range of [-256,256) of immediate encoding range on our TSO loadstore operations. Updates the inline constant pass in ConstProp to support this range on TSO IR ops if the host supports RCPC2. Apple M1 supports this extension, didn't test with Cortex-X2/A710.
84 lines
2.6 KiB
C++
84 lines
2.6 KiB
C++
/*
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$info$
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meta: ir|opts ~ IR to IR Optimization
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tags: ir|opts
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desc: Defines which passes are run, and runs them
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$end_info$
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*/
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#include "Interface/Context/Context.h"
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#include "Interface/IR/PassManager.h"
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#include "Interface/IR/Passes.h"
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#include "Interface/IR/Passes/RegisterAllocationPass.h"
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#include <FEXCore/Config/Config.h>
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namespace FEXCore::IR {
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class IREmitter;
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void PassManager::AddDefaultPasses(FEXCore::Context::Context *ctx, bool InlineConstants, bool StaticRegisterAllocation) {
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FEX_CONFIG_OPT(DisablePasses, O0);
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if (!DisablePasses()) {
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InsertPass(CreateContextLoadStoreElimination());
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if (Is64BitMode()) {
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// This needs to run after RCLSE
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// This only matters for 64-bit code since these instructions don't exist in 32-bit
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InsertPass(CreateLongDivideEliminationPass());
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}
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InsertPass(CreateDeadStoreElimination());
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InsertPass(CreatePassDeadCodeElimination());
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InsertPass(CreateConstProp(InlineConstants, ctx->HostFeatures.SupportsTSOImm9));
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////// InsertPass(CreateDeadFlagCalculationEliminination());
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InsertPass(CreateSyscallOptimization());
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InsertPass(CreatePassDeadCodeElimination());
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// only do SRA if enabled and JIT
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if (InlineConstants && StaticRegisterAllocation)
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InsertPass(CreateStaticRegisterAllocationPass());
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}
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else {
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// only do SRA if enabled and JIT
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if (InlineConstants && StaticRegisterAllocation)
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InsertPass(CreateStaticRegisterAllocationPass());
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}
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// If the IR is compacted post-RA then the node indexing gets messed up and the backend isn't able to find the register assigned to a node
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// Compact before IR, don't worry about RA generating spills/fills
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InsertPass(CreateIRCompaction(ctx->OpDispatcherAllocator), "Compaction");
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}
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void PassManager::AddDefaultValidationPasses() {
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#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
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InsertValidationPass(Validation::CreatePhiValidation());
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InsertValidationPass(Validation::CreateIRValidation(), "IRValidation");
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InsertValidationPass(Validation::CreateRAValidation());
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InsertValidationPass(Validation::CreateValueDominanceValidation());
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#endif
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}
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void PassManager::InsertRegisterAllocationPass(bool OptimizeSRA) {
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InsertPass(IR::CreateRegisterAllocationPass(GetPass("Compaction"), OptimizeSRA), "RA");
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}
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bool PassManager::Run(IREmitter *IREmit) {
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bool Changed = false;
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for (auto const &Pass : Passes) {
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Changed |= Pass->Run(IREmit);
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}
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#if defined(ASSERTIONS_ENABLED) && ASSERTIONS_ENABLED
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for (auto const &Pass : ValidationPasses) {
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Changed |= Pass->Run(IREmit);
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}
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#endif
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return Changed;
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}
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}
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