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a798880ac8
Instead of having this sort of odd indirection through a struct type, we can add support for defining custom enums in the IR description. This lets us both get strong typing (and allow for weak typing, should any enum in the future need it), without needing a struct for a basic value type. Even then, if we do need a struct for anything in the future, then we still allow strong typing for values themselves while allowing them to be used in various ways.
414 lines
14 KiB
C++
414 lines
14 KiB
C++
// SPDX-License-Identifier: MIT
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/*
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$info$
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meta: ir|dumper ~ IR -> Text
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tags: ir|dumper
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$end_info$
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*/
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#include "Interface/IR/IntrusiveIRList.h"
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#include "Interface/IR/RegisterAllocationData.h"
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#include <FEXCore/IR/IR.h>
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#include <FEXCore/fextl/fmt.h>
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#include <FEXCore/fextl/sstream.h>
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#include <algorithm>
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#include <array>
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#include <ostream>
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#include <stdint.h>
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#include <string_view>
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#include <iomanip>
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namespace FEXCore::IR {
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#define IROP_GETNAME_IMPL
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#define IROP_GETRAARGS_IMPL
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#define IROP_REG_CLASSES_IMPL
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#define IROP_HASSIDEEFFECTS_IMPL
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#define IROP_SIZES_IMPL
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#define IROP_GETHASDEST_IMPL
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#include <FEXCore/IR/IRDefines.inc>
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static void PrintArg(fextl::stringstream* out, const IRListView*, const SHA256Sum& Arg) {
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*out << fextl::fmt::format("sha256:{:02x}", fmt::join(Arg.data, ""));
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, uint64_t Arg) {
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*out << fextl::fmt::format("#{:#x}", Arg);
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, CondClass Arg) {
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if (Arg == CondClass::AL) {
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*out << "ALWAYS";
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return;
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}
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static constexpr std::array<std::string_view, 22> CondNames = {"EQ", "NEQ", "UGE", "ULT", "MI", "PL", "VS", "VC",
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"UGT", "ULE", "SGE", "SLT", "SGT", "SLE", "TSTZ", "TSTNZ",
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"FLU", "FGE", "FLEU", "FGT", "FU", "FNU"};
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*out << CondNames[FEXCore::ToUnderlying(Arg)];
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, MemOffsetType Arg) {
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static constexpr std::array<std::string_view, 3> Names = {
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"SXTX",
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"UXTW",
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"SXTW",
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};
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*out << Names[Arg];
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, RegisterClassType Arg) {
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if (Arg == GPRClass.Val) {
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*out << "GPR";
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} else if (Arg == GPRFixedClass.Val) {
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*out << "GPRFixed";
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} else if (Arg == FPRClass.Val) {
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*out << "FPR";
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} else if (Arg == FPRFixedClass.Val) {
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*out << "FPRFixed";
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} else {
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*out << "Unknown Registerclass " << Arg;
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}
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}
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static void PrintArg(fextl::stringstream* out, const IRListView* IR, OrderedNodeWrapper Arg) {
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if (Arg.IsImmediate()) {
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auto PhyReg = PhysicalRegister(Arg);
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switch (PhyReg.Class) {
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case FEXCore::IR::GPRClass.Val: *out << "r"; break;
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case FEXCore::IR::GPRFixedClass.Val: *out << "R"; break;
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case FEXCore::IR::FPRClass.Val: *out << "v"; break;
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case FEXCore::IR::FPRFixedClass.Val: *out << "V"; break;
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case FEXCore::IR::ComplexClass.Val: *out << "c"; break;
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case FEXCore::IR::InvalidClass.Val: *out << "invalid"; break;
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default: *out << "unknown"; break;
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}
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if (PhyReg.Class != FEXCore::IR::InvalidClass.Val) {
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*out << std::dec << (uint32_t)PhyReg.Reg;
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}
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return;
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}
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auto [CodeNode, IROp] = IR->at(Arg)();
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const auto ArgID = Arg.ID();
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if (ArgID.IsInvalid()) {
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*out << "%Invalid";
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} else {
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*out << "%" << std::dec << ArgID;
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}
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if (GetHasDest(IROp->Op)) {
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auto ElementSize = IROp->ElementSize;
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uint32_t NumElements = 0;
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if (IROp->ElementSize == OpSize::iUnsized) {
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ElementSize = IROp->Size;
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}
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if (ElementSize != OpSize::iUnsized) {
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NumElements = IR::NumElements(IROp->Size, ElementSize);
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}
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*out << " i" << std::dec << IR::OpSizeAsBits(ElementSize);
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if (NumElements > 1) {
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*out << "v" << std::dec << NumElements;
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}
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}
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, FEXCore::IR::FenceType Arg) {
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if (Arg == IR::Fence_Load) {
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*out << "Loads";
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} else if (Arg == IR::Fence_Store) {
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*out << "Stores";
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} else if (Arg == IR::Fence_LoadStore) {
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*out << "LoadStores";
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} else {
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*out << "<Unknown Fence Type>";
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}
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, FEXCore::IR::RoundType Arg) {
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switch (Arg) {
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case FEXCore::IR::Round_Nearest: *out << "Nearest"; break;
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case FEXCore::IR::Round_Negative_Infinity: *out << "-Inf"; break;
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case FEXCore::IR::Round_Positive_Infinity: *out << "+Inf"; break;
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case FEXCore::IR::Round_Towards_Zero: *out << "Towards Zero"; break;
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case FEXCore::IR::Round_Host: *out << "Host"; break;
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default: *out << "<Unknown Round Type>"; break;
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}
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, FEXCore::IR::SyscallFlags Arg) {
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switch (Arg) {
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case FEXCore::IR::SyscallFlags::DEFAULT: *out << "Default"; break;
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case FEXCore::IR::SyscallFlags::OPTIMIZETHROUGH: *out << "Optimize Through"; break;
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case FEXCore::IR::SyscallFlags::NOSYNCSTATEONENTRY: *out << "No Sync State on Entry"; break;
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case FEXCore::IR::SyscallFlags::NORETURN: *out << "No Return"; break;
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case FEXCore::IR::SyscallFlags::NOSIDEEFFECTS: *out << "No Side Effects"; break;
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default: *out << "<Unknown Round Type>"; break;
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}
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, FEXCore::IR::NamedVectorConstant Arg) {
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*out << [Arg] {
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// clang-format off
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switch (Arg) {
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case NamedVectorConstant::NAMED_VECTOR_INCREMENTAL_U16_INDEX:
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return "u16_incremental_index";
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case NamedVectorConstant::NAMED_VECTOR_INCREMENTAL_U16_INDEX_UPPER:
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return "u16_incremental_index_upper";
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case NamedVectorConstant::NAMED_VECTOR_PADDSUBPS_INVERT:
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return "addsubps_invert";
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case NamedVectorConstant::NAMED_VECTOR_PADDSUBPS_INVERT_UPPER:
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return "addsubps_invert_upper";
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case NamedVectorConstant::NAMED_VECTOR_PADDSUBPD_INVERT:
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return "addsubpd_invert";
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case NamedVectorConstant::NAMED_VECTOR_PADDSUBPD_INVERT_UPPER:
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return "addsubpd_invert_upper";
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case NamedVectorConstant::NAMED_VECTOR_PSUBADDPS_INVERT:
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return "subaddps_invert";
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case NamedVectorConstant::NAMED_VECTOR_PSUBADDPS_INVERT_UPPER:
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return "subaddps_invert_upper";
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case NamedVectorConstant::NAMED_VECTOR_PSUBADDPD_INVERT:
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return "subaddpd_invert";
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case NamedVectorConstant::NAMED_VECTOR_PSUBADDPD_INVERT_UPPER:
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return "subaddpd_invert_upper";
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case NamedVectorConstant::NAMED_VECTOR_MOVMSKPS_SHIFT:
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return "movmskps_shift";
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case NamedVectorConstant::NAMED_VECTOR_AESKEYGENASSIST_SWIZZLE:
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return "aeskeygenassist_swizzle";
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case NamedVectorConstant::NAMED_VECTOR_ZERO:
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return "vectorzero";
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case NamedVectorConstant::NAMED_VECTOR_X87_ONE:
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return "x87_1_0";
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case NamedVectorConstant::NAMED_VECTOR_X87_LOG2_10:
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return "x87_log2_10";
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case NamedVectorConstant::NAMED_VECTOR_X87_LOG2_E:
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return "x87_log2_e";
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case NamedVectorConstant::NAMED_VECTOR_X87_PI:
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return "x87_pi";
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case NamedVectorConstant::NAMED_VECTOR_X87_LOG10_2:
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return "x87_log10_2";
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case NamedVectorConstant::NAMED_VECTOR_X87_LOG_2:
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return "x87_log2";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F32_I32:
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return "cvtmax_f32_i32";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F32_I32_UPPER:
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return "cvtmax_f32_i32_upper";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F32_I64:
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return "cvtmax_f32_i64";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F64_I32:
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return "cvtmax_f64_i32";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F64_I32_UPPER:
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return "cvtmax_f64_i32_upper";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_F64_I64:
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return "cvtmax_f64_i64";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_I32:
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return "cvtmax_i32";
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case NamedVectorConstant::NAMED_VECTOR_CVTMAX_I64:
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return "cvtmax_i64";
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default:
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return "<Unknown Named Vector Constant>";
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}
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// clang-format on
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}();
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, IndexNamedVectorConstant Arg) {
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*out << [Arg] {
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// clang-format off
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switch (Arg) {
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case IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFLW:
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return "pshuflw";
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case IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFHW:
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return "pshufhw";
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case IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PSHUFD:
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return "pshufd";
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case IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_SHUFPS:
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return "shufps";
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case IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPS_MASK:
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return "dpps_mask";
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case IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_DPPD_MASK:
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return "dppd_mask";
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case IndexNamedVectorConstant::INDEXED_NAMED_VECTOR_PBLENDW:
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return "pblendw";
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default:
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return "<Unknown Indexed Named Vector Constant>";
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}
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// clang-format on
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}();
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, FEXCore::IR::OpSize Arg) {
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switch (Arg) {
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case OpSize::i8Bit: *out << "i8"; break;
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case OpSize::i16Bit: *out << "i16"; break;
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case OpSize::i32Bit: *out << "i32"; break;
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case OpSize::i64Bit: *out << "i64"; break;
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case OpSize::i128Bit: *out << "i128"; break;
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case OpSize::i256Bit: *out << "i256"; break;
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case OpSize::f80Bit: *out << "f80"; break;
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default: *out << "<Unknown OpSize Type>"; break;
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}
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, FEXCore::IR::FloatCompareOp Arg) {
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switch (Arg) {
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case FloatCompareOp::EQ: *out << "FEQ"; break;
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case FloatCompareOp::LT: *out << "FLT"; break;
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case FloatCompareOp::LE: *out << "FLE"; break;
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case FloatCompareOp::UNO: *out << "UNO"; break;
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case FloatCompareOp::NEQ: *out << "NEQ"; break;
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case FloatCompareOp::ORD: *out << "ORD"; break;
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default: *out << "<Unknown OpSize Type>"; break;
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}
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, FEXCore::IR::BreakDefinition Arg) {
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*out << "{" << Arg.ErrorRegister << ".";
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*out << static_cast<uint32_t>(Arg.Signal) << ".";
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*out << static_cast<uint32_t>(Arg.TrapNumber) << ".";
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*out << static_cast<uint32_t>(Arg.si_code) << "}";
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, FEXCore::IR::ShiftType Arg) {
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switch (Arg) {
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case ShiftType::LSL: *out << "LSL"; break;
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case ShiftType::LSR: *out << "LSR"; break;
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case ShiftType::ASR: *out << "ASR"; break;
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case ShiftType::ROR: *out << "ROR"; break;
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default: *out << "<Unknown Shift Type>"; break;
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}
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, FEXCore::IR::BranchHint Arg) {
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switch (Arg) {
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case BranchHint::None: *out << "None"; break;
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case BranchHint::Call: *out << "Call"; break;
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case BranchHint::Return: *out << "Return"; break;
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default: *out << "<Unknown Branch Hint>"; break;
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}
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}
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static void PrintArg(fextl::stringstream* out, const IRListView*, const std::array<uint8_t, 0x10>& Arg) {
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*out << fextl::fmt::format("{:02x}", fmt::join(Arg, ""));
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}
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void Dump(fextl::stringstream* out, const IRListView* IR) {
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auto HeaderOp = IR->GetHeader();
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int8_t CurrentIndent = 0;
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auto AddIndent = [&out, &CurrentIndent]() {
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for (uint8_t i = 0; i < CurrentIndent; ++i) {
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*out << "\t";
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}
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};
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++CurrentIndent;
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AddIndent();
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*out << fextl::fmt::format("(%0) IRHeader %{}, #{:#x}, #{}, #{}\n", HeaderOp->Blocks.ID(), HeaderOp->OriginalRIP, HeaderOp->BlockCount,
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HeaderOp->NumHostInstructions);
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for (auto [BlockNode, BlockHeader] : IR->GetBlocks()) {
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{
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auto BlockIROp = BlockHeader->C<FEXCore::IR::IROp_CodeBlock>();
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AddIndent();
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*out << "(%" << IR->GetID(BlockNode) << ") "
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<< "CodeBlock ";
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*out << "%" << BlockIROp->Begin.ID() << ", ";
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*out << "%" << BlockIROp->Last.ID() << std::endl;
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}
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++CurrentIndent;
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for (auto [CodeNode, IROp] : IR->GetCode(BlockNode)) {
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const auto ID = IR->GetID(CodeNode);
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const auto Name = FEXCore::IR::GetName(IROp->Op);
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{
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AddIndent();
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if (GetHasDest(IROp->Op)) {
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auto ElementSize = IROp->ElementSize;
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uint8_t NumElements = 0;
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if (IROp->ElementSize != OpSize::iUnsized) {
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ElementSize = IROp->Size;
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}
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if (ElementSize != OpSize::iUnsized) {
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NumElements = IR::NumElements(IROp->Size, ElementSize);
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}
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*out << "%" << std::dec << ID;
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auto PhyReg = PhysicalRegister(CodeNode);
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if (!PhyReg.IsInvalid()) {
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switch (PhyReg.Class) {
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case FEXCore::IR::GPRClass.Val: *out << "(r"; break;
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case FEXCore::IR::GPRFixedClass.Val: *out << "(R"; break;
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case FEXCore::IR::FPRClass.Val: *out << "(v"; break;
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case FEXCore::IR::FPRFixedClass.Val: *out << "(V"; break;
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case FEXCore::IR::ComplexClass.Val: *out << "(complex"; break;
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case FEXCore::IR::InvalidClass.Val: *out << "(invalid"; break;
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default: *out << "(unknown"; break;
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}
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if (PhyReg.Class != FEXCore::IR::InvalidClass.Val) {
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*out << std::dec << (uint32_t)PhyReg.Reg << ")";
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} else {
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*out << ")";
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}
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}
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*out << " i" << std::dec << IR::OpSizeAsBits(ElementSize);
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if (NumElements > 1) {
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*out << "v" << std::dec << NumElements;
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}
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*out << " = ";
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} else {
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auto ElementSize = IROp->ElementSize;
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if (IROp->ElementSize == OpSize::iUnsized) {
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ElementSize = IROp->Size;
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}
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uint32_t NumElements = 0;
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if (ElementSize != OpSize::iUnsized) {
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NumElements = IR::NumElements(IROp->Size, ElementSize);
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}
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*out << "(%" << std::dec << ID << ' ';
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*out << 'i' << std::dec << IR::OpSizeAsBits(ElementSize);
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if (NumElements > 1) {
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*out << 'v' << std::dec << NumElements;
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}
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*out << ") ";
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}
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*out << Name;
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#define IROP_ARGPRINTER_HELPER
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#include <FEXCore/IR/IRDefines.inc>
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default: *out << "<Unknown Args>"; break;
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}
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//*out << " (" << std::dec << CodeNode->GetUses() << ")";
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*out << "\n";
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}
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}
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CurrentIndent = std::max(0, CurrentIndent - 1);
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}
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}
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}
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