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FEX-Emu--FEX/unittests/InstructionCountCI/Atomics.json
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Alyssa Rosenzweig 27c8bf3021 InstCountCI: explicitly disable AFP everywhere 
(except for when we explicitly enable AFP).

Since AFP gets saved/restored, we get `msr fpcr` garbage in random instructions
when AFP is enabled. Explicitly disable everywhere since it's not worth our time
to triage which files might hit that path. Fixes instcountci on AFP-supporting
hosts now that we have AFP enabled.

Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
2024-06-18 11:40:20 -04:00

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{
"Features": {
"Bitness": 64,
"EnabledHostFeatures": [],
"DisabledHostFeatures": [
"SVE128",
"SVE256",
"AFP",
"FLAGM",
"FLAGM2"
]
},
"Instructions": {
"lock add byte [rax], cl": {
"ExpectedInstructionCount": 5,
"Comment": "0x00",
"ExpectedArm64ASM": [
"ldaddalb w5, w20, [x4]",
"eor w27, w20, w5",
"lsl w0, w20, #24",
"cmn w0, w5, lsl #24",
"add w26, w20, w5"
]
},
"lock add word [rax], cx": {
"ExpectedInstructionCount": 5,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddalh w5, w20, [x4]",
"eor w27, w20, w5",
"lsl w0, w20, #16",
"cmn w0, w5, lsl #16",
"add w26, w20, w5"
]
},
"lock add dword [rax], ecx": {
"ExpectedInstructionCount": 3,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddal w5, w20, [x4]",
"eor w27, w20, w5",
"adds w26, w20, w5"
]
},
"lock or byte [rax], cl": {
"ExpectedInstructionCount": 3,
"Comment": "0x08",
"ExpectedArm64ASM": [
"ldsetalb w5, w20, [x4]",
"orr w26, w20, w5",
"cmn wzr, w26, lsl #24"
]
},
"lock or word [rax], cx": {
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetalh w5, w20, [x4]",
"orr w26, w20, w5",
"cmn wzr, w26, lsl #16"
]
},
"lock or dword [rax], ecx": {
"ExpectedInstructionCount": 3,
"Comment": "0x09",
"ExpectedArm64ASM": [
"ldsetal w5, w20, [x4]",
"orr w26, w20, w5",
"tst w26, w26"
]
},
"lock adc byte [rax], cl": {
"ExpectedInstructionCount": 18,
"Comment": "0x10",
"ExpectedArm64ASM": [
"adc w20, wzr, w5",
"ldaddalb w20, w20, [x4]",
"eor w27, w20, w5",
"uxtb w21, w5",
"adc w22, wzr, w21",
"add w23, w20, w22",
"uxtb w26, w23",
"cmp w26, w22",
"cset x22, lo",
"cmn wzr, w26, lsl #24",
"mrs x23, nzcv",
"orr w22, w23, w22, lsl #29",
"eor w21, w20, w21",
"eor w20, w26, w20",
"bic w20, w20, w21",
"ubfx x20, x20, #7, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock adc word [rax], cx": {
"ExpectedInstructionCount": 18,
"Comment": "0x11",
"ExpectedArm64ASM": [
"adc w20, wzr, w5",
"ldaddalh w20, w20, [x4]",
"eor w27, w20, w5",
"uxth w21, w5",
"adc w22, wzr, w21",
"add w23, w20, w22",
"uxth w26, w23",
"cmp w26, w22",
"cset x22, lo",
"cmn wzr, w26, lsl #16",
"mrs x23, nzcv",
"orr w22, w23, w22, lsl #29",
"eor w21, w20, w21",
"eor w20, w26, w20",
"bic w20, w20, w21",
"ubfx x20, x20, #15, #1",
"orr w20, w22, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock adc dword [rax], ecx": {
"ExpectedInstructionCount": 4,
"Comment": "0x11",
"ExpectedArm64ASM": [
"adc w20, wzr, w5",
"ldaddal w20, w20, [x4]",
"eor w27, w20, w5",
"adcs w26, w20, w5"
]
},
"lock sbb byte [rax], cl": {
"ExpectedInstructionCount": 20,
"Comment": "0x18",
"ExpectedArm64ASM": [
"adc w20, wzr, w5",
"neg w1, w20",
"ldaddalb w1, w20, [x4]",
"eor w27, w20, w5",
"uxtb w20, w20",
"cset w21, hs",
"sub w21, w20, w21",
"sub w22, w21, w5",
"uxtb w26, w22",
"cmp w21, w26",
"cset x21, lo",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w5",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb word [rax], cx": {
"ExpectedInstructionCount": 20,
"Comment": "0x19",
"ExpectedArm64ASM": [
"adc w20, wzr, w5",
"neg w1, w20",
"ldaddalh w1, w20, [x4]",
"eor w27, w20, w5",
"uxth w20, w20",
"cset w21, hs",
"sub w21, w20, w21",
"sub w22, w21, w5",
"uxth w26, w22",
"cmp w21, w26",
"cset x21, lo",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, w5",
"eor w20, w26, w20",
"and w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb dword [rax], ecx": {
"ExpectedInstructionCount": 11,
"Comment": "0x19",
"ExpectedArm64ASM": [
"adc w20, wzr, w5",
"neg w1, w20",
"ldaddal w1, w20, [x4]",
"eor w27, w20, w5",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs w26, w20, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock and byte [rax], cl": {
"ExpectedInstructionCount": 4,
"Comment": "0x20",
"ExpectedArm64ASM": [
"mvn w1, w5",
"ldclralb w1, w20, [x4]",
"and w26, w20, w5",
"cmn wzr, w26, lsl #24"
]
},
"lock and word [rax], cx": {
"ExpectedInstructionCount": 4,
"Comment": "0x21",
"ExpectedArm64ASM": [
"mvn w1, w5",
"ldclralh w1, w20, [x4]",
"and w26, w20, w5",
"cmn wzr, w26, lsl #16"
]
},
"lock and dword [rax], ecx": {
"ExpectedInstructionCount": 3,
"Comment": "0x21",
"ExpectedArm64ASM": [
"mvn w1, w5",
"ldclral w1, w20, [x4]",
"ands w26, w20, w5"
]
},
"lock sub byte [rax], cl": {
"ExpectedInstructionCount": 9,
"Comment": "0x28",
"ExpectedArm64ASM": [
"neg w1, w5",
"ldaddalb w1, w20, [x4]",
"eor w27, w20, w5",
"lsl w0, w20, #24",
"cmp w0, w5, lsl #24",
"sub w26, w20, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub word [rax], cx": {
"ExpectedInstructionCount": 9,
"Comment": "0x28",
"ExpectedArm64ASM": [
"neg w1, w5",
"ldaddalh w1, w20, [x4]",
"eor w27, w20, w5",
"lsl w0, w20, #16",
"cmp w0, w5, lsl #16",
"sub w26, w20, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub dword [rax], ecx": {
"ExpectedInstructionCount": 7,
"Comment": "0x29",
"ExpectedArm64ASM": [
"neg w1, w5",
"ldaddal w1, w20, [x4]",
"eor w27, w20, w5",
"subs w26, w20, w5",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock xor byte [rax], cl": {
"ExpectedInstructionCount": 3,
"Comment": "0x30",
"ExpectedArm64ASM": [
"ldeoralb w5, w20, [x4]",
"eor w26, w20, w5",
"cmn wzr, w26, lsl #24"
]
},
"lock xor word [rax], cx": {
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoralh w5, w20, [x4]",
"eor w26, w20, w5",
"cmn wzr, w26, lsl #16"
]
},
"lock xor dword [rax], ecx": {
"ExpectedInstructionCount": 3,
"Comment": "0x31",
"ExpectedArm64ASM": [
"ldeoral w5, w20, [x4]",
"eor w26, w20, w5",
"tst w26, w26"
]
},
"lock add qword [rax], rcx": {
"ExpectedInstructionCount": 3,
"Comment": "0x01",
"ExpectedArm64ASM": [
"ldaddal x5, x20, [x4]",
"eor w27, w20, w5",
"adds x26, x20, x5"
]
},
"xchg byte [rax], cl": {
"ExpectedInstructionCount": 2,
"Comment": "0x86",
"ExpectedArm64ASM": [
"swpalb w5, w20, [x4]",
"bfxil x5, x20, #0, #8"
]
},
"xchg word [rax], cx": {
"ExpectedInstructionCount": 2,
"Comment": "0x87",
"ExpectedArm64ASM": [
"swpalh w5, w20, [x4]",
"bfxil x5, x20, #0, #16"
]
},
"xchg dword [rax], ecx": {
"ExpectedInstructionCount": 1,
"Comment": "0x87",
"ExpectedArm64ASM": [
"swpal w5, w5, [x4]"
]
},
"xchg qword [rax], rcx": {
"ExpectedInstructionCount": 1,
"Comment": "0x87",
"ExpectedArm64ASM": [
"swpal x5, x5, [x4]"
]
},
"xadd byte [rax], bl": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xc0",
"ExpectedArm64ASM": [
"uxtb w20, w7",
"ldaddalb w20, w21, [x4]",
"eor w27, w21, w20",
"lsl w0, w21, #24",
"cmn w0, w20, lsl #24",
"add w26, w21, w20",
"bfxil x7, x21, #0, #8"
]
},
"xadd word [rax], bx": {
"ExpectedInstructionCount": 7,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"uxth w20, w7",
"ldaddalh w20, w21, [x4]",
"eor w27, w21, w20",
"lsl w0, w21, #16",
"cmn w0, w20, lsl #16",
"add w26, w21, w20",
"bfxil x7, x21, #0, #16"
]
},
"xadd dword [rax], ebx": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"mov w20, w7",
"ldaddal w20, w7, [x4]",
"eor w27, w7, w20",
"adds w26, w7, w20"
]
},
"xadd qword [rax], rbx": {
"ExpectedInstructionCount": 4,
"Comment": "0x0f 0xc1",
"ExpectedArm64ASM": [
"ldaddal x7, x20, [x4]",
"eor w27, w20, w7",
"adds x26, x20, x7",
"mov x7, x20"
]
},
"lock add byte [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalb w20, w27, [x4]",
"lsl w0, w27, #24",
"cmn w0, w20, lsl #24",
"add w26, w27, #0x1 (1)"
]
},
"lock add byte [rax], 0xFF": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x80 /0",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"ldaddalb w20, w21, [x4]",
"mvn w27, w21",
"lsl w0, w21, #24",
"cmn w0, w20, lsl #24",
"add w26, w21, #0xff (255)"
]
},
"lock add word [rax], 0x100": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldaddalh w20, w27, [x4]",
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16",
"add w26, w27, #0x100 (256)"
]
},
"lock add word [rax], 0xFFFF": {
"ExpectedInstructionCount": 6,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"ldaddalh w20, w21, [x4]",
"mvn w27, w21",
"lsl w0, w21, #16",
"cmn w0, w20, lsl #16",
"add w26, w21, w20"
]
},
"lock add dword [rax], 0x100": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldaddal w20, w27, [x4]",
"adds w26, w27, #0x100 (256)"
]
},
"lock add dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldaddal w20, w21, [x4]",
"mvn w27, w21",
"adds w26, w21, w20"
]
},
"lock add qword [rax], 0x100": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldaddal x20, x27, [x4]",
"adds x26, x27, #0x100 (256)"
]
},
"lock add qword [rax], -2147483647": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x81 /0",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldaddal x20, x27, [x4]",
"adds x26, x27, x20"
]
},
"lock add word [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalh w20, w27, [x4]",
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16",
"add w26, w27, #0x1 (1)"
]
},
"lock add dword [rax], 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal w20, w27, [x4]",
"adds w26, w27, #0x1 (1)"
]
},
"lock add qword [rax], 1": {
"ExpectedInstructionCount": 3,
"Comment": "GROUP1 0x83 /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal x20, x27, [x4]",
"adds x26, x27, #0x1 (1)"
]
},
"lock or byte [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x80 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetalb w20, w20, [x4]",
"orr w26, w20, #0x1",
"cmn wzr, w26, lsl #24"
]
},
"lock or byte [rax], 0xFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x80 /1",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"ldsetalb w20, w20, [x4]",
"orr w26, w20, #0xff",
"cmn wzr, w26, lsl #24"
]
},
"lock or word [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetalh w20, w20, [x4]",
"orr w26, w20, #0x100",
"cmn wzr, w26, lsl #16"
]
},
"lock or word [rax], 0xFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"ldsetalh w20, w20, [x4]",
"orr w26, w20, #0xffff",
"cmn wzr, w26, lsl #16"
]
},
"lock or dword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal w20, w20, [x4]",
"orr w26, w20, #0x100",
"tst w26, w26"
]
},
"lock or dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldsetal w20, w21, [x4]",
"orr w26, w21, w20",
"tst w26, w26"
]
},
"lock or qword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0x100",
"tst x26, x26"
]
},
"lock or qword [rax], -2147483647": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0xffffffff80000001",
"tst x26, x26"
]
},
"lock or word [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetalh w20, w20, [x4]",
"orr w26, w20, #0x1",
"cmn wzr, w26, lsl #16"
]
},
"lock or dword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal w20, w20, [x4]",
"orr w26, w20, #0x1",
"tst w26, w26"
]
},
"lock or qword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldsetal x20, x20, [x4]",
"orr x26, x20, #0x1",
"tst x26, x26"
]
},
"lock adc byte [rax], 1": {
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w20, wzr, w20",
"ldaddalb w20, w27, [x4]",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w27, w20",
"uxtb w26, w21",
"cmp w26, w20",
"cset x20, lo",
"cmn wzr, w26, lsl #24",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w27, #0x1",
"eor w22, w26, w27",
"bic w21, w22, w21",
"ubfx x21, x21, #7, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock adc byte [rax], 0xFF": {
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x80 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"adc w20, wzr, w20",
"ldaddalb w20, w20, [x4]",
"mvn w27, w20",
"mov w21, #0xff",
"adc w21, wzr, w21",
"add w22, w20, w21",
"uxtb w26, w22",
"cmp w26, w21",
"cset x21, lo",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0xff",
"eor w20, w26, w20",
"bic w20, w20, w22",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock adc word [rax], 0x100": {
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adc w20, wzr, w20",
"ldaddalh w20, w27, [x4]",
"mov w20, #0x100",
"adc w20, wzr, w20",
"add w21, w27, w20",
"uxth w26, w21",
"cmp w26, w20",
"cset x20, lo",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w27, #0x100",
"eor w22, w26, w27",
"bic w21, w22, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock adc word [rax], 0xFFFF": {
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"adc w20, wzr, w20",
"ldaddalh w20, w20, [x4]",
"mvn w27, w20",
"mov w21, #0xffff",
"adc w21, wzr, w21",
"add w22, w20, w21",
"uxth w26, w22",
"cmp w26, w21",
"cset x21, lo",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"eor w22, w20, #0xffff",
"eor w20, w26, w20",
"bic w20, w20, w22",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock adc dword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adc w21, wzr, w20",
"ldaddal w21, w27, [x4]",
"adcs w26, w27, w20"
]
},
"lock adc dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"adc w21, wzr, w20",
"ldaddal w21, w21, [x4]",
"mvn w27, w21",
"adcs w26, w21, w20"
]
},
"lock adc qword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adc x21, xzr, x20",
"ldaddal x21, x27, [x4]",
"adcs x26, x27, x20"
]
},
"lock adc qword [rax], -2147483647": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"adc x21, xzr, x20",
"ldaddal x21, x27, [x4]",
"adcs x26, x27, x20"
]
},
"lock adc word [rax], 1": {
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w20, wzr, w20",
"ldaddalh w20, w27, [x4]",
"mov w20, #0x1",
"adc w20, wzr, w20",
"add w21, w27, w20",
"uxth w26, w21",
"cmp w26, w20",
"cset x20, lo",
"cmn wzr, w26, lsl #16",
"mrs x21, nzcv",
"orr w20, w21, w20, lsl #29",
"eor w21, w27, #0x1",
"eor w22, w26, w27",
"bic w21, w22, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock adc dword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w21, wzr, w20",
"ldaddal w21, w27, [x4]",
"adcs w26, w27, w20"
]
},
"lock adc qword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /2",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc x21, xzr, x20",
"ldaddal x21, x27, [x4]",
"adcs x26, x27, x20"
]
},
"lock sbb byte [rax], 1": {
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w20, wzr, w20",
"neg w1, w20",
"ldaddalb w1, w27, [x4]",
"uxtb w20, w27",
"cset w21, hs",
"sub w21, w20, w21",
"sub w22, w21, #0x1 (1)",
"uxtb w26, w22",
"cmp w21, w26",
"cset x21, lo",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"bic w20, w20, w26",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb byte [rax], 0xFF": {
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x80 /3",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"adc w20, wzr, w20",
"neg w1, w20",
"ldaddalb w1, w20, [x4]",
"mvn w27, w20",
"uxtb w20, w20",
"cset w21, hs",
"sub w21, w20, w21",
"sub w22, w21, #0xff (255)",
"uxtb w26, w22",
"cmp w21, w26",
"cset x21, lo",
"cmn wzr, w26, lsl #24",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"bic w20, w26, w20",
"ubfx x20, x20, #7, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb word [rax], 0x100": {
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adc w20, wzr, w20",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"uxth w20, w27",
"cset w21, hs",
"sub w21, w20, w21",
"sub w22, w21, #0x100 (256)",
"uxth w26, w22",
"cmp w21, w26",
"cset x21, lo",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"bic w20, w20, w26",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb word [rax], 0xFFFF": {
"ExpectedInstructionCount": 19,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddalh w1, w21, [x4]",
"mvn w27, w21",
"uxth w21, w21",
"cset w22, hs",
"sub w22, w21, w22",
"sub w20, w22, w20",
"uxth w26, w20",
"cmp w22, w26",
"cset x20, lo",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w20, w22, w20, lsl #29",
"bic w21, w26, w21",
"ubfx x21, x21, #15, #1",
"orr w20, w20, w21, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb dword [rax], 0x100": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddal w1, w27, [x4]",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs w26, w27, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 12,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddal w1, w21, [x4]",
"mvn w27, w21",
"mrs x22, nzcv",
"eor w22, w22, #0x20000000",
"msr nzcv, x22",
"sbcs w26, w21, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb qword [rax], 0x100": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"adc x21, xzr, x20",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs x26, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb qword [rax], -2147483647": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x81 /3",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"adc x21, xzr, x20",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs x26, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb word [rax], 1": {
"ExpectedInstructionCount": 18,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w20, wzr, w20",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"uxth w20, w27",
"cset w21, hs",
"sub w21, w20, w21",
"sub w22, w21, #0x1 (1)",
"uxth w26, w22",
"cmp w21, w26",
"cset x21, lo",
"cmn wzr, w26, lsl #16",
"mrs x22, nzcv",
"orr w21, w22, w21, lsl #29",
"bic w20, w20, w26",
"ubfx x20, x20, #15, #1",
"orr w20, w21, w20, lsl #28",
"msr nzcv, x20"
]
},
"lock sbb dword [rax], 1": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc w21, wzr, w20",
"neg w1, w21",
"ldaddal w1, w27, [x4]",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs w26, w27, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sbb qword [rax], 1": {
"ExpectedInstructionCount": 11,
"Comment": "GROUP1 0x83 /3",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"adc x21, xzr, x20",
"neg x1, x21",
"ldaddal x1, x27, [x4]",
"mrs x21, nzcv",
"eor w21, w21, #0x20000000",
"msr nzcv, x21",
"sbcs x26, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock and byte [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x80 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn w1, w20",
"ldclralb w1, w20, [x4]",
"and w26, w20, #0x1",
"cmn wzr, w26, lsl #24"
]
},
"lock and byte [rax], 0xFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x80 /4",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"mvn w1, w20",
"ldclralb w1, w20, [x4]",
"and w26, w20, #0xff",
"cmn wzr, w26, lsl #24"
]
},
"lock and word [rax], 0x100": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mvn w1, w20",
"ldclralh w1, w20, [x4]",
"and w26, w20, #0x100",
"cmn wzr, w26, lsl #16"
]
},
"lock and word [rax], 0xFFFF": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"mvn w1, w20",
"ldclralh w1, w20, [x4]",
"and w26, w20, #0xffff",
"cmn wzr, w26, lsl #16"
]
},
"lock and dword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mvn w1, w20",
"ldclral w1, w20, [x4]",
"ands w26, w20, #0x100"
]
},
"lock and dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"mvn w1, w20",
"ldclral w1, w21, [x4]",
"ands w26, w21, w20"
]
},
"lock and qword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"mvn x1, x20",
"ldclral x1, x20, [x4]",
"ands x26, x20, #0x100"
]
},
"lock and qword [rax], -2147483647": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /4",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"mvn x1, x20",
"ldclral x1, x20, [x4]",
"ands x26, x20, #0xffffffff80000001"
]
},
"lock and word [rax], 1": {
"ExpectedInstructionCount": 5,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn w1, w20",
"ldclralh w1, w20, [x4]",
"and w26, w20, #0x1",
"cmn wzr, w26, lsl #16"
]
},
"lock and dword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn w1, w20",
"ldclral w1, w20, [x4]",
"ands w26, w20, #0x1"
]
},
"lock and qword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /4",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mvn x1, x20",
"ldclral x1, x20, [x4]",
"ands x26, x20, #0x1"
]
},
"lock sub byte [rax], 1": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalb w1, w27, [x4]",
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
"sub w26, w27, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub byte [rax], 0xFF": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP1 0x80 /5",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"neg w1, w20",
"ldaddalb w1, w21, [x4]",
"mvn w27, w21",
"lsl w0, w21, #24",
"cmp w0, w20, lsl #24",
"sub w26, w21, #0xff (255)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub word [rax], 0x100": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
"sub w26, w27, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub word [rax], 0xFFFF": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"neg w1, w20",
"ldaddalh w1, w21, [x4]",
"mvn w27, w21",
"lsl w0, w21, #16",
"cmp w0, w20, lsl #16",
"sub w26, w21, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub dword [rax], 0x100": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"neg w1, w20",
"ldaddal w1, w27, [x4]",
"subs w26, w27, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 8,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"neg w1, w20",
"ldaddal w1, w21, [x4]",
"mvn w27, w21",
"subs w26, w21, w20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub qword [rax], 0x100": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"subs x26, x27, #0x100 (256)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub qword [rax], -2147483647": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x81 /5",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"subs x26, x27, x20",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub word [rax], 1": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddalh w1, w27, [x4]",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
"sub w26, w27, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub dword [rax], 1": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg w1, w20",
"ldaddal w1, w27, [x4]",
"subs w26, w27, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock sub qword [rax], 1": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP1 0x83 /5",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"neg x1, x20",
"ldaddal x1, x27, [x4]",
"subs x26, x27, #0x1 (1)",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock xor byte [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x80 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoralb w20, w20, [x4]",
"eor w26, w20, #0x1",
"cmn wzr, w26, lsl #24"
]
},
"lock xor byte [rax], 0xFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x80 /6",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"ldeoralb w20, w20, [x4]",
"eor w26, w20, #0xff",
"cmn wzr, w26, lsl #24"
]
},
"lock xor word [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoralh w20, w20, [x4]",
"eor w26, w20, #0x100",
"cmn wzr, w26, lsl #16"
]
},
"lock xor word [rax], 0xFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"ldeoralh w20, w20, [x4]",
"eor w26, w20, #0xffff",
"cmn wzr, w26, lsl #16"
]
},
"lock xor dword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral w20, w20, [x4]",
"eor w26, w20, #0x100",
"tst w26, w26"
]
},
"lock xor dword [rax], 0xFFFFFFFF": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldeoral w20, w21, [x4]",
"eor w26, w21, w20",
"tst w26, w26"
]
},
"lock xor qword [rax], 0x100": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov w20, #0x100",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0x100",
"tst x26, x26"
]
},
"lock xor qword [rax], -2147483647": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x81 /6",
"ExpectedArm64ASM": [
"mov x20, #0xffffffff80000001",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0xffffffff80000001",
"tst x26, x26"
]
},
"lock xor word [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoralh w20, w20, [x4]",
"eor w26, w20, #0x1",
"cmn wzr, w26, lsl #16"
]
},
"lock xor dword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral w20, w20, [x4]",
"eor w26, w20, #0x1",
"tst w26, w26"
]
},
"lock xor qword [rax], 1": {
"ExpectedInstructionCount": 4,
"Comment": "GROUP1 0x83 /6",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldeoral x20, x20, [x4]",
"eor x26, x20, #0x1",
"tst x26, x26"
]
},
"lock dec byte [rax]": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP3 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov w21, #0xff",
"ldaddalb w21, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #24",
"cmp w0, w20, lsl #24",
"sub w26, w27, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
"lock not byte [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf6 /2",
"ExpectedArm64ASM": [
"mov w20, #0xff",
"steorlb w20, [x4]"
]
},
"lock not word [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffff",
"steorlh w20, [x4]"
]
},
"lock not dword [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"steorl w20, [x4]"
]
},
"lock not qword [rax]": {
"ExpectedInstructionCount": 2,
"Comment": "GROUP2 0xf7 /2",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"steorl x20, [x4]"
]
},
"lock neg byte [rax]": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xf6 /3",
"ExpectedArm64ASM": [
"ldaxrb w1, [x4]",
"neg w2, w1",
"stlxrb w3, w2, [x4]",
"cbnz w3, #-0xc",
"mov w27, w1",
"cmp wzr, w27, lsl #24",
"neg w26, w27",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock neg word [rax]": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxrh w1, [x4]",
"neg w2, w1",
"stlxrh w3, w2, [x4]",
"cbnz w3, #-0xc",
"mov w27, w1",
"cmp wzr, w27, lsl #16",
"neg w26, w27",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock neg dword [rax]": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxr w1, [x4]",
"neg w2, w1",
"stlxr w3, w2, [x4]",
"cbnz w3, #-0xc",
"mov w27, w1",
"negs w26, w27",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock neg qword [rax]": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP2 0xf7 /3",
"ExpectedArm64ASM": [
"ldaxr x1, [x4]",
"neg x2, x1",
"stlxr w3, x2, [x4]",
"cbnz x3, #-0xc",
"mov x27, x1",
"negs x26, x27",
"mrs x20, nzcv",
"eor w20, w20, #0x20000000",
"msr nzcv, x20"
]
},
"lock dec word [rax]": {
"ExpectedInstructionCount": 10,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"mov w21, #0xffff",
"ldaddalh w21, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #16",
"cmp w0, w20, lsl #16",
"sub w26, w27, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
"lock dec dword [rax]": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov w20, #0xffffffff",
"ldaddal w20, w27, [x4]",
"cset w20, hs",
"subs w26, w27, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock dec qword [rax]": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /1",
"ExpectedArm64ASM": [
"mov x20, #0xffffffffffffffff",
"ldaddal x20, x27, [x4]",
"cset w20, hs",
"subs x26, x27, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock inc byte [rax]": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalb w20, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #24",
"cmn w0, w20, lsl #24",
"add w26, w27, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
"lock inc word [rax]": {
"ExpectedInstructionCount": 9,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddalh w20, w27, [x4]",
"cset w21, hs",
"lsl w0, w27, #16",
"cmn w0, w20, lsl #16",
"add w26, w27, #0x1 (1)",
"mrs x20, nzcv",
"bfi w20, w21, #29, #1",
"msr nzcv, x20"
]
},
"lock inc dword [rax]": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal w20, w27, [x4]",
"cset w20, hs",
"adds w26, w27, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
},
"lock inc qword [rax]": {
"ExpectedInstructionCount": 7,
"Comment": "GROUP4 0xfe /0",
"ExpectedArm64ASM": [
"mov w20, #0x1",
"ldaddal x20, x27, [x4]",
"cset w20, hs",
"adds x26, x27, #0x1 (1)",
"mrs x21, nzcv",
"bfi w21, w20, #29, #1",
"msr nzcv, x21"
]
}
}
}
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